19-1740; Rev 0; 6/00 Triple-Output TFT LCD DC-DC Converter Features ♦ Three Integrated DC-DC Converters ♦ 1MHz Current-Mode PWM Boost Regulator Up to +13V Main High-Power Output ±1% Accuracy High Efficiency (93%) ♦ Dual Charge-Pump Outputs Up to +40V Positive Charge-Pump Output Down to -40V Negative Charge-Pump Output ♦ Internal Supply Sequencing ♦ Internal Power MOSFETs ♦ +2.7V to +5.5V Input Supply ♦ 0.1µA Shutdown Current ♦ 0.6mA Quiescent Current ♦ Internal Soft-Start ♦ Power-Ready Output ♦ Ultra-Small External Components ♦ Thin TSSOP Package (1.1mm max) Ordering Information PART MAX1748EUE TEMP. RANGE PIN-PACKAGE -40°C to +85°C 16 TSSOP Pin Configuration ________________________Applications TFT Active Matrix LCD Displays Passive Matrix LCD Displays PDAs TOP VIEW 16 TGND RDY 1 FB 2 Digital Still Cameras Camcorders 15 LX INTG 3 IN 4 14 PGND MAX1748 13 SUPP GND 5 12 DRVP REF 6 11 SUPN FBP 7 10 DRVN FBN 8 9 SHDN TSSOP Typical Operating Circuit appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1748 General Description The MAX1748 triple-output DC-DC converter in a lowprofile TSSOP package provides the regulated voltages required by active matrix, thin-film transistor (TFT) liquid crystal displays (LCDs). One high-power DC-DC converter and two low-power charge pumps convert the +3.3V to +5V input supply voltage into three independent output voltages. The primary high-power DC-DC converter generates a boosted output voltage (VMAIN) up to 13V that is regulated within ±1%. The low-power BiCMOS control circuitry and the low on-resistance (0.35Ω) of the integrated power MOSFET allows efficiency up to 93%. The 1MHz current-mode PWM architecture provides fast transient response and allows the use of ultra-small inductors and ceramic capacitors. The dual charge pumps independently regulate one positive output (VPOS) and one negative output (VNEG). These low-power outputs use external diode and capacitor stages (as many stages as required) to regulate output voltages up to +40V and down to -40V. A proprietary regulation algorithm minimizes output ripple, as well as capacitor sizes for both charge pumps. The MAX1748 is available in the ultra-thin TSSOP package (1.1mm max height). MAX1748 Triple-Output TFT LCD DC-DC Converter ABSOLUTE MAXIMUM RATINGS IN, SHDN, TGND to GND .........................................-0.3V to +6V DRVN to GND .........................................-0.3V to (VSUPN + 0.3V) DRVP to GND..........................................-0.3V to (VSUPP + 0.3V) PGND to GND.....................................................................±0.3V RDY to GND ...........................................................-0.3V to +14V LX, SUPP, SUPN to PGND .....................................-0.3V to +14V INTG, REF, FB, FBN, FBP to GND ...............-0.3V to (VIN + 0.3V) Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 9.4mW/°C above +70°C) ..........755mW Operating Temperature Range MAX1748EUE .................................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = 10V, TGND = PGND = GND, CREF = 0.22µF, CINTG = 470pF, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Supply Range SYMBOL CONDITIONS VIN MIN TYP 2.7 2.2 MAX UNITS 5.5 V Input Undervoltage Threshold VUVLO VIN rising, 40mV hysteresis (typ) 2.4 2.6 V IN Quiescent Supply Current IIN VFB = VFBP = 1.5V, VFBN = -0.2V 0.6 1 mA SUPP Quiescent Current ISUPP VFBP = 1.5V 0.4 0.8 mA SUPN Quiescent Current ISUPN VFBN = -0.1V 0.4 0.8 mA IN Shutdown Current V SHDN = 0, VIN = 5V 0.1 10 µA SUPP Shutdown Current V SHDN = 0, VSUPP = 13V 0.1 10 µA SUPN Shutdown Current V SHDN = 0, VSUPN = 13V 0.1 10 µA 13 V 1.248 1.261 V 50 nA 0.85 1 1.15 MHz 78 85 90 % MAIN BOOST CONVERTER Output Voltage Range VMAIN FB Regulation Voltage VFB TA = 0°C to +85°C VIN FB Input Bias Current IFB VFB = 1.25V, INTG = GND Operating Frequency fOSC Oscillator Maximum Duty Cycle Load Regulation 1.235 -50 0.2 % Line Regulation 0.1 %/V Integrator Gm 320 µmho LX Switch On-Resistance LX Leakage Current IMAIN = 0 to 200mA, VMAIN = 10V RLX(ON) ILX ILX = 100mA 0.35 0.7 Ω VLX = 13V 0.01 20 µA 0.380 0.500 Phase I = soft-start (1.0ms) LX Current Limit ILX(MAX) 0.275 Phase II = soft-start (1.0ms) 0.75 Phase III = soft-start (1.0ms) 1.12 Phase IV = fully on (after 3.0ms) 1.1 Maximum RMS LX Current Soft-Start Period tSS FB Fault Trip Level POSITIVE CHARGE PUMP VSUPP Input Supply Range 2 Power-up to the end of Phase III 1.07 VSUPP 1.5 A 2.0 1 A 3072 / fOSC s 1.1 2.7 _______________________________________________________________________________________ 1.14 V 13 V Triple-Output TFT LCD DC-DC Converter (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = 10V, TGND = PGND = GND, CREF = 0.22µF, CINTG = 470pF, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN MAX 0.5 × fOSC Operating Frequency FBP Regulation Voltage FBP Input Bias Current DRVP PCH On-Resistance TYP VFBP IFBP VFBP = 1.5V 1.20 -50 VFBP = 1.213V DRVP NCH On-Resistance VFBP = 1.275V FBP Power-Ready Trip Level Rising edge FBP Fault Trip Level Falling edge Hz 1.25 1.30 50 V nA 3 10 Ω 1.5 4 20 1.091 Maximum RMS DRVP Current UNITS Ω kΩ 1.125 1.159 V 1.11 V 0.1 A NEGATIVE CHARGE PUMP VSUPN Input Supply Range VSUPN 2.7 Operating Frequency FBN Regulation Voltage FBN Input Bias Current 13 0.5 × fOSC VFBN IFBN VFBN = -0.05V -50 -50 DRVN PCH On-Resistance DRVN NCH On-Resistance VFBN = 0.035V VFBN = -0.025V 20 FBN Power-Ready Trip Level Rising edge 80 FBN Fault Trip Level Falling edge Maximum RMS DRVN Current V Hz 0 50 50 mV nA 3 1.5 10 4 Ω Ω kΩ 110 165 mV 130 mV 0.1 A REFERENCE Reference Voltage VREF Reference Undervoltage Threshold LOGIC SIGNALS -2µA < IREF < 50µA VREF rising SHDN Input Low Voltage 1.25 1.269 V 0.9 1.05 1.2 V 0.9 V 0.01 1 µA 0.4V hysteresis (typ) SHDN Input High Voltage SHDN Input Current 1.231 2.1 I SHDN V RDY Output Low Voltage ISINK = 2mA 0.25 0.5 V RDY Output High Voltage V RDY = 13V 0.01 1 µA _______________________________________________________________________________________ 3 MAX1748 ELECTRICAL CHARACTERISTICS (continued) MAX1748 Triple-Output TFT LCD DC-DC Converter ELECTRICAL CHARACTERISTICS (continued) (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = 10V, TGND = PGND = GND, CREF = 0.22µF, CINTG = 470pF, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER Input Supply Range SYMBOL CONDITIONS VIN Input Undervoltage Threshold VUVLO VIN rising, 40mV hysteresis (typ) IN Quiescent Supply Current IIN VFB = VFBP = 1.5V, VFBN = -0.2V MIN MAX UNITS 2.7 5.5 V 2.2 2.6 V 1 mA SUPP Quiescent Current ISUPP VFBP = 1.5V 0.8 mA SUPN Quiescent Current ISUPN VFBN = -0.1V 0.8 mA IN Shutdown Current V SHDN = 0, VIN = 5V 10 µA SUPP Shutdown Current V SHDN = 0, VSUPP = 13V 10 µA SUPN Shutdown Current V SHDN = 0, VSUPN = 13V 10 µA VIN 13 V 1.225 1.271 V -50 50 nA 0.75 1.25 MHz 90 % MAIN BOOST CONVERTER Output Voltage Range VMAIN FB Regulation Voltage VFB FB Input Bias Current IFB Operating Frequency FOSC VFB = 1.25V, INTG = GND Oscillator Maximum Duty Cycle LX Switch On-Resistance 78 LX Leakage Current RLX(ON) ILX LX Current Limit ILX(MAX) ILX = 100mA 0.7 Ω VLX = 13V 20 µA Phase I = soft-start (1.0ms) Phase IV = fully on (after 3.0ms) FB Fault Trip Level 0.275 0.500 1.1 2.0 1.07 1.14 A V POSITIVE CHARGE PUMP SUPP Input Supply Range VSUPP 2.7 13 V FBP Regulation Voltage VFBP 1.20 1.30 V FBP Input Bias Current IFBP -50 50 nA 10 Ω VFBP = 1.5V DRVP PCH On-Resistance VFBP = 1.213V DRVP NCH On-Resistance VFBP = 1.275V FBP Power-Ready Trip Level Rising edge 4 20 Ω kΩ 1.091 1.159 V 2.7 13 V -50 50 mV -50 50 nA 10 Ω NEGATIVE CHARGE PUMP SUPN Input Supply Range FBN Regulation Voltage FBN Input Bias Current VSUPN VFBN IFBN VFBN = -0.05V DRVN PCH On-Resistance VFBN = 0.035V DRVN NCH On-Resistance FBN Power-Ready Trip Level 4 Ω VFBN = -0.025V 20 kΩ Rising edge 80 165 1.223 1.269 V 0.9 1.2 V mV REFERENCE Reference Voltage Reference Undervoltage 4 VREF -2µA < IREF < 50µA VREF rising _______________________________________________________________________________________ Triple-Output TFT LCD DC-DC Converter (VIN = +3.0V, SHDN = IN, VSUPP = VSUPN = 10V, TGND = PGND = GND, CREF = 0.22µF, CINTG = 470pF, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 0.9 V LOGIC SIGNALS SHDN Input Low Voltage 0.45V hysteresis (typ) SHDN Input High Voltage 2.1 V 1 µA RDY Output Low Voltage ISINK = 2mA 0.5 V RDY Output High Leakage V RDY = 13V 1 µA SHDN Input Current I SHDN Note 1: Specifications from 0°C to -40°C are guaranteed by design, not production tested. Typical Operating Characteristics (Circuit of Figure 5, VIN = 3.3V, TA = +25°C, unless otherwise noted.) VIN = 5.0V 90 EFFICIENCY (%) 9.98 VMAIN (V) 95 9.96 9.94 9.92 MAX1748toc03 10.00 VMAIN = 10V VMAIN = 8V 95 VIN = 5.0V 90 EFFICIENCY (%) VIN = 5.0V 100 MAX1748toc02 VIN = 3.3V 100 MAX1748 toc01 10.04 10.02 MAIN STEP-UP CONVERTER EFFICIENCY vs. LOAD CURRENT (BOOST ONLY) MAIN STEP-UP CONVERTER EFFICIENCY vs. LOAD CURRENT (BOOST ONLY) MAIN OUTPUT VOLTAGE vs. LOAD CURRENT 85 VIN = 3.3V 80 75 85 VIN = 3.3V 80 75 9.90 9.88 9.86 70 65 65 60 60 9.84 0 100 200 300 400 500 0 600 100 200 300 400 500 0 600 100 200 300 400 500 600 700 800 IMAIN (mA) IMAIN (mA) IMAIN (mA) EFFICIENCY vs. LOAD CURRENT (BOOST CONVERTER AND CHARGE PUMPS) NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT NEGATIVE CHARGE-PUMP EFFICIENCY vs. LOAD CURRENT VNEG = -5V -4.65 80 MAX1748toc06 85 -4.60 MAX1748toc05 VMAIN = 8V MAX1748toc04 90 VSUPN = 6V 70 -4.70 VMAIN = 10V 70 65 VSUPN = 6V -4.75 VNEG (V) 75 -4.80 -4.85 -4.90 60 VIN = 3.3V VNEG = -5V WITH INEG = 10mA VPOS = 15V WITH IPOS = 5mA 55 50 0 50 100 150 200 250 300 350 400 IMAIN (mA) EFFICIENCY (%) 80 EFFICIENCY (%) 70 VSUPN = 8V -4.95 VSUPN = 10V VSUPN = 8V 60 VSUPN = 10V 50 40 30 -5.00 VNEG = -5V 20 -5.05 0 5 10 15 20 INEG (mA) 25 30 35 40 0 5 10 15 20 25 30 35 40 INEG (mA) _______________________________________________________________________________________ 5 MAX1748 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (Circuit of Figure 5, VIN = 3.3V, TA = +25°C, unless otherwise noted.) POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. LOAD CURRENT -4 15.2 VPOS (V) -7 -8 INEG = 1mA -9 EFFICIENCY (%) 15.0 INEG = 20mA -6 VSUPN = 12V 14.9 VSUPN = 10V VSUPN = 8V 14.8 14.7 80 VSUPP = 10V 70 VSUPP = 12V 60 14.6 INEG = 10mA 50 -10 14.5 VNEG = -10mA -11 5 6 7 8 9 10 11 14.4 40 0 12 2 4 6 8 0 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20 IPOS (mA) MAXIMUM POSITIVE CHARGE-PUMP OUTPUT VOLTAGE vs. SUPPLY VOLTAGE SWITCHING FREQUENCY vs. INPUT VOLTAGE REFERENCE VOLTAGE vs. REFERENCE LOAD CURRENT IPOS = 10mA 20 18 IPOS = 1mA 16 14 IPOS = 20mA 12 1.20 1.15 1.10 MEASURED FROM THE FALLING EDGE OF LX VMAIN = 10V IMAIN = 100mA 1.254 1.05 1.00 VIN = 3.3V 1.252 VREF (V) VPOS = 22V 22 SWITCHING FREQUENCY (MHz) 24 MAX1748toc12 IPOS (mA) MAX1748toc10 VSUPN (V) MAX1748toc11 VNEG (V) VSUPP = 8V 90 15.1 -5 1.250 1.248 0.95 0.90 1.246 0.85 10 0.80 8 5 6 7 8 9 10 11 1.244 2.5 12 3.0 3.5 4.0 4.5 5.0 5.5 0 5 10 15 20 25 30 35 40 45 50 VSUPP (V) INPUT VOLTAGE (V) IREF (µA) RIPPLE WAVEFORMS LOAD-TRANSIENT RESPONSE LOAD-TRANSIENT RESPONSE WITHOUT INTEGRATOR VMAIN 10mV/div VNEG 10mV/div 1µs/div IMAIN 200mA/div IMAIN 200mA/div ILX 500mA/div ILX 500mA/div VMAIN 200mV/div VMAIN 200mV/div VPOS 10mV/div VMAIN = 10V, IMAIN = 200mA, VNEG = -5V, INEG = 10mA, VPOS = 15V, IPOS = 10mA MAX1748toc15 MAX1748 toc14 MAX1748toc13 6 100 MAX1748toc08 15.3 MAX1748toc07 -3 POSITIVE CHARGE-PUMP EFFICIENCY vs. LOAD CURRENT MAX1748toc09 MAXIMUM NEGATIVE CHARGE-PUMP OUTPUT VOLTAGE vs. SUPPLY VOLTAGE VPOS (V) MAX1748 Triple-Output TFT LCD DC-DC Converter 100µs/div VIN = 3.3V, VMAIN = 10V, RMAIN = 500Ω TO 50Ω (20mA TO 200mA) 100µs/div VIN = 3.3V, VMAIN = 10V, INTG = REF, RMAIN = 500Ω TO 50Ω (20mA TO 200mA) _______________________________________________________________________________________ Triple-Output TFT LCD DC-DC Converter MAIN BOOST STARTUP WAVEFORM WITH LOAD MAIN BOOST STARTUP WAVEFORM MAX1748toc16 VSHDN 2V/div 2V POWER-UP SEQUENCING MAX1748toc17 2V MAX1748toc18 VSHDN 2V/div VSHDN 2V/div VMAIN 5V/div VMAIN 5V/div ILX 500mA/div VNEG 5V/div VPOS 10V/div 0 0 VMAIN 5V/div 10V 10V 0 0 ILX 500mA/div 0 1ms/div 0 1ms/div 2ms/div VMAIN = 10V, RMAIN = 50Ω (200mA) RMAIN = 1kΩ, VMAIN = 10V VMAIN = 10V, VNEG = -5V, VPOS = 15V Pin Description PIN NAME FUNCTION 1 RDY Active-Low Open-Drain Output. Indicates all outputs are ready. The on-resistance is 125Ω (typ). 2 FB Main Boost Regulator Feedback Input. Regulates to 1.248V nominal. Connect feedback resistive divider to analog ground (GND). 3 INTG 4 IN 5 GND Analog Ground. Connect to power ground (PGND) underneath the IC. 6 REF Internal Reference Bypass Terminal. Connect a 0.22µF capacitor from this terminal to analog ground (GND). External load capability to 50µA. 7 FBP Positive Charge-Pump Regulator Feedback Input. Regulates to 1.25V nominal. Connect feedback resistive divider to analog ground (GND). 8 FBN Negative Charge-Pump Regulator Feedback Input. Regulates to 0V nominal. 9 SHDN Active-Low Logic-Level Shutdown Input. Connect SHDN to IN for normal operation. 10 DRVN Negative Charge-Pump Driver Output. Output high level is VSUPN, and low level is PGND. 11 SUPN Negative Charge-Pump Driver Supply Voltage. Bypass to PGND with a 0.1µF capacitor. 12 DRVP Positive Charge-Pump Driver Output. Output high level is VSUPP, and low level is PGND. Main Boost Integrator Output. If used, connect 470pF to analog ground (GND). To disable integrator, connect to REF. Supply Input. +2.7V to +5.5V input range. Bypass with a 0.1µF capacitor between IN and GND, as close to the pins as possible. _______________________________________________________________________________________ 7 MAX1748 Typical Operating Characteristics (continued) (Circuit of Figure 5, VIN = 3.3V, TA = +25°C, unless otherwise noted.) Triple-Output TFT LCD DC-DC Converter MAX1748 Pin Description (continued) PIN NAME FUNCTION 13 SUPP Positive Charge-Pump Driver Supply Voltage. Bypass to PGND with a 0.1µF capacitor. 14 PGND Power Ground. Connect to GND underneath the IC. 15 LX 16 TGND Main Boost Regulator Power MOSFET N-Channel Drain. Connect output diode and output capacitor as close to PGND as possible. Must be connected to ground. Detailed Description The MAX1748 is a highly efficient triple-output power supply for TFT LCD applications. The device contains one high-power step-up converter and two low-power charge pumps. The primary boost converter uses an internal N-channel MOSFET to provide maximum efficiency and to minimize the number of external components. The output voltage of the main boost converter (VMAIN) can be set from VIN to 13V with external resistors. The dual charge pumps independently regulate a positive output (VPOS) and a negative output (VNEG). These low-power outputs use external diode and capacitor stages (as many stages as required) to regulate output voltages up to +40V and down to -40V. A proprietary regulation algorithm minimizes output ripple as well as capacitor sizes for both charge pumps. Also included in the MAX1748 are a precision 1.25V reference that sources up to 50µA, logic shutdown, soft-start, power-up sequencing, fault detection, and an active-low open-drain ready output. Main Boost Converter The MAX1748 main step-up converter switches at a constant 1MHz internal oscillator frequency to allow the use of small inductors and output capacitors. The MOSFET switch pulse width is modulated to control the power transferred on each switching cycle and to regulate the output voltage. During PWM operation, the internal clock’s rising edge sets a flip-flop, which turns on the N-channel MOSFET (Figure 1). The switch turns off when the sum of the voltage-error, slope-compensation, and current-feedback signals trips the multi-input comparator and resets the flip-flop. The switch remains off for the rest of the clock cycle. Changes in the output voltage error signal shift the switch current trip level, consequently modulating the MOSFET duty cycle. 8 Dual Charge-Pump Regulator The MAX1748 contains two individual low-power charge pumps. One charge pump inverts the supply voltage (SUPN) and provides a regulated negative output voltage. The second charge pump doubles the supply voltage (SUPP) and provides a regulated positive output voltage. The MAX1748 contains internal P-channel and N-channel MOSFETs to control the power transfer. The internal MOSFETs switch at a constant 500kHz (0.5 ✕ fOSC). Negative Charge Pump During the first half-cycle, the P-channel MOSFET turns on and the flying capacitor C5 charges to VSUPN minus a diode drop (Figure 2). During the second half-cycle, the P-channel MOSFET turns off, and the N-channel MOSFET turns on, level shifting C5. This connects C5 in parallel with the reservoir capacitor C6. If the voltage across C6 minus a diode drop is lower than the voltage across C5, charge flows from C5 to C6 until the diode (D5) turns off. The amount of charge transferred to the output is controlled by the variable N-channel on-resistance. Positive Charge Pump During the first half-cycle, the N-channel MOSFET turns on and charges the flying capacitor C3 (Figure 3). This initial charge is controlled by the variable N-channel on-resistance. During the second half-cycle, the Nchannel MOSFET turns off and the P-channel MOSFET turns on, level shifting C3 by VSUPP volts. This connects C3 in parallel with the reservoir capacitor C4. If the voltage across C4 plus a diode drop (VPOS + VDIODE) is smaller than the level-shifted flying capacitor voltage (VC3 + VSUPP), charge flows from C3 to C4 until the diode (D3) turns off. Soft-Start For the main boost regulator, soft-start allows a gradual increase of the internal current-limit level during startup to reduce input surge currents. The MAX1748 divides _______________________________________________________________________________________ Triple-Output TFT LCD DC-DC Converter MAX1748 L1 VOUT = [1 + (R1 / R2)] x VREF VREF = 1.25V VIN = 2.7V TO 5.5V IN OSC LX S R VMAIN (UP TO 13V) D1 Q R1 + PGND C1 ILIM + RCOMP FB + - + Gm INTG CINTG REF + MAX1748 GND R2 C2 CCOMP 1.25V Figure 1. PWM Boost Converter Block Diagram the soft-start period into four phases. During phase 1, the MAX1748 limits the current limit to only 0.38A (see Electrical Characteristics), approximately a quarter of the maximum current limit (ILX(MAX)). If the output does not reach regulation within 1ms, soft-start enters phase II and the current limit is increased by another 25%. This process is repeated for phase III. The maximum 1.5A (typ) current limit is reached within 3.0ms or when the output reaches regulation, whichever occurs first (see the Startup Waveforms in the Typical Operating Characteristics). For the charge pumps, soft-start is achieved by controlling the rise rate of the output voltage. The output voltage regulates within 4ms, regardless of output capacitance and load, limited only by the regulator’s output impedance. Shutdown A logic-low level on SHDN disables all three MAX1748 converters and the reference. When shut down, supply current drops to 0.1µA to maximize battery life and the reference is pulled to ground. The output capacitance and load current determine the rate at which each output voltage will decay. A logic-level high on SHDN power activates the MAX1748 (see Power-Up Sequencing). Do not leave SHDN floating. If unused, connect SHDN to IN. Power-Up Sequencing Upon power-up or exiting shutdown, the MAX1748 starts a power-up sequence. First, the reference powers up. Then the main DC-DC step-up converter powers up with soft-start enabled. Once the main boost _______________________________________________________________________________________ 9 MAX1748 Triple-Output TFT LCD DC-DC Converter VSUPN = 2.7V TO 13V SUPN OSC D4 DRVN C5 D5 R5 FBN + VNEG C6 + R6 VREF 1.25V REF MAX1748 CREF 0.22µF PGND GND VPOS = (R5 / R6) x VREF VREF = 1.25V Figure 2. Negative Charge-Pump Block Diagram VSUPP = 2.7V TO 13V SUPP OSC D2 C3 DRVP D3 R3 FBP + VPOS C4 + - R4 VREF 1.25V MAX1748 GND PGND VPOS = [1 + (R3 / R4)] x VREF VREF = 1.25V Figure 3. Positive Charge-Pump Block Diagram 10 ______________________________________________________________________________________ Triple-Output TFT LCD DC-DC Converter Power Ready Power ready is an open-drain output. When the powerup sequence is properly completed, the MOSFET turns on and pulls RDY low with a typical 125Ω on-resistance. If a fault is detected, the internal open-drain MOSFET appears as a high impedance. Connect a 100kΩ pull-up resistor between RDY and IN for a logiclevel output. Fault Detection Once RDY is low and if any output falls below its faultdetection threshold, RDY goes high impedance. For the reference, the fault threshold is 1.05V. For the main boost converter, the fault threshold is 88% of its nominal value (VFB < 1.1V). For the negative charge pump, the fault threshold is approximately 90% of its nominal value (VFBN < 130mV). For the positive charge pump, the fault threshold is 88% of its nominal value (VFBP < 1.11V). Once an output faults, all outputs later in the power sequence shut down until the faulted output rises above its power-up threshold. For example, if the negative charge-pump output voltage falls below the fault detection threshold, the main boost converter remains active while the positive charge pump stops switching and its output voltage decays, depending on output capacitance and load. The positive charge-pump output will not power up until the negative charge-pump output voltage rises above its power-up threshold (see the Power-Up Sequencing section). Voltage Reference The voltage at REF is nominally 1.25V. The reference can source up to 50µA with good load regulation (see Typical Operating Characteristics). Connect a 0.22µF bypass capacitor between REF and GND. Design Procedure Main Boost Converter Output Voltage Selection Adjust the output voltage by connecting a voltage divider from the output (V MAIN ) to FB to GND (see Typical Operating Circuit). Select R2 in the 10kΩ to 20kΩ range. Higher resistor values improve efficiency at low output current but increase output voltage error due to the feedback input bias current. Calculate R1 with the following equations: R1 = R2 [(VMAIN / VREF) - 1] where VREF = 1.25V. VMAIN may range from VIN to 13V. Feedback Compensation For stability, add a pole-zero pair from FB to GND in the form of a series resistor (R COMP ) and capacitor (CCOMP). The resistor should be half the value of the R2 feedback resistor. Inductor Selection Inductor selection depends on input voltage, output voltage, maximum current, switching frequency, size, and availability of inductor values. Other factors can include efficiency and ripple voltage. Inductors are specified by their inductance (L), peak current (IPEAK), and resistance (RL). The following boost-circuit equations are useful in choosing inductor values based on the application. They allow the trading of peak current and inductor value while allowing for consideration of component availability and cost. The following equation includes a constant LIR, which is the ratio of the inductor peak-to-peak AC current to maximum average DC inductor current. A good compromise between the size of the inductor, loss, and output ripple is to choose an LIR of 0.3 to 0.5. The peak inductor current is then given by: IPEAK = IMAIN(MAX) × VMAIN Efficiency × VIN(MIN) [ ] × 1 + (LIR/2) The inductance value is then given by: 2 L= VIN(MIN) × Efficiency × (VMAIN − VIN(MIN) ) 2 V(MAIN) × LIR × IMAIN(MAX) × fOSC Considering the typical application circuit, the maximum DC load current (IMAIN(MAX)) is 200mA with a 10V output. A 6.8µH inductance value is then chosen, based on the above equations and using 85% efficiency and a 1MHz operating frequency. Smaller inductance values typically offer a smaller physical size for a given series resistance and current rating, allowing the smallest overall circuit dimensions. However, due to higher peak inductor currents, the output voltage ripple (IPEAK ✕ output filter capacitor ESR) will be higher. Use inductors with a ferrite core or equivalent; powder iron cores are not recommended for use with the MAX1748’s high switching frequencies. The inductor’s maximum current rating should exceed IPEAK. Under fault conditions, inductor current may reach up to 2.0A. ______________________________________________________________________________________ 11 MAX1748 converter reaches regulation, the negative charge pump turns on. When the negative output voltage reaches approximately 88% of its nominal value (VFBN < 110mV), the positive charge pump starts up. Finally, when the positive output voltage reaches 90% of its nominal value (VFBP > 1.125V), the active-low ready signal (RDY) goes low (see Power Ready section). MAX1748 Triple-Output TFT LCD DC-DC Converter The MAX1748’s fast current-limit circuitry allows the use of soft-saturation inductors while still protecting the IC. The inductor’s DC resistance significantly affects efficiency. For best performance, select inductors with resistance less than the internal N-channel FET resistance. To minimize radiated noise in sensitive applications, use a shielded inductor. The inductor should have as low a series resistance as possible. For continuous inductor current, the power loss in the inductor resistance, PLR, is approximated by: PLR ≅ (IMAIN ✕ VMAIN / VIN)2 ✕ RL where RL is the inductor series resistance. Output Capacitor A 10µF capacitor works well in most applications. The equivalent series resistance (ESR) of the output filter capacitor affects efficiency and output ripple. Output voltage ripple is largely the product of the peak inductor current and the output capacitor ESR. Use low-ESR ceramic capacitors for best performance. Low-ESR, surface-mount tantalum capacitors with higher capacity may be used for load transients with high peak currents. Voltage ratings and temperature characteristics should be considered. Input Capacitor The input capacitor (CIN) in boost designs reduces the current peaks drawn from the input supply and reduces noise injection. The value of CIN is largely determined by the source impedance of the input supply. High source impedance requires high input capacitance, particularly as the input voltage falls. Since step-up DCDC converters act as “constant-power” loads to their input supply, input current rises as input voltage falls. A good starting point is to use the same capacitance value for CIN as for COUT. Table 1 lists suggested component suppliers. Integrator Capacitor The MAX1748 contains an internal current integrator that improves the DC load regulation but increases the peak-to-peak transient voltage (see the load-transient waveforms in the Typical Operating Characteristics). For highly accurate DC load regulation, enable the current integrator by connecting a 470pF capacitor to INTG. To minimize the peak-to-peak transient voltage at the expense of DC regulation, disable the integrator by connecting INTG to REF and adding a 100kΩ resistor to GND. 12 Rectifier Diode Use a Schottky diode with an average current rating equal to or greater than the peak inductor current, and a voltage rating at least 1.5 times the main output voltage (VMAIN). Charge Pump Efficiency Considerations The efficiency characteristics of the MAX1748 regulated charge pumps are similar to a linear regulator. They are dominated by quiescent current at low output currents and by the input voltage at higher output currents (see Typical Operating Characteristics). So the maximum efficiency may be approximated by: Efficiency ≅ VNEG / [VIN ✕ N]; for the negative charge pump Efficiency ≅ VPOS / [VIN ✕ (N + 1)]; for the positive charge pump where N is the number of charge-pump stages. Output Voltage Selection Adjust the positive output voltage by connecting a voltage-divider from the output (VPOS) to FBP to GND (see Typical Operating Circuit). Adjust the negative output Table 1. Component Suppliers SUPPLIER INDUCTORS PHONE FAX Coilcraft 847-639-6400 847-639-1469 Coiltronics 561-241-7876 561-241-9339 Sumida USA 847-956-0666 847-956-0702 Toko 847-297-0070 847-699-1194 CAPACITORS AVX 803-946-0690 803-626-3123 Kemet 408-986-0424 408-986-1442 Sanyo 619-661-6835 619-661-1055 Taiyo Yuden 408-573-4150 408-573-4159 Central Semiconductor 516-435-1110 516-435-1824 International Rectifier 310-322-3331 310-322-3332 Motorola 602-303-5454 602-994-6430 DIODES Nihon 847-843-7500 847-843-2798 Zetex 516-543-7100 516-864-7630 ______________________________________________________________________________________ Triple-Output TFT LCD DC-DC Converter R3 = R4 [(VPOS / VREF) - 1] R5 = R6 (VNEG / VREF) where VREF = 1.25V. VPOS may range from VSUPP to 40V, and VNEG may range from 0 to -40V. Flying Capacitor Increasing the flying capacitor’s value reduces the output current capability. Above a certain point, increasing the capacitance has a negligible effect because the output current capability becomes dominated by the internal switch resistance and the diode impedance. Start with 0.1µF ceramic capacitors. Smaller values may be used for low-current applications. Charge-Pump Output Capacitor Increasing the output capacitance or decreasing the ESR reduces the output ripple voltage and the peak-topeak transient voltage. Use the following equation to approximate the required capacitor value: COUT ≥ [IOUT / (500kHz ✕ VRIPPLE)] Charge-Pump Input Capacitor Use a bypass capacitor with a value equal to or greater than the flying capacitor. Place the capacitor as close to the IC as possible. Connect directly to PGND. Rectifier Diode Use Schottky diodes with a current rating equal to or greater than 4 times the average output current, and a voltage rating at least 1.5 times VSUPP for the positive charge pump and VSUPN for the negative charge pump. PC Board Layout and Grounding Careful printed circuit layout is extremely important to minimize ground bounce and noise. First, place the main boost converter output diode and output capacitor less than 0.2in (5mm) from the LX and PGND pins with wide traces and no vias. Then place 0.1µF ceramic bypass capacitors near the charge-pump input pins (SUPP and SUPN) to the PGND pin. Keep the chargepump circuitry as close to the IC as possible, using wide traces and avoiding vias when possible. Locate all feedback resistive dividers as close to their respective feedback pins as possible. The PC board should feature separate GND and PGND areas connected at only one point under the IC. To maximize output power and efficiency and to minimize output power ripple voltage, use extra wide power ground traces and solder the IC’s power ground pin directly to it. Avoid having sensitive traces near the switching nodes and high-current lines. Refer to the MAX1748 evaluation kit for an example of proper board layout. Applications Information Boost Converter Using a Cascoded MOSFET For applications that require output voltages greater than 13V, cascode an external N-channel MOSFET (Figure 4). Place the MOSFET as close to the LX pin as possible. Connect the gate to the input voltage (VIN) and the source to LX. MOSFET Selection Choose a MOSFET with an on-resistance (R DS(ON)) lower than the internal N-channel MOSFET. Lower RDS(ON) will improve efficiency. The external N-channel MOSFET must have a drain-voltage rating higher than the main output voltage (VMAIN). Chip Information TRANSISTOR COUNT: 2846 ______________________________________________________________________________________ 13 MAX1748 voltage by connecting a voltage-divider from the output (VNEG) to FBN to REF. Select R4 and R6 in the 50kΩ to 100kΩ range. Higher resistor values improve efficiency at low output current but increase output voltage error due to the feedback input bias current. Calculate the remaining resistors with the following equations: 14 3.3µF 1.0µF VNEG = -8V, 20mA 0.47µF VIN = 5.0V CREF 0.22µF R5 319k 100k R6 49.9k 0.1µF 0.22µF PGND REF FBN DRVN RDY SHDN IN SUPN MAX1748 6.8µH GND TGND INTG FBP DRVP FB LX SUPP CINTG 470pF 0.1µF 0.22µF R4 49.9k R2 10k R1 130k R3 1M RCOMP 5k 0.47µF 1.0µF VPOS = +25V, 5mA CCOMP 68nF COUT 10µF VMAIN = +18V, 140mA MAX1748 Triple-Output TFT LCD DC-DC Converter Figure 4. Power Supply Using Cascoded MOSFET ______________________________________________________________________________________ VNEG = -5V, 20mA 1.0µF 3.3µF CINTG 470pF 100k R5 200k CREF 0.22µF R6 49.9k 0.1µF 0.1µF GND TGND INTG REF FBN DRVN RDY SHDN IN MAX1748 6.8µH PGND FBP DRVP SUPP SUPN FB LX 0.1µF RCOMP 5k R4 49.9k 0.1µF 0.1µF R2 10k R1 70k R3 670k CCOMP 6.8nF COUT 10µF 1.0µF VPOS = +15V, 10mA VMAIN = +10V, 200mA Typical Operating Circuit ______________________________________________________________________________________ 15 MAX1748 VIN = 3.0V Triple-Output TFT LCD DC-DC Converter Triple-Output TFT LCD DC-DC Converter MAX1748 TSSOP.EPS Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.