ETC AM29LV017M

Am29LV017M
Data Sheet
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PRODUCTION PENDING
Production subject to customer demand. Contact your
local AMD sales representative for more information
Am29LV017M
16 Megabit (2 M x 8-Bit) MirrorBitTM
3.0 Volt-only Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 2.7 to 3.6 volt read and write operations for
battery-powered applications
■ Manufactured on 0.23 µm MirrorBit process
technology
— Compatible with and replaces Am29LV017B
device
■ SecSiTM (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or
by the customer
■ High performance
— Access times as fast as 70 ns
■ Ultra low power consumption (typical values at 5
MHz)
— 400 nA Automatic Sleep mode current
— 400 nA standby mode current
— 15 mA read current
— 40 mA program/erase current
■ Flexible sector architecture
— Thirty-two 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Minimum 100,000 erase cycle guarantee
per sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
— 48-ball FBGA
— 40-pin TSOP
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
■ Command sequence optimized for mass storage
— Specific address not required for unlock cycles
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 26009 Rev: C Amendment/0
Issue Date: April 7, 2003
P E N D I N G
GENERAL DESCRIPTION
The Am29LV017M is a 16 Mbit, 3.0 Volt-only Flash
memory organized as 2,097,152 bytes. The device is
offered in 48-ball FBGA and 40-pin TSOP packages.
The byte-wide (x8) data appears on DQ7–DQ0. All
read, program, and erase operations are accomplished
using only a single power supply. The device can also
be programmed in standard EPROM programmers.
The standard device offers access times of 70, 90, and
120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
2
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. The Program Suspend/Program Resume
feature enables the host system to pause a program
operation in a given sector to read any other sector and
then complete the program operation.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron
injection.
Am29LV017M
April 7, 2003
P E N D I N G
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV017M Device Bus Operations................................ 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 10
Table 2. Am29LV017M Sector Address Table................................ 11
Autoselect Mode ..................................................................... 12
Table 3. Am29LV017M Autoselect Codes (High Voltage Method) . 12
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Figure 1. Temporary Sector Unprotect Operation........................... 13
SecSi (Secured Silicon) Sector Flash Memory Region .......... 15
Table 1. SecSi Sector Contents ......................................................15
Figure 3. SecSi Sector Protect Verify.............................................. 16
Hardware Data Protection ...................................................... 16
Low VCC Write Inhibit .............................................................. 16
Write Pulse “Glitch” Protection ............................................... 16
Logical Inhibit .......................................................................... 16
Power-Up Write Inhibit ............................................................ 16
Common Flash Memory Interface (CFI) . . . . . . . 17
Table 4. CFI Query Identification String.......................................... 17
Table 5. System Interface String..................................................... 17
Table 6. Device Geometry Definition .............................................. 18
Table 7. Primary Vendor-Specific Extended Query ........................ 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20
Reading Array Data ................................................................ 20
Reset Command ..................................................................... 20
Autoselect Command Sequence ............................................ 20
Byte Program Command Sequence ....................................... 20
Unlock Bypass Command Sequence ..................................... 21
Figure 4. Program Operation .......................................................... 21
Program Suspend/Program Resume Command Sequence ... 22
Figure 5. Program Suspend/Program Resume............................... 22
Chip Erase Command Sequence ........................................... 23
Sector Erase Command Sequence ........................................ 23
Erase Suspend/Erase Resume Commands ........................... 23
Figure 6. Erase Operation............................................................... 24
Table 8. Am29LV017M Command Definitions .............................. 25
Write Operation Status . . . . . . . . . . . . . . . . . . . . 26
DQ7: Data# Polling ................................................................. 26
Figure 7. Data# Polling Algorithm .................................................. 26
RY/BY#: Ready/Busy# ............................................................ 27
DQ6: Toggle Bit I .................................................................... 27
DQ2: Toggle Bit II ................................................................... 27
Reading Toggle Bits DQ6/DQ2 ............................................... 27
Figure 8. Toggle Bit Algorithm........................................................ 28
DQ5: Exceeded Timing Limits ................................................ 29
DQ3: Sector Erase Timer ....................................................... 29
Table 9. Write Operation Status..................................................... 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 30
Figure 9. Maximum Negative Overshoot Waveform ...................... 30
Figure 10. Maximum Positive Overshoot Waveform...................... 30
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Test Setup..................................................................... 32
Table 10. Test Specifications ......................................................... 32
Figure 12. Input Waveforms and Measurement Levels ................. 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Read Operations .................................................................... 33
Figure 13. Read Operations Timings ............................................. 33
Hardware Reset (RESET#) .................................................... 34
Figure 14. RESET# Timings .......................................................... 34
Erase/Program Operations ..................................................... 35
Figure 15. Program Operation Timings..........................................
Figure 16. Chip/Sector Erase Operation Timings ..........................
Figure 17. Data# Polling Timings (During Embedded Algorithms).
Figure 18. Toggle Bit Timings (During Embedded Algorithms)......
Figure 19. DQ2 vs. DQ6.................................................................
Figure 20. Temporary Sector Unprotect Timing Diagram ..............
Figure 21. Sector Protect/Unprotect Timing Diagram ....................
Figure 22. Alternate CE# Controlled Write Operation Timings ......
36
36
37
38
38
39
40
42
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 43
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 43
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 44
TS 040—40-Pin Standard TSOP ............................................ 44
TSR040—40-Pin Reverse TSOP ........................................... 45
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 6 mm package .................................................................. 46
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision A (June 24, 2002) .................................................... 47
Revision A + 1 (July 3, 2002) .................................................. 47
Revision B (December 9, 2002) .............................................. 47
Command Definitions ............................................................. 25
April 7, 2003
Am29LV017M
3
P E N D I N G
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV017M
VCC = 2.7–3.6 V
70
90
120
VCC = 3.0–3.6 V
70R
90R
120R
Max access time, ns (tACC)
70
90
120
Max CE# access time, ns (tCE)
70
90
120
Max OE# access time, ns (tOE)
30
35
50
Speed Option
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A20
4
Am29LV017M
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
April 7, 2003
P E N D I N G
CONNECTION DIAGRAMS
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
April 7, 2003
40-Pin Standard TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
40-Pin Reverse TSOP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
NC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
Am29LV017M
5
P E N D I N G
CONNECTION DIAGRAM
48-Ball FBGA (Top View, Balls Facing Down)
A6
B6
C6
D6
E6
F6
G6
H6
A14
A13
A15
A16
A17
NC
A20
VSS
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A11
A12
A19
A10
DQ6
DQ7
A4
B4
C4
D4
E4
F4
G4
H4
DQ4
WE#
RESET#
NC
NC
DQ5
NC
VCC
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
NC
NC
DQ2
DQ3
VCC
NC
A2
B2
C2
D2
E2
F2
G2
H2
A7
A18
A6
A5
DQ0
NC
NC
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Special Handling Instructions for FBGA
Packages
Special handling is required for Flash Memory products
in molded packages (FBGA and TSOP). The package
6
and/or data integrity may be compromised if the
package body is exposed to temperatures above 150C
for prolonged periods of time.
Am29LV017M
April 7, 2003
P E N D I N G
PIN CONFIGURATION
A0–A20=21 addresses
LOGIC SYMBOL
21
DQ0–DQ7=8 data inputs/outputs
A0–A20
CE# = Chip enable
8
DQ0–DQ7
OE# = Output enable
WE# = Write enable
CE#
RESET#=Hardware reset pin, active low
OE#
RY/BY#=Ready/Busy output
WE#
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
RESET#
VSS
= Device ground
NC
= Pin not connected internally
April 7, 2003
RY/BY#
Am29LV017M
7
P E N D I N G
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29LV017M
70
E
I
TEMPERATURE RANGE
I
=
Industrial (–40°C to +85°C)
PACKAGE TYPE
E
=
F
=
WA
=
40-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 040)
40-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR040)
48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8 x 6 mm package (FBA048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29LV017M
16 Megabit (2 M x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program and Erase
Production Pending
Valid Combinations
Production subject to customer demand. Contact your
local AMD sales representative to request ordering
information.
8
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29LV017M
April 7, 2003
P E N D I N G
DEVICE BUS OPERATIONS
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the
Table 1.
Operation
Am29LV017M Device Bus Operations
CE#
OE#
WE#
RESET#
Addresses
DQ0–DQ7
Read
L
L
H
H
AIN
DOUT
Write
L
H
L
H
AIN
DIN
X
High-Z
VCC ±
0.3 V
X
X
VCC ±
0.3 V
Output Disable
L
H
H
H
X
High-Z
Reset
X
X
X
L
X
High-Z
Sector Protect (See Note)
L
H
L
VID
Sector Addresses,
A6 = L, A1 = H, A0 = L
DIN, DOUT
Sector Unprotect (See Note)
L
H
L
VID
Sector Addresses
A6 = H, A1 = H, A0 = L
DIN, DOUT
Temporary Sector Unprotect
X
X
X
VID
AIN
DIN
Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Note: The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at VIH.
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in
the DC Characteristics table represents the active current specification for reading array data.
April 7, 2003
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Word/Byte Program Command Sequence” section has details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
Am29LV017M
9
P E N D I N G
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteristics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
“RESET#: Hardware Reset Pin”.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
tACC + 30 ns. The automatic sleep mode is
10
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
the system. I CC4 in the DC Characteristics table
represents the automatic sleep m ode cu rrent
specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29LV017M
April 7, 2003
P E N D I N G
Table 2.
Am29LV017M Sector Address Table
Sector
A20
A19
A18
A17
A16
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
000000–00FFFF
SA1
0
0
0
0
1
010000–01FFFF
SA2
0
0
0
1
0
020000–02FFFF
SA3
0
0
0
1
1
030000–03FFFF
SA4
0
0
1
0
0
040000–04FFFF
SA5
0
0
1
0
1
050000–05FFFF
SA6
0
0
1
1
0
060000–06FFFF
SA7
0
0
1
1
1
070000–07FFFF
SA8
0
1
0
0
0
080000–08FFFF
SA9
0
1
0
0
1
090000–09FFFF
SA10
0
1
0
1
0
0A0000–0AFFFF
SA11
0
1
0
1
1
0B0000–0BFFFF
SA12
0
1
1
0
0
0C0000–0CFFFF
SA13
0
1
1
0
1
0D0000–0DFFFF
SA14
0
1
1
1
0
0E0000–0EFFFF
SA15
0
1
1
1
1
0F0000–0FFFFF
SA16
1
0
0
0
0
100000–10FFFF
SA17
1
0
0
0
1
110000–11FFFF
SA18
1
0
0
1
0
120000–12FFFF
SA19
1
0
0
1
1
130000–13FFFF
SA20
1
0
1
0
0
140000–14FFFF
SA21
1
0
1
0
1
150000–15FFFF
SA22
1
0
1
1
0
160000–16FFFF
SA23
1
0
1
1
1
170000–17FFFF
SA24
1
1
0
0
0
180000–18FFFF
SA25
1
1
0
0
1
190000–19FFFF
SA26
1
1
0
1
0
1A0000–1AFFFF
SA27
1
1
0
1
1
1B0000–1BFFFF
SA28
1
1
1
0
0
1C0000–1CFFFF
SA29
1
1
1
0
1
1D0000–1DFFFF
SA30
1
1
1
1
0
1E0000–1EFFFF
SA31
1
1
1
1
1
1F0000–1FFFFF
April 7, 2003
Am29LV017M
11
P E N D I N G
Autoselect Mode
Table 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 3 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7-DQ0.
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 8. This method
does not require VID. See “” for details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 3.
Am29LV017M Autoselect Codes (High Voltage Method)
CE#
OE#
WE#
A20
to
A16
Manufacturer ID: AMD
L
L
H
X
X
VID
X
L
X
L
L
01h
Device ID: Am29LV017M
L
L
H
X
X
VID
X
L
X
L
H
C8h
Description
A15
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
01h
(protected)
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
12
Am29LV017M
April 7, 2003
P E N D I N G
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors.
protected again. Figure 1 shows the algorithm, and
Figure 20 shows the timing diagrams, for this feature.
START
Sector protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the
algorithms and Figure 21 shows the timing diagram.
This method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors
must first be protected prior to the first sector unprotect
write cycle.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Temporary Sector
Unprotect Completed
(Note 2)
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Notes:
Temporary Sector Unprotect
1. All protected sectors unprotected.
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are
April 7, 2003
2. All previously protected sectors are protected once
again.
Figure 1.
Am29LV017M
Temporary Sector Unprotect Operation
13
P E N D I N G
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 µs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Reset
PLSCNT = 1
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
Yes
No
Yes
PLSCNT
= 1000?
Protect another
sector?
Device failed
No
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Single
High Voltage
Sector Protect
Algorithm
Sector Protect
complete
Set up
next sector
address
Data = 00h?
Yes
Last sector
verified?
No
Yes
Single High Voltage
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Figure 2.
14
In-System Single High Voltage Sector Protect/Unprotect Algorithms
Am29LV017M
April 7, 2003
P E N D I N G
SecSi (Secured Silicon) Sector Flash
Memory Region
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 128 words/256 bytes in
length, and uses a SecSi Sector Indicator Bit (DQ7) to
indicate whether or not the SecSi Sector is locked
when shipped from the factory. This bit is permanently
set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the
security of the ESN once the product is shipped to the
field.
In devices with an ESN, the SecSi Sector is protected
when the device is shipped from the factory. The SecSi
Sector cannot be modified in any way. A factory locked
device has an 8-word/16-byte random ESN at addresses 000000h–000007h.
AMD offers the device with the SecSi Sector either
factory locked or customer lockable. The factorylocked version is always protected when shipped from
the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi
Sector unprotected, allowing customers to program
the sector after receiving the device. The customerlockable version also has the SecSi Sector Indicator
Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from
being used to replace devices that are factory locked.
The SecSi sector address space in this device is allocated as follows:
Table 1.
SecSi Sector
Address Range
x16
x8
000000h–
000007h
000000h–
00000Fh
000008h–
00007Fh
000010h–
0000FFh
SecSi Sector Contents
Standard
Factory
Locked
ExpressFlash
Factory Locked
ESN
ESN or
determined by
customer
Unavailable
Determined by
customer
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
As an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 128-word/256 bytes SecSi
sector.
The system may program the SecSi Sector using the
write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions.
Programming and protecting the SecSi Sector must be
used with caution since, once protected, there is no
procedure available for unprotecting the SecSi Sector
area and none of the bits in the SecSi Sector memory
space can be modified in any way.
Customer
Lockable
The SecSi Sector area can be protected using one of
the following procedures:
Determined by
customer
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 1,
except that RESET# may be at either VIH or VID.
This allows in-system protection of the SecSi Sector
without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0).
This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or
until power is removed from the device. On power-up,
or following a hardware reset, the device reverts to
sending commands to sector SA0. Note that the ACC
function and unlock bypass modes are not available
when the SecSi Sector is enabled.
April 7, 2003
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. The devices are then shipped from AMD’s factory with the
SecSi Sector permanently locked. Contact an AMD
representative for details on using AMD’s ExpressFlash service.
■ To verify the protect/unprotect status of the SecSi
Sector, follow the algorithm shown in Figure 2.
Once the SecSi Sector is programmed, locked and
verified, the system must write the Exit SecSi Sector
Region command sequence to return to reading and
writing within the remainder of the array.
Am29LV017M
15
P E N D I N G
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
START
RESET# =
VIH or VID
Wait 1 µs
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Remove VIH or VID
from RESET#
Write reset
command
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
SecSi Sector
Protect Verify
complete
Logical Inhibit
Write cycles are inhibited by holding any one of OE#
= VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE#
is a logical one.
Power-Up Write Inhibit
Figure 3.
SecSi Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 8 for com-
16
If WE# = CE# = V IL and OE# = V IH during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
a u to m at ic al l y re se t to re a di n g a rra y d ata o n
power-up.
Am29LV017M
April 7, 2003
P E N D I N G
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families.
Flash vendors can standardize their existing interfaces
for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array
Table 4.
data. The system can read CFI information at the
addresses given in Tables 4–7. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 4–7. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100, available online at
http://www.amd.com/flash/cfi. Alternatively, contact an
AMD representative for copies of these documents.
CFI Query Identification String
Addresses
Data
Description
10h
11h
12h
51h
52h
59h
Query Unique ASCII string “QRY”
13h
14h
02h
00h
Primary OEM Command Set
15h
16h
40h
00h
Address for Primary Extended Table
17h
18h
00h
00h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
00h
00h
Address for Alternate OEM Extended Table (00h = none exists)
Table 5.
System Interface String
Addresses
Data
1Bh
27h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
36h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
00h
VPP Min. voltage (00h = no VPP pin present)
1Eh
00h
VPP Max. voltage (00h = no VPP pin present)
1Fh
07h
Typical timeout per single byte/word write 2N µs
20h
00h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
0Ah
Typical timeout per individual block erase 2N ms
22h
00h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
01h
Max. timeout for byte/word write 2N times typical
24h
00h
Max. timeout for buffer write 2N times typical
25h
04h
Max. timeout per individual block erase 2N times typical
26h
00h
Max. timeout for full chip erase 2N times typical (00h = not supported)
April 7, 2003
Description
Am29LV017M
17
P E N D I N G
Table 6.
Addresses
18
Device Geometry Definition
Data
Description
N
27h
15h
Device Size = 2 byte
28h
29h
00h
00h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
00h
00h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
01h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
1Fh
00h
00h
01h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
00h
00h
00h
00h
Erase Block Region 2 Information
35h
36h
37h
38h
00h
00h
80h
00h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
00h
00h
00h
00h
Erase Block Region 4 Information
Am29LV017M
April 7, 2003
P E N D I N G
Table 7.
Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
50h
52h
49h
Query-unique ASCII string “PRI”
43h
31h
Major version number, ASCII
44h
33h
Minor version number, ASCII
Address Sensitive Unlock (Bit 1-0)
0 = Required, 1 = Not Required
45h
08h
Process Technology (Bit 7-2)
10b = 0.23 µm MirrorBit
46h
02h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
01h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
01h
Sector Temporary Unprotect: 00 = Not Supported, 01 = Supported
49h
04h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
00h
Simultaneous Operation: 00 = Not Supported, 01 = Supported
4Bh
00h
Burst Mode Type: 00 = Not Supported, 01 = Supported
4Ch
00h
Page Mode Type: 00 = Not Supported, 01 = 4 Word Page,
02 = 8 Word Page
April 7, 2003
Am29LV017M
19
P E N D I N G
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 8 defines the valid register command
sequences. Writing incorrect address and data values
or writing them in the improper sequence may place
the device in an unknown state. A reset command is
then required to return the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information
on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
20
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 8 shows the address and data requirements.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address XX02h returns XX01h if that sector is protected, or 00h if it is unprotected. Refer to
Table 2 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The device programs one byte of data for each program operation. The command sequence requires four
bus cycles, and is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or timings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table
8 shows the address and data requirements for the
byte program command sequence. Note that the autoselect and CFI functions are unavailable when a program operation is in progress.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See “Write Operation Status”
for information on these status bits.
Am29LV017M
April 7, 2003
P E N D I N G
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
don’t cares for both cycles. The device then returns to
reading array data.
Figure 4 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 15 for
timing diagrams
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
START
Write Program
Command Sequence
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes to the device faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command sequence, resulting in faster total programming
time. Table 8 shows the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note: See Table 8 for program command sequence.
Figure 4.
April 7, 2003
Data Poll
from System
Am29LV017M
Program Operation
21
P E N D I N G
Program Suspend/Program Resume
Command Sequence
The Program Suspend command allows the system to
interrupt a programming operation or a Write to Buffer
programming operation so that data can be read from
any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the program operation within 15
µs maximum (5µs typical) and updates the status bits.
Addresses are not required when writing the Program
Suspend command.
The system must write the Program Resume command (address bits are don’t care) to exit the Program
Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be
written after the device has resume programming.
Program Operation
or Write-to-Buffer
Sequence in Progress
After the programming operation has been suspended, the system can read array data from any nonsuspended sector. The Program Suspend command
may also be issued during a programming operation
while an erase is suspended. In this case, data may
be read from any addresses not in Erase Suspend or
Program Suspend. If a read is needed from the SecSi
Sector area (One-time Program area), then user must
use the proper command sequences to enter and exit
this region.
The system may also write the autoselect command
sequence when the device is in the Program Suspend
mode. The system can read as many autoselect
codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See
Autoselect Command Sequence for more information.
After the Program Resume command is written, the
device reverts to programming. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more
information.
22
Write address/data
XXXh/B0B0h
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Wait 15 µs
Read data as
required
No
Autoselect and SecSi Sector
read operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Done
reading?
Yes
Write address/data
XXXh/3030h
Write Program Resume
Command Sequence
Device reverts to
operation prior to
Program Suspend
Figure 5. Program Suspend/Program Resume
Am29LV017M
April 7, 2003
P E N D I N G
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 8 shows
the address and data requirements for the chip erase
command sequence. Note that the autoselect, and CFI
functions are unavailable when a erase operation is in
progress.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched.
Figure 6 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase
command. Table 8 shows the address and data requirements for the sector erase command sequence.
Note that the autoselect and CFI functions are unavailable when a erase operation is in progress.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time beApril 7, 2003
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the operation. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to “Write Operation Status” for information on these status bits.)
Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the time-out period 50 µs
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
Am29LV017M
23
P E N D I N G
minates the time-out period and suspends the erase
operation.
Erase Suspend command can be written after the device has resumed erasing.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
START
Write Erase
Command Sequence
Data Poll
from System
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
24
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 8 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Am29LV017M
Figure 6.
Erase Operation
April 7, 2003
P E N D I N G
Command Definitions
Command Sequence
1)
Read 5)
Reset 6)
Autoselect
7)
Cycles
Table 8.
Am29LV017M Command Definitions
Bus Cycles (Notes 2–4)
First
Second
Addr
Data
1
RA
RD
Third
Fourth
Addr
Data
Addr
Data
Addr
Data
1
XXX
F0
Manufacturer ID
4
XXX
AA
XXX
55
XXX
90
X00
01
Device ID
4
XXX
AA
XXX
55
XXX
90
X01
C8
90
SA
X02
00
01
PA
PD
Sector Protect
Verify 8)
CFI Query 9)
4
1
XXX
XXX
55
AA
XXX
55
XXX
XXX
XXX
Fifth
Sixth
Addr
Data
Addr
Data
98
Byte Program
4
XXX
AA
XXX
55
XXX
A0
Unlock Bypass
3
XXX
AA
XXX
55
XXX
20
Unlock Bypass Program
9)
2
XXX
A0
PA
PD
Unlock Bypass Reset
11)
2
XXX
90
XXX
00
Chip Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
XXX
10
Sector Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
SA
30
Program/Erase Suspend
12)
1
XXX
B0
Program/Erase Resume
13)
1
XXX
30
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or CE#
pulse.
Notes:
1. See Table 1 for descriptions of bus operations.
SA = Address of the sector to be erased or verified. Address
bits A20–A16 uniquely select any sector.
2. All values are in hexadecimal.
8. The data is 00h for an unprotected sector and 01h for a
protected sector.
3. Except when reading array or autoselect data, all bus
cycles are write operations.
9. Command is valid when device is ready to read array data
or when device is in autoselect mode.
4. Address bits are don’t care for unlock and command
cycles, except when PA or SA is required.
10. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.
5. No unlock or command cycles required when device is in
read mode.
11. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the Unlock
Bypass mode.
6. The Reset command is required to return to the read
mode when the device is in the autoselect mode or if DQ5
goes high.
7. The fourth cycle of the autoselect command sequence is
a read cycle.
April 7, 2003
12. The system may read and program functions in nonerasing sectors, or enter the autoselect mode, when in
the Erase Suspend mode. The Erase Suspend command
is valid only during a sector erase operation.
13. The Erase Resume command is valid only during the
Erase Suspend mode.
Am29LV017M
25
P E N D I N G
WRITE OPERATION STATUS
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 9 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
Table 9 shows the outputs for Data# Polling on DQ7.
Figure 7 shows the Data# Polling algorithm.
START
DQ7: Data# Polling
Read DQ7–DQ0
Addr = VA
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
DQ7 = Data?
No
No
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 17, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
26
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected.
Yes
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29LV017M
Figure 7.
Data# Polling Algorithm
April 7, 2003
P E N D I N G
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. (The RY/BY# pin is not available on the 44-pin SO package.)
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 9 shows the outputs for RY/BY#. Figures 14, 15
and 16 shows RY/BY# for reset, program, and erase
operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or CE#
to control the read cycles). When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
April 7, 2003
Table 9 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm in flowchart form,
and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. Figure 18 in the “AC Characteristics” section shows the toggle bit timing diagrams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 9 to compare outputs
for DQ2 and DQ6.
Figure 8 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 18 shows the toggle bit timing diagram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 8 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
Am29LV017M
27
P E N D I N G
must write the reset command to return to reading
array data.
START
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 8).
Read DQ7–DQ0
1)
Read DQ7–DQ0
Table 9 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 18 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 19 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
Toggle Bit
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 8.
28
Am29LV017M
Toggle Bit Algorithm
April 7, 2003
P E N D I N G
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
Table 9.
Operation
Embedded Program
Standard Algorithm
Mode
Embedded Erase Algorithm
Program
Suspend
Mode
ProgramSuspend Read
Reading within Erase
Suspended Sector
Erase
Suspend Reading within Non-Erase
Mode
Suspended Sector
Erase-Suspend-Program
tional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches
from “0” to “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the “Sector Erase Command Sequence” section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been accepted. Table 9 shows the outputs for DQ3.
Write Operation Status
DQ7
2)
DQ6
DQ5
1)
DQ3
DQ2
2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
Program-Suspended
Sector
Invalid (not allowed)
Non-Program
Suspended Sector
Data
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
April 7, 2003
Am29LV017M
29
P E N D I N G
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –55°C to +150°C
20 ns
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
20 ns
–2.0 V
A9, OE#, and
RESET# (Note 2) . . . . . . . . . . . .–0.5 V to +12.5 V
20 ns
All other pins (Note 1) . . . . . . –0.5 V to VCC+0.5 V
Figure 9. Maximum Negative
Overshoot Waveform
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 9.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may
overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 10.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 9. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 10. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC (full voltage range) . . . . . . . . . . . .+2.7 V to 3.6 V
VCC (regulated voltage range) . . . . . . .+3.0 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
30
Am29LV017M
April 7, 2003
P E N D I N G
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
±1.0
µA
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
35
µA
ILR
Reset Leakage Current
VCC = VCC max; RESET# = 12.5 V
35
µA
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
±1.0
µA
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
ICC2
VCC Active Write Current
(Notes 2, 3, 5)
ICC3
5 MHz
15
30
1 MHz
2
10
CE# = VIL, OE# = VIH
40
60
mA
VCC Standby Current (Note 2)
CE#, RESET# = VCC±0.3 V
0.4
5
µA
ICC4
VCC Reset Current (Note 2)
RESET# = VSS ± 0.3 V
0.8
5
µA
ICC5
Automatic Sleep Mode
(Notes 2, 4)
VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V
0.4
5
µA
VIL1
Input Low Voltage 1(6, 7)
–0.5
0.8
V
VIH1
Input High Voltage 1 (6, 7)
1.9
VCC + 0.5
V
VIL2
Input Low Voltage 2 (6, 8)
–0.5
0.3 x VIO
V
VIH2
Input High Voltage 2 (6, 8)
1.9
VIO + 0.5
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.3 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
0.45
V
VOH1
Output High Voltage
VOH2
VLKO
mA
IOH = –2.0 mA, VCC = VCC min = VIO
0.85 VIO
V
IOH = –100 µA, VCC = VCC min = VIO
VIO–0.4
V
Low VCC Lock-Out Voltage (5)
2.3
2.5
V
Notes:
1.
On the WP#/ACC pin only, the maximum input load current when
WP# = VIL is ± 5.0 µA.
5.
Automatic sleep mode enables the low power mode when
addresses remain stable for tACC + 30 ns.
2.
The ICC current listed is typically less than 2 mA/MHz, with OE# at
VIH.
6.
If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO.
Maximum VIH for these connections is VIO + 0.3 V
3.
Maximum ICC specifications are tested with VCC = VCCmax.
ICC active while Embedded Erase or Embedded Program is in
progress.
7.
VCC voltage requirements.
4.
April 7, 2003
8.
VIO voltage requirements.
9.
Not 100% tested.
Am29LV017M
31
P E N D I N G
TEST CONDITIONS
Table 10.
Test Specifications
3.3 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
90,
90R
Output Load
6.2 kΩ
Test Setup
120,
120R
Unit
1 TTL gate
Output Load
Capacitance, CL
(including jig
capacitance)
Note: Diodes are IN3064 or equivalent
Figure 11.
70,
70R
30
100
pF
Input Rise and Fall
Times
5
ns
Input Pulse Levels
0.0–3.0
V
Input timing
measurement
reference levels
1.5
V
Output timing
measurement
reference levels
1.5
V
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.5 V
Measurement Level
1.5 V
Output
0.0 V
Figure 12.
32
Input Waveforms and Measurement Levels
Am29LV017M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
70,
70R
90,
90R
120,
120R
Unit
Min
70
90
120
ns
CE# = VIL
OE# = VIL
Max
70
90
120
ns
OE# = VIL
Max
70
90
120
ns
Output Enable to Output Delay
Max
30
35
50
ns
tDF
Chip Enable to Output High Z 1)
Max
16
ns
tDF
Output Enable to Output High Z 1)
Max
16
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Min
0
ns
JEDEC
Std
Description
tAVAV
tRC
Read Cycle Time 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Test Setup
tOEH
Output Enable
Hold Time 1)
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First 1)
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 10 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 13.
April 7, 2003
Read Operations Timings
Am29LV017M
33
P E N D I N G
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14.
34
RESET# Timings
Am29LV017M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
70,
70R
90,
90R
120,
120R
Unit
70
90
120
ns
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time 1)
Min
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
50
ns
tDVWH
tDS
Data Setup Time
Min
35
45
50
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time 1)
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
Programming Operation 2)
Typ
TBD
µs
tWHWH2
tWHWH2
Sector Erase Operation 2)
Typ
0.4
sec
tVCS
VCC Setup Time 1)
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Min
90
ns
tBUSY
35
35
50
ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
April 7, 2003
Am29LV017M
35
P E N D I N G
AC CHARACTERISTICS
Read Status Data (last two cycles)
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
XXXh
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
tBUSY
tRB
RY/BY#
tVCS
VCC
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 15.
Program Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
XXXh
Addresses
Read Status Data
VA
SA
VA
XXXh for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 16.
36
Chip/Sector Erase Operation Timings
Am29LV017M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 17.
April 7, 2003
Data# Polling Timings (During Embedded Algorithms)
Am29LV017M
37
P E N D I N G
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Figure shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
Figure 18.
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Toggle Bit Timings (During Embedded Algorithms)
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an erase-suspended
sector.
Figure 19.
38
DQ2 vs. DQ6
Am29LV017M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
tVIDR
VID Rise and Fall Time (See Note)
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
All Speed Options
Unit
Min
500
ns
Min
4
µs
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 20.
April 7, 2003
Temporary Sector Unprotect Timing Diagram
Am29LV017M
39
P E N D I N G
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
Valid*
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 21.
40
Sector Protect/Unprotect Timing Diagram
Am29LV017M
April 7, 2003
P E N D I N G
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
70,
70R
90,
90R
120,
120R
Unit
70
90
120
ns
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time 1)
Min
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
50
ns
tDVEH
tDS
Data Setup Time
Min
35
45
50
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
Programming Operation 2)
Typ
TBD
µs
tWHWH2
tWHWH2
Sector Erase Operation 2)
Typ
0.4
sec
0
35
35
ns
50
ns
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
April 7, 2003
Am29LV017M
41
P E N D I N G
AC CHARACTERISTICS
XXX for program
XXX for erase
PA for program
SA for sector erase
XXX for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = Program Address, PD = Program Data, DOUT = Data Out, DQ7# = complement of data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 22.
42
Alternate CE# Controlled Write Operation Timings
Am29LV017M
April 7, 2003
P E N D I N G
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ 1)
Max 2)
Unit
Sector Erase Time
0.4
15
s
Chip Erase Time
22.5
Byte Programming Time
TBD
TBD
µs
Chip Programming Time 4)
TBD
TBD
s
s
Comments
Excludes 00h programming
prior to erasure 4)
Excludes system level
overhead 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See
Table 8 for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
April 7, 2003
Am29LV017M
43
P E N D I N G
PHYSICAL DIMENSIONS*
TS 040—40-Pin Standard TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
44
Am29LV017M
April 7, 2003
P E N D I N G
PHYSICAL DIMENSIONS
TSR040—40-Pin Reverse TSOP
Dwg rev AA; 10/99
* For reference only. BSC is an ANSI standard for Basic Space Centering.
April 7, 2003
Am29LV017M
45
P E N D I N G
PHYSICAL DIMENSIONS
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 6 mm package
Dwg rev AF; 10/99
46
Am29LV017M
April 7, 2003
P E N D I N G
REVISION SUMMARY
Revision A (June 24, 2002)
Absolute Maximum Rating
Initial release.
Changed the Ambient Temperature with Power Applied
from –55°C to +125°C to –65°C to +125°C.
Revision A + 1 (July 3, 2002)
Corrected FBGA package markings in Ordering Information.
Figure 6. Program Suspend/Program Resume
Added text and flowchart.
Corrected numbers in DC Characteristics table.
Table 8. Primary Vendor-Specific Extend Query
Removed Zero Power Flash figures for DC Characteristics, replaced with TBD.
Added proccess technology reference to the 45h address and corrected data variable.
Corrected erase and programming performance times.
Table 10. Write Operation Status
Corrected minimum erase and program cycle endurance specification.
Added program suspend mode.
Operating Ranges
Revision B (February 6, 2003)
Corrected typos in VIO ranges.
Global
DC Characteristics table
Added regulated speed options and updated effected
tables in datasheet.
Destinctive Characteristics
Changed VIH1 and VIH2 minimum to 1.9.
Removed typos in notes.
Hardware Reset, Erase and Program Operations,
Temporary Sector Unprotect, and Alternate CE#
Controlled Erase and Program Operations
Added SecSi text.
General Description
Added Note. Changed tWHWH1 to TBD.
Added page suspend text.
CMOS Compatible
Product Selector Guide
Added another Vcc range and regulated speed
options.
Ordering Information
Added regulated speed options.
Removed V IL , V IH , V OL , and V OH from table and
added V IL1 , V IH1 , V IL2 , V IH2 , V OL , V OH1 , and V OH2
from the CM OS tabl e in the Am 29LV640M H/L
datasheet.
Customer Lockable: SecSi Sector NOT
Programmed or Protected at the factory.
Removed Commercial temperature range.
Changed WC package type to WA package type.
Byte/Word Program Command Sequence, Sector
Erase Command Sequence, and Chip Erase Command Sequence
Noted that the SecSi Sector, autoselect, and CFI
functions are unavailable when a program or erase
operation is in progress.
Added second bullet, SecSi sector-protect verify text
and figure 3.
Physical Dimensions
Changed the FBC048 package to the FBA048
package.
Revision C (April 7, 2003)
Global
Common Flash Memory Interface (CFI)
Coverted to “Production Pending” status.
Changed CFI website address.
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, MirrorBitTM, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
April 7, 2003
Am29LV017M
47
Representatives in U.S. and Canada
Sales Offices and Representatives
North America
ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 5 6 ) 8 3 0 - 9 1 9 2
ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 0 2 ) 24 2 - 4 4 0 0
CALIFORNIA,
Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 4 9 ) 4 5 0 - 7 5 0 0
Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 0 8 ) 7 3 2 - 24 0 0
COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 0 3 ) 74 1 - 2 9 0 0
CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 0 3 ) 2 6 4 - 7 8 0 0
FLORIDA,
Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 2 7 ) 7 9 3 - 0 0 5 5
Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 0 5 ) 8 2 0 - 1 1 1 3
GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 7 0 ) 8 1 4 - 0 2 2 4
ILLINOIS,
Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 3 0 ) 7 7 3 - 4 4 2 2
MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 8 1 ) 2 1 3 - 6 4 0 0
MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 4 8 ) 4 7 1 - 6 2 9 4
MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 1 2 ) 74 5 - 0 0 0 5
NEW JERSEY,
Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 3 ) 7 0 1 - 1 7 7 7
NEW YORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 4 2 5 - 8 0 5 0
NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 9 ) 8 4 0 - 8 0 8 0
OREGON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 0 3 ) 24 5 - 0 0 8 0
PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 1 5 ) 3 4 0 - 1 1 8 7
SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 6 0 5 ) 69 2 - 5 7 7 7
TEXAS,
Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 1 2 ) 3 4 6 - 7 8 3 0
Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 2 ) 9 8 5 - 1 3 4 4
Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 8 1 ) 3 76 - 8 0 8 4
VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 0 3 ) 7 3 6 - 9 5 6 8
International
AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . . T E L ( 6 1 ) 2 - 8 8 - 7 7 7 - 2 2 2
BELGIUM, Antwerpen . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 2 ) 3 - 2 4 8 - 4 3 - 0 0
BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 5 5 ) 1 1 - 5 5 0 1 - 2 1 0 5
CHINA,
Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 6 ) 1 0 - 6 5 1 0 - 2 1 8 8
Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 6 ) 2 1 - 6 3 5 - 0 0 8 3 8
Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 6 ) 75 5 - 24 6 - 1 5 5 0
FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 5 8 ) 8 8 1 - 3 1 1 7
FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 3 ) - 1 - 4 9 7 5 1 0 1 0
GERMANY,
Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 6 1 7 2 - 9 2 6 7 0
Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 8 9 - 4 5 0 5 3 0
HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . . T E L ( 8 5 ) 2 - 2 9 5 6 - 0 3 8 8
ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 9 ) - 0 2 - 3 8 1 9 6 1
INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 9 1 ) 1 1 - 6 2 3 - 8 6 2 0
JAPAN,
Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 1 ) 6 - 6 2 4 3 - 3 2 5 0
Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 1 ) 3 - 3 3 4 6 - 7 6 0 0
KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 2 ) 2 - 3 4 6 8 - 2 6 0 0
RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(7)-095-795-06-22
SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(46)8-562-540-00
TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 8 8 6 ) 2 - 8 7 7 3 - 1 5 5 5
UNITED KINGDOM,
Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 4 ) 1 2 76 - 8 0 3 1 0 0
Haydcock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 4 ) 1 9 4 2 - 2 7 2 8 8 8
Advanced Micro Devices reserves the right to make changes in its product without notice
in order to improve design or performance characteristics.The performance
characteristics listed in this document are guaranteed by specific tests, guard banding,
design and other practices common to the industry. For specific testing details, contact
your local AMD sales representative.The company assumes no responsibility for the use of
any circuits described herein.
© Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD Arrow logo and combination thereof, are trademarks of
Advanced Micro Devices, Inc. Other product names are for informational purposes only
and may be trademarks of their respective companies.
es
ARIZONA,
Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 8 0 ) 8 3 9 - 2 3 2 0
CALIFORNIA,
Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 1 8 ) 8 7 8 - 5 8 0 0
Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 4 9 ) 2 6 1 - 2 1 2 3
San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 5 8 ) 2 7 8 - 4 9 5 0
Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 0 8 ) 3 5 0 - 4 8 0 0
CANADA,
Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . . ( 6 0 4 ) 4 3 0 - 3 6 8 0
Calgary, Alberta - Davetek Marketing. . . . . . . . . . . . . . . . . ( 4 0 3 ) 2 8 3 - 3 5 7 7
Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . . ( 6 1 3 ) 5 9 2 - 9 5 4 0
Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . ( 9 0 5 ) 6 7 2 - 2 0 3 0
St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . ( 5 1 4 ) 7 4 7 - 1 2 1 1
COLORADO,
Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . . ( 3 0 3 ) 2 7 7 - 0 4 5 6
FLORIDA,
Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . . ( 3 2 1 ) 7 2 8 - 7 7 0 6
Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . . ( 9 5 4 ) 5 2 7 - 4 9 4 9
Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . . ( 4 0 7 ) 8 7 2 - 5 7 7 5
St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . . ( 7 2 7 ) 8 9 4 - 3 6 0 3
GEORGIA,
Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . ( 6 7 8 ) 5 8 4 - 1 1 2 8
ILLINOIS,
Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . . ( 8 4 7 ) 9 6 7 - 8 4 3 0
INDIANA,
Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 6 5 ) 4 5 7 - 7 2 4 1
IOWA,
Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . ( 3 1 9 ) 2 9 4 - 1 0 0 0
KANSAS,
Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 3 ) 4 6 9 - 1 3 1 2
MASSACHUSETTS,
Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . . ( 7 8 1 ) 2 3 8 - 0 8 7 0
MICHIGAN,
Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 1 0 ) 2 2 7 - 0 0 0 7
MINNESOTA,
St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . . ( 6 5 1 ) 69 9 - 0 2 0 0
MISSOURI,
St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 1 4 ) 9 9 7 - 4 5 5 8
NEW JERSEY,
Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . . ( 8 5 6 ) 8 6 6 - 1 2 3 4
NEW YORK,
Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 7 4 1 - 7 1 1 6
East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . ( 3 1 5 ) 4 3 7 - 8 3 4 3
Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 5 8 6 - 3 6 6 0
Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . ( 5 1 6 ) 5 3 6 - 4 2 4 2
NORTH CAROLINA,
Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . . ( 9 1 9 ) 8 4 6 - 5 7 2 8
OHIO,
Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . . ( 4 4 0 ) 8 1 6 - 1 6 6 0
Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . ( 6 1 4 ) 7 8 1 - 0 7 2 5
Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . ( 9 3 7 ) 8 9 8 - 9 6 1 0
Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . ( 6 1 4 ) 5 2 3 - 1 9 9 0
OREGON,
Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . ( 5 0 3 ) 6 7 0 - 0 5 5 7
UTAH,
Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . . ( 8 0 1 ) 2 8 8 - 2 5 0 0
VIRGINIA,
Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . ( 4 1 0 ) 7 6 1 - 2 2 5 5
WASHINGTON,
Kirkland - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . ( 4 2 5 ) 8 2 2 - 9 2 2 0
WISCONSIN,
Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . . ( 2 6 2 ) 5 74 - 9 3 9 3
Representatives in Latin America
ARGENTINA,
Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655
CHILE,
Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993
COLUMBIA,
Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 7 1 ) 4 1 0 - 4 1 8 2
MEXICO,
Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 2 3 ) 8 1 7 - 3 9 0 0
Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 5 2 5 ) 7 5 2 - 2 7 2 7
Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . . ( 5 2 8 ) 3 69 - 6 8 2 8
PUERTO RICO,
Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 8 7 ) 8 5 1 - 6 0 0 0
One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400
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©2003 Advanced Micro Devices, Inc.
01/03
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