Am29LV160D Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Publication Number 22358 Revision B Amendment +3 Issue Date November 10, 2000 Am29LV160D 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors ■ Manufactured on 0.23 µm process technology — Fully compatible with 0.32 µm Am29LV160B device ■ High performance — Access times as fast as 70 ns ■ Ultra low power consumption (typical values at 5 MHz) ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1,000,000 write cycle guarantee per sector ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ Package option — 48-ball FBGA — 200 nA Automatic Sleep mode current — 48-pin TSOP — 200 nA standby mode current — 44-pin SO — 9 mA read current — 20 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode) ■ CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Compatibility with JEDEC standards — One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode) — Pinout and software compatible with singlepower supply Flash — Supports full chip erase — Superior inadvertent write protection — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Top or bottom boot block configurations available ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion (not available on 44-pin SO) ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22358 Rev: B Amendment/+3 Issue Date: November 10, 2000 GENERAL DESCRIPTION The Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V CC supply. A 12.0 V V PP or 5.0 V CC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The Am29LV160D is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. 2 The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. Am29LV160D TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. Am29LV160D Device Bus Operations ................................9 DQ2: Toggle Bit II ................................................................... 26 Reading Toggle Bits DQ6/DQ2 ............................................... 26 Figure 6. Toggle Bit Algorithm........................................................ 27 DQ3: Sector Erase Timer ....................................................... 28 Table 10. Write Operation Status ................................................... 28 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29 Figure 7. Maximum Negative Overshoot Waveform ...................... 29 Figure 8. Maximum Positive Overshoot Waveform........................ 29 Word/Byte Configuration .......................................................... 9 Requirements for Reading Array Data ..................................... 9 Writing Commands/Command Sequences ............................ 10 Program and Erase Operation Status .................................... 10 Standby Mode ........................................................................ 10 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 11 Output Disable Mode .............................................................. 11 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 2. Sector Address Tables (Am29LV160DT) ..........................12 Table 3. Sector Address Tables (Am29LV160DB) ..........................13 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Operations .................................................................... 33 Autoselect Mode ..................................................................... 14 Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14 Sector Protection/Unprotection ............................................... 14 Temporary Sector Unprotect .................................................. 15 Figure 1. Temporary Sector Unprotect Operation........................... 15 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 16 Common Flash Memory Interface (CFI) . . . . . . . 17 Table 5. CFI Query Identification String ..........................................17 Table 6. System Interface String .....................................................18 Table 7. Device Geometry Definition ..............................................18 Hardware Data Protection ...................................................... 19 Table 8. Primary Vendor-Specific Extended Query ........................19 Low VCC Write Inhibit .............................................................. 19 Write Pulse “Glitch” Protection ............................................... 19 Logical Inhibit .......................................................................... 19 Power-Up Write Inhibit ............................................................ 19 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20 Reading Array Data ................................................................ 20 Reset Command ..................................................................... 20 Autoselect Command Sequence ............................................ 20 Word/Byte Program Command Sequence ............................. 20 Unlock Bypass Command Sequence ..................................... 21 Figure 3. Program Operation .......................................................... 21 Chip Erase Command Sequence ........................................... 21 Sector Erase Command Sequence ........................................ 22 Erase Suspend/Erase Resume Commands ........................... 22 Figure 4. Erase Operation............................................................... 23 Command Definitions ............................................................. 24 Table 9. Am29LV160D Command Definitions ................................24 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 25 DQ7: Data# Polling ................................................................. 25 Figure 5. Data# Polling Algorithm ................................................... 25 RY/BY#: Ready/Busy# ........................................................... 26 DQ6: Toggle Bit I .................................................................... 26 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 31 Figure 10. Typical ICC1 vs. Frequency ........................................... 31 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 11. Test Setup..................................................................... 32 Table 11. Test Specifications ......................................................... 32 Figure 12. Input Waveforms and Measurement Levels ................. 32 Figure 13. Read Operations Timings ............................................. 33 Hardware Reset (RESET#) .................................................... 34 Figure 14. RESET# Timings .......................................................... 34 Word/Byte Configuration (BYTE#) ........................................ 35 Figure 15. BYTE# Timings for Read Operations............................ 35 Figure 16. BYTE# Timings for Write Operations............................ 35 Erase/Program Operations ..................................................... 36 Figure 17. Program Operation Timings.......................................... Figure 18. Chip/Sector Erase Operation Timings .......................... Figure 19. Data# Polling Timings (During Embedded Algorithms). Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations ............................................................ Figure 22. Temporary Sector Unprotect/Timing Diagram .............. Figure 23. Sector Protect/Unprotect Timing Diagram .................... Figure 24. Alternate CE# Controlled Write Operation Timings ...... 37 38 39 39 40 40 41 43 Erase and Programming Performance . . . . . . . 44 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 44 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 44 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 45 TS 048—48-Pin Standard TSOP ............................................ 45 TSR048—48-Pin Reverse TSOP ........................................... 46 FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm ................................................................................ 47 SO 044—44-Pin Small Outline Package ................................ 48 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision A (January 1999) ..................................................... 49 Revision A+1 (April 19, 1999) ................................................. 49 Revision B (November 23, 1999) ............................................ 49 Revision B+1 (February 22, 2000) .......................................... 49 Revision B+2 (November 7, 2000) ......................................... 49 Revision B+3 (November 10, 2000) ....................................... 49 Am29LV160D 3 PRODUCT SELECTOR GUIDE Family Part Number Am29LV160D Voltage Range: VCC = 2.7–3.6 V -70 -90 -120 Max access time, ns (tACC) 70 90 120 Max CE# access time, ns (tCE) 70 90 120 Max OE# access time, ns (tOE) 30 35 50 Speed Option Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM DQ0–DQ15 (A-1) RY/BY# VCC Sector Switches VSS Erase Voltage Generator RESET# WE# BYTE# Input/Output Buffers State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Address Latch STB Timer A0–A19 4 Am29LV160D STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix CONNECTION DIAGRAMS A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard TSOP Reverse TSOP Am29LV160D 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE# RESET# NC NC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 5 CONNECTION DIAGRAMS RESET# A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 SO WE# A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC FBGA Top View, Balls Facing Down A6 B6 C6 D6 E6 A13 A12 A14 A15 A16 A5 B5 C5 D5 E5 F5 G5 H5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE# RESET# NC A19 DQ5 DQ12 VCC DQ4 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY# NC A18 NC DQ2 DQ10 DQ11 DQ3 A2 B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE# OE# VSS Special Handling Instructions Special handling is required for Flash Memory products in FBGA packages. 6 F6 G6 BYTE# DQ15/A-1 H6 VSS Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. Am29LV160D PIN CONFIGURATION A0–A19 LOGIC SYMBOL = 20 addresses 20 DQ0–DQ14 = 15 data inputs/outputs A0–A19 DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode 16 or 8 DQ0–DQ15 (A-1) CE# = Chip enable CE# OE# = Output enable OE# WE# = Write enable RESET# = Hardware reset pin RY/BY# = Ready/Busy output (N/A SO 044) WE# RESET# BYTE# VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device ground NC = Pin not connected internally Am29LV160D RY/BY# (N/A SO 044) 7 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29LV160D T -70 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) WC = 48-ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 9 mm package (FBC048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29LV160D 16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations For TSOP and SO Packages Am29LV160DT-70, Am29LV160DB-70 Valid Combinations for FBGA Packages Order Number Am29LV160DT-70, Am29LV160DB-70 EC, EI, EE, FC, FI, FE, SC, SI, SE Am29LV160DT-90, Am29LV160DB-90 Am29LV160DT-90, Am29LV160DB-90 Am29LV160DT-120, Am29LV160DB-120 Am29LV160DT-120, Am29LV160DB-120 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 8 Package Marking Am29LV160D L160DT70V, L160DB70V WCC, WCI, WCE L160DT90V, L160DB90V L160DT12V, L160DB12V C, I, E DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of Table 1. the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Am29LV160D Device Bus Operations DQ8–DQ15 Operation CE# OE# WE# RESET# Addresses (Note 1) DQ0– DQ7 BYTE# = VIH BYTE# = VIL Read L L H H AIN DOUT DOUT Write L H L H AIN DIN DIN DQ8–DQ14 = High-Z, DQ15 = A-1 VCC ± 0.3 V X X VCC ± 0.3 V X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-Z Sector Protect (Note 2) L H L VID Sector Address, A6 = L, A1 = H, A0 = L DIN X X Sector Unprotect (Note 2) L H L VID Sector Address, A6 = H, A1 = H, A0 = L DIN X X Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Protection/Unprotection” section. Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re- main at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Am29LV160D 9 Writing Commands/Command Sequences Program and Erase Operation Status To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using b o t h s t a n d a r d a n d U n l o ck B y p a s s c o m m a n d sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. 10 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. Am29LV160D RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to deter mine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29LV160D 11 Table 2. Sector Address Tables (Am29LV160DT) Sector A19 A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) SA0 0 0 0 0 0 X X X 64/32 000000–00FFFF 00000–07FFF SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF SA33 1 1 1 1 1 1 0 1 8/4 1FA000–1FBFFF FD000–FDFFF SA34 1 1 1 1 1 1 1 X 16/8 1FC000–1FFFFF FE000–FFFFF Byte Mode (x8) Word Mode (x16) Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section. 12 Am29LV160D Table 3. Sector Address Tables (Am29LV160DB) Sector A19 A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) Address Range (in hexadecimal) SA0 0 0 0 0 0 0 0 X 16/8 000000–003FFF 00000–01FFF SA1 0 0 0 0 0 0 1 0 8/4 004000–005FFF 02000–02FFF SA2 0 0 0 0 0 0 1 1 8/4 006000–007FFF 03000–03FFF SA3 0 0 0 0 0 1 X X 32/16 008000–00FFFF 04000–07FFF SA4 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA5 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA6 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA7 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA8 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA9 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA10 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA11 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA12 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA14 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA15 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA17 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA18 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA19 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA20 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA21 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA22 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA23 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA24 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA25 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA26 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA27 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA28 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA30 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA31 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA33 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA34 1 1 1 1 1 X X X 64/32 1F0000–1FFFFF F8000–FFFFF Byte Mode (x8) Word Mode (x16) Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section. Am29LV160D 13 Autoselect Mode Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 9. This method does not require VID. See “Command Definitions” for details on using the autoselect mode. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. Description Mode Manufacturer ID: AMD Am29LV160D Autoselect Codes (High Voltage Method) CE# OE# WE# L L H L L H Device ID: Am29LV160D (Top Boot Block) Word Byte L L H Device ID: Am29LV160D (Bottom Boot Block) Word L L H A19 A11 to to A12 A10 Sector Protection Verification L L L L A1 A0 DQ8 to DQ15 DQ7 to DQ0 X 01h 22h C4h X C4h 22h 49h X 49h X 01h (protected) X 00h (unprotected) X VID X L X L L X X VID X L X L H VID X X H H A6 A5 to A2 X X Byte A9 A8 to A7 SA X VID X L L X X L H H L L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. Sector protection/unprotection can be implemented via two methods. 14 The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Details on this method are provided in a supplement, publication number 21468. Contact an AMD representative to request a copy. Am29LV160D Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure shows the algorithm, and Figure 22 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 1. Am29LV160D Temporary Sector Unprotect Operation 15 START START Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address PLSCNT = 1 RESET# = VID Wait 1 µs Temporary Sector Unprotect Mode No PLSCNT = 1 RESET# = VID Wait 1 µs No First Write Cycle = 60h? First Write Cycle = 60h? Yes Yes Set up sector address No All sectors protected? Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Wait 150 µs Increment PLSCNT Temporary Sector Unprotect Mode Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Reset PLSCNT = 1 Wait 15 ms Read from sector address with A6 = 0, A1 = 1, A0 = 0 Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 Increment PLSCNT No No PLSCNT = 25? Yes Yes No Yes Device failed Read from sector address with A6 = 1, A1 = 1, A0 = 0 Data = 01h? PLSCNT = 1000? Protect another sector? No Data = 00h? Yes Yes Remove VID from RESET# Device failed Last sector verified? Write reset command Sector Protect Algorithm Sector Protect complete Yes Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. 16 In-System Sector Protect/Unprotect Algorithms Am29LV160D Set up next sector address No No COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. Table 5. The system can read CFI information at the addresses given in Tables 5–8. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents. CFI Query Identification String Addresses (Word Mode) Addresses (Byte Mode) Data 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h Query Unique ASCII string “QRY” 13h 14h 26h 28h 0002h 0000h Primary OEM Command Set 15h 16h 2Ah 2Ch 0040h 0000h Address for Primary Extended Table 17h 18h 2Eh 30h 0000h 0000h Alternate OEM Command Set (00h = none exists) 19h 1Ah 32h 34h 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) Description Am29LV160D 17 Table 6. System Interface String Addresses (Word Mode) Addresses (Byte Mode) Data 1Bh 36h 0027h VCC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h VCC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported) Table 7. Addresses (Word Mode) 18 Addresses (Byte Mode) Description Device Geometry Definition Data Description N 27h 4Eh 0015h Device Size = 2 byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 58h 0004h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0000h 0000h 0040h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h Erase Block Region 2 Information 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0080h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 001Eh 0000h 0000h 0001h Erase Block Region 4 Information Am29LV160D Table 8. Primary Vendor-Specific Extended Query Addresses (Word Mode) Addresses (Byte Mode) Data 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h 88h 0030h Minor version number, ASCII 45h 8Ah 0000h Address Sensitive Unlock 0 = Required, 1 = Not Required 46h 8Ch 0002h Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001h Sector Protect 0 = Not Supported, X = Number of sectors in per group 48h 90h 0001h Sector Temporary Unprotect 00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000h Simultaneous Operation 00 = Not Supported, 01 = Supported 4Bh 96h 0000h Burst Mode Type 00 = Not Supported, 01 = Supported 4Ch 98h 0000h Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page Description Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 9 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. Am29LV160D 19 COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. 20 The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 9 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a Am29LV160D hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. START Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1,” or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Write Program Command Sequence Embedded Program algorithm in progress Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams. Data Poll from System Verify Data? No Yes Increment Address No Last Address? Yes Programming Completed Note: See Table 9 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 9 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Am29LV160D 21 “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to “Write Operation Status” for information on these status bits.) Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to Figure 18 for timing diagrams. Sector Erase Command Sequence Erase Suspend/Erase Resume Commands Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend command. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are 22 When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another Am29LV160D valid operation. See “Autoselect Command Sequence” for more information. START The system must write the Erase Resume command (address bits are “don’t care”) to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Write Erase Command Sequence Data Poll from System No Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed Notes: 1. See Table 9 for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information. Figure 4. Am29LV160D Erase Operation 23 Command Definitions Cycles Table 9. Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID, Top Boot Block Device ID, Bottom Boot Block Sector Protect Verify (Note 9) 1 1 Word Byte Word Byte Word Byte 4 4 4 Word First Addr Data RA RD XXX F0 555 AA AAA 555 AA AAA 555 AA AAA 555 4 Byte Word Byte Word Program Byte Word Unlock Bypass Byte Unlock Bypass Program (Note 11) Unlock Bypass Reset (Note 12) Word Chip Erase Byte Word Sector Erase Byte Erase Suspend (Note 13) Erase Resume (Note 14) CFI Query (Note 10) Am29LV160D Command Definitions 4 3 2 2 6 6 1 1 Bus Cycles (Notes 2–5) Third Fourth Addr Data Addr Data 2AA 555 2AA 555 2AA 555 555 AAA 555 AAA 555 AAA 55 AA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX 55 55 55 2AA AA AAA 1 Second Addr Data 90 90 90 555 55 555 90 AAA X00 01 X01 (SA) X04 22C4 C4 2249 49 XX00 XX01 00 01 PA PD X02 X01 X02 (SA) X02 Fifth Addr Data Sixth Addr Data 2AA 555 2AA 555 55 555 AAA 10 55 SA 30 98 AA AA A0 90 AA AA 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 55 555 AAA 555 AAA A0 20 PD 00 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA B0 30 Legend: PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. 10. Command is valid when device is ready to read array data or when device is in autoselect mode. 4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required. 12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 24 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 14. The Erase Resume command is valid only during the Erase Suspend mode. Am29LV160D WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 10 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 10 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. START DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading array data. Read DQ7–DQ0 Addr = VA DQ7 = Data? No No DQ5 = 1? Yes During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. Read DQ7–DQ0 Addr = VA After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. FAIL When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7– DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms), in the “AC Characteristics” section illustrates this. Yes DQ7 = Data? Yes No PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Am29LV160D Figure 5. Data# Polling Algorithm 25 RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. (The RY/BY# pin is not available on the 44-pin SO package.) If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 10 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. 26 Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and Am29LV160D the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). START Read DQ7–DQ0 Read DQ7–DQ0 (Note 1) Toggle Bit = Toggle? No Yes No DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit = Toggle? (Notes 1, 2) No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. Figure 6. Am29LV160D Toggle Bit Algorithm 27 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional Table 10. Erase Suspend Mode After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10 shows the outputs for DQ3. Write Operation Status DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) DQ7# Toggle 0 N/A No toggle 0 Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase Suspended Sector 1 No toggle 0 N/A Toggle 1 Reading within Non-Erase Suspended Sector Data Data Data Data Data 1 Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0 Operation Standard Mode sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 µs. See also the “Sector Erase Command Sequence” section. Embedded Program Algorithm RY/BY# Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 28 Am29LV160D ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied. . . . . . . . . . . . . . –65°C to +125°C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . –0.5 V to +12.5 V 20 ns 20 ns +0.8 V –0.5 V –2.0 V All other pins (Note 1). . . . . . . –0.5 V to VCC+0.5 V 20 ns Output Short Circuit Current (Note 3) . . . . . . 200 mA Figure 7. Maximum Negative Overshoot Waveform Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns Figure 8. Maximum Positive Overshoot Waveform OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . –55°C to +125°C VCC Supply Voltages VCC for all devices . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. Am29LV160D 29 DC CHARACTERISTICS CMOS Compatible Parameter Description Test Conditions Min ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ICC1 VCC Active Read Current (Notes 1, 2) Typ Max Unit ±1.0 µA 35 µA ±1.0 µA CE# = VIL, OE# = VIH, Byte Mode 5 MHz 9 16 1 MHz 2 4 CE# = VIL, OE# = VIH, Word Mode 5 MHz 9 16 1 MHz 2 4 mA ICC2 VCC Active Write Current (Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 30 mA ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±0.3 V 0.2 5 µA ICC4 VCC Standby Current During Reset RESET# = VSS ± 0.3 V (Notes 2, 4) 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4, 6) 0.2 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage VOH2 VLKO VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V IOH = -2.0 mA, VCC = VCC min 0.85 x VCC IOH = -100 µA, VCC = VCC min VCC–0.4 Low VCC Lock-Out Voltage (Note 4) 2.3 V 2.5 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested. 30 Am29LV160D DC CHARACTERISTICS (Continued) Zero Power Flash Supply Current in mA 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 Time in ns Note: Addresses are switching at 1 MHz Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 10 3.6 V Supply Current in mA 8 2.7 V 6 4 2 0 1 2 3 4 5 Frequency in MHz Note: T = 25 °C Figure 10. Typical ICC1 vs. Frequency Am29LV160D 31 TEST CONDITIONS Table 11. Test Specifications 3.3 V Test Condition Output Load 2.7 kΩ Device Under Test -70 30 Input Rise and Fall Times 6.2 kΩ Figure 11. 100 ns 0.0–3.0 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V Test Setup Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H 3.0 V Input Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 1.5 V Measurement Level 0.0 V Figure 12. 32 pF 5 Input Pulse Levels Note: Diodes are IN3064 or equivalent Unit 1 TTL gate Output Load Capacitance, CL (including jig capacitance) CL -90, -120 Input Waveforms and Measurement Levels Am29LV160D 1.5 V Output AC CHARACTERISTICS Read Operations Parameter Speed Options JEDEC Std Description tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable to Output Delay tGLQV tOE tEHQZ tGHQZ tAXQX Test Setup -70 -90 -120 Unit Min 70 90 120 ns CE# = VIL OE# = VIL Max 70 90 120 ns OE# = VIL Max 70 90 120 ns Output Enable to Output Delay Max 30 35 50 ns tDF Chip Enable to Output High Z (Note 1) Max 25 30 30 ns tDF Output Enable to Output High Z (Note 1) Max 25 30 30 ns Read Min 0 ns Toggle and Data# Polling Min 10 ns Min 0 ns tOEH Output Enable Hold Time (Note 1) tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Notes: 1. Not 100% tested. 2. See Figure 11 and Table 11 for test specifications. tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs RESET# RY/BY# 0V Figure 13. Read Operations Timings Am29LV160D 33 AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description Test Setup All Speed Options Unit tREADY RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) Max 20 µs tREADY RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH RESET# High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 14. 34 RESET# Timings Am29LV160D AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Speed Options Std Description -70 -90 -120 Unit tELFL/tELFH CE# to BYTE# Switching Low or High Max tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 30 30 ns tFHQV BYTE# Switching High to Output Active Min 70 90 120 ns 5 ns CE# OE# BYTE# BYTE# Switching from word to byte mode tELFL Data Output (DQ0–DQ7) Data Output (DQ0–DQ14) DQ0–DQ14 Address Input DQ15 Output DQ15/A-1 tFLQZ tELFH BYTE# BYTE# Switching from byte to word mode Data Output (DQ0–DQ7) DQ0–DQ14 Address Input DQ15/A-1 Data Output (DQ0–DQ14) DQ15 Output tFHQV Figure 15. BYTE# Timings for Read Operations CE# The falling edge of the last WE# signal WE# BYTE# tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations Am29LV160D 35 AC CHARACTERISTICS Erase/Program Operations Parameter Speed Options JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min tWLAX tAH Address Hold Time Min 45 45 50 ns tDVWH tDS Data Setup Time Min 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns -90 -120 Unit 70 90 120 ns Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns 0 ns tGHWL tGHWL tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min 30 Byte Typ 5 tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns Program/Erase Valid to RY/BY# Delay Min 90 ns tBUSY 35 35 50 ns ns µs Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 36 -70 Am29LV160D AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses 555h Read Status Data (last two cycles) PA PA PA tAH CE# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# tVCS VCC Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 17. Program Operation Timings Am29LV160D 37 AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h In Progress 30h Complete 10 for Chip Erase tBUSY tRB RY/BY# tVCS VCC Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). 2. Illustration shows device in word mode. Figure 18. 38 Chip/Sector Erase Operation Timings Am29LV160D AC CHARACTERISTICS tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data Valid Data True High Z Valid Data True tBUSY RY/BY# Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 19. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ6/DQ2 tBUSY Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) RY/BY# Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 20. Toggle Bit Timings (During Embedded Algorithms) Am29LV160D 39 AC CHARACTERISTICS Enter Embedded Erasing Erase Suspend Erase Suspend Program Erase Suspend Read Erase WE# Enter Erase Suspend Program Erase Resume Erase Erase Suspend Read Erase Complete DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations Temporary Sector Unprotect Parameter JEDEC Std Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect All Speed Options Unit Min 500 ns Min 4 µs Note: Not 100% tested. 12 V RESET# 0 or 3 V tVIDR tVIDR Program or Erase Command Sequence CE# WE# tRSP RY/BY# Figure 22. 40 Temporary Sector Unprotect/Timing Diagram Am29LV160D AC CHARACTERISTICS VID VIH RESET# SA, A6, A1, A0 Valid* Valid* Sector Protect/Unprotect Data 60h Valid* Verify 60h 40h Status Sector Protect: 150 µs Sector Unprotect: 15 ms 1 µs CE# WE# OE# Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 23. Sector Protect/Unprotect Timing Diagram Am29LV160D 41 AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter Speed Options JEDEC Std Description tAVAV tWC Write Cycle Time (Note 1) Min tAVEL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 45 45 50 ns tDVEH tDS Data Setup Time Min 35 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min tEHEL tCPH CE# Pulse Width High Min 30 Byte Typ 5 tWHWH1 tWHWH1 Programming Operation (Note 2) Word Typ 7 -90 -120 Unit 70 90 120 ns tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 0 35 35 ns 50 ns ns µs Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 42 -70 Am29LV160D sec AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tCP CE# tWS tWHWH1 or 2 tCPH tBUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example. Figure 24. Alternate CE# Controlled Write Operation Timings Am29LV160D 43 ERASE AND PROGRAMMING PERFORMANCE Parameter Typ (Note 1) Max (Note 2) Unit Sector Erase Time 0.7 15 s Chip Erase Time 25 Byte Programming Time 5 150 µs Word Programming Time 7 210 µs s Chip Programming Time Byte Mode 11 33 s (Note 3) Word Mode 7.2 21.6 s Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA VCC Current Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time 44 Am29LV160D PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP Dwg rev AA; 10/99 * For reference only. BSC is an ANSI standard for Basic Space Centering. Am29LV160D 45 PHYSICAL DIMENSIONS TSR048—48-Pin Reverse TSOP Dwg rev AA; 10/99 * For reference only. BSC is an ANSI standard for Basic Space Centering. 46 Am29LV160D PHYSICAL DIMENSIONS FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm Dwg rev AF; 10/99 Am29LV160D 47 PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package Dwg rev AC; 10/99 48 Am29LV160D REVISION SUMMARY Revision A (January 1999) Physical Dimensions The Am29LV160D is fully form, fit, and function compatible with the Am29LV160B device, with the following differences: Replaced figures with more detailed illustrations. Revision B+1 (February 22, 2000) A 70 ns device at full voltage range is now available. The 80 ns speed option has been deleted. Global Byte and word programming times, and byte- and word-mode chip programming times are now reduced. Ordering Information At extended temperatures (>+85°C), sleep and standby currents increase. Added dash to speed options. Added dash to OPN. Revision B+2 (November 7, 2000) Global Revision A+1 (April 19, 1999) Global Deleted Preliminary status from data sheet. Deleted burn-in option. Added table of contents. Reclassified the document from advance information to preliminary. Revision B+3 (November 10, 2000) The 70 ns speed option is now also available with the industrial and extended temperature range ratings. Revision B (November 23, 1999) Command Definitions Reset Command: Deleted reference to Figure 14, RESET# Timings, which applies only to hardware reset. AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Trademarks Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am29LV160D 49