AUSTIN AS5LC1008

SRAM
AS5LC1008
Austin Semiconductor, Inc.
128K x 8 SRAM
PIN ASSIGNMENT
High-Speed CMOS SRAM with
3.3V Revolutionary Pinout
(Top View)
32-Pin, 400-mil
Plastic SOJ (DJ) & Ceramic SOJ (DCJ)
FEATURES
• High-speed access times of 10, 12, 15 and 20 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater noise
immunity
• Easy memory expansion with CE\ and OE\ options
• CE\ power-down
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Single 3.3V power supply
OPTIONS
MARKING
• Timing
10ns access
12ns access
15ns access
20ns access
-10
-12
-15
-20
• Package
Plastic SOJ (32-pin, 400-mil)
*Ceramic SOJ (32-pin, 400-mil)
DJ
DCJ
• Operating Temperature Ranges
-Military (-55oC to +125oC)
-Industrial (-40oC to +85oC)
A0
A1
A2
A3
CE\
I/O 0
I/O 1
Vcc
GND
I/O 2
I/O 3
WE\
A4
A5
A6
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE\
I/O 7
I/O 6
GND
Vcc
I/O 5
I/O 4
A12
A11
A10
A9
A8
No. 906
No. 501
PIN FUNCTIONS
PIN
A0 - A16
CE\
OE\
WE\
I/O0 - I/O7
XT
IT
*Consult Factory, Possible Future Offering
GENERAL DESCRIPTION
The ASI AS5LC1008 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The AS5LC1008 is fabricated using high-performance
CMOS technology. This highly reliable process coupled with
innovative circuit design techniques, yields higher performance
and low power consumption devices.
When CE\ is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down to 250µW (typical) with CMOS input levels.
The AS5LC1008 operates from a single 3.3V power supply
and all inputs are TTL-compatible.
AS5LC1008
Rev. 1.0 11/02
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
GND
DESCRIPTION
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
AS5LC1008
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
A0 - A16
128K x 8
MEMORY ARRAY
DECODER
VCC
GND
I/O DATA
CIRCUIT
I/O0 - I/O7
CE\
OE\
WE\
COLUMN I/O
CONTROL
CIRCUIT
ABSOLUTE MAXIMUM RATINGS*
Terminal Voltage with Respect to GND (VTERM)...........................................................................................-0.5V to VCC + 0.5V
Temperature Under Bias (TBIAS).............................................................................................................................-55°C to +125°C
Storage Temperature (TSTG)....................................................................................................................................-65°C to +150°C
Power Dissipation (PT)................................................................................................................................................................1.0W
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
I/O Operation VCC Current
WE\
CE\
OE\
X
H
X
High-Z
ISB1, ISB2
H
L
H
High-Z
ICC1, ICC2
Read
H
L
L
DOUT
ICC1, ICC2
Write
L
L
X
DIN
ICC1, ICC2
AS5LC1008
Rev. 1.0 11/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
AS5LC1008
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
PARAMETER
Output HIGH Voltage
SYMBOL
CONDITIONS
MIN
MAX
UNITS
VOH
VCC = Min., IOH = -4.0mA
2.4
---
V
Output LOW Voltage
VOL
VCC = Min., IOL = 8.0mA
---
0.4
V
Input HIGH Voltage
VIH
2.2
VCC + 0.3
V
VIL
-0.3
0.8
V
Input LOW Voltage
1
Input Leakage
ILI
GND < VIN < VCC
-5
5
µA
Output Leakage
ILO
GND < VOUT < VCC;
Outputs Disabled
-5
5
µA
NOTE: 1. VIL = -3.0V for pulse width less than 10ns.
POWER SUPPLY CHARACTERISTICS1
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
PARAMETER
VCC Dynamic Operating
Supply Current
SYM
VCC = Max, CE\ = VIL,
ICC
IOUT = 0 mA, f = Max
VCC = Max, VIN = VIH or VIL
ISB
CE\ > VIH, f = Max
TTL Standby Current
(TTL Inputs)
ISB1
CMOS Standby Current
(CMOS Inputs)
-10
-12
-20
-15
MIN MAX MIN MAX MIN MAX MIN MAX UNIT
CONDITIONS
VCC = Max, VIN = VIH or VIL
CE\ > VIH, f = 0
VIN > VCC - 0.2V,
ISB2
or VIN < 0.2V, f = 0
---
160
---
140
---
130
---
120
mA
---
45
---
40
---
35
---
30
mA
---
30
---
30
---
30
---
30
mA
---
10
---
10
---
10
---
10
mA
NOTE: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE1,2
PARAMETER
SYMBOL CONDITIONS
MAX
UNIT
Input Capacitance
CIN
VIN = 0V
6
pF
Input/Output Capacitance
CI/O
VOUT = 0V
8
pF
NOTE:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1MHz, VCC = 3.3V.
AS5LC1008
Rev. 1.0 11/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
AS5LC1008
Austin Semiconductor, Inc.
READ CYCLE SWITCHING CHARACTERISTICS1
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
-10
PARAMETER
-12
-15
-20
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Read Cycle Time
tRC
10
---
12
---
15
---
20
---
ns
Address Access Time
tAA
---
10
---
12
---
15
---
20
ns
Output Hold time
tOHA
2
---
2
---
2
---
2
---
ns
CE\ Access Time
tACE
---
10
---
12
---
15
---
20
ns
OE\ Access Time
tDOE
---
5
---
6
---
7
---
8
ns
2
tLZOE
2
tHZOE
2
tLZCE
2
tHZCE
0
---
0
---
0
---
0
---
ns
0
5
0
6
0
7
0
8
ns
2
---
2
---
2
---
2
---
ns
0
5
0
6
0
7
0
8
ns
OE\ to Low-Z Output
OE\ to High-Z Output
CE\ to Low-Z Output
CE\ to High-Z Output
NOTES:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1 output loading specified
in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Rise and Fall Times
Input and Output timing and Reference Levels
Output Load
UNIT
0V to 3.0V
3ns
1.5V
See Figures 1 and 2
AC TEST LOADS
FIGURE 1
AS5LC1008
Rev. 1.0 11/02
FIGURE 2
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AS5LC1008
READ CYCLE #11,2
READ CYCLE #21,3
NOTES:
1. WE\ is HIGH for a Read Cycle.
2. The device is continuously selected. OE\, CE\ = VIL.
3. Address is valid prior to or coincident with CE\ LOW transitions.
AS5LC1008
Rev. 1.0 11/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
SRAM
AS5LC1008
Austin Semiconductor, Inc.
WRITE CYCLE SWITCHING CHARACTERISTICS1,3
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3V)
SYMBOL
-10
MIN
MAX
Write Cycle Time
tWC
10
---
12
---
15
---
20
---
ns
CE\ to Write End
tSCE
7
---
8
---
9
---
10
---
ns
Address Setup Time to Write End
tAW
8
---
9
---
10
---
12
---
ns
Address Hold from Write End
tHA
0
---
0
---
0
---
0
---
ns
Address Setup Time
tSA
0
---
0
---
0
---
0
---
ns
1
7
---
8
---
9
---
10
---
ns
2
10
---
12
---
12
---
15
---
ns
PARAMETER
WE\ Pulse Width (OE\ HIGH)
WE\ Pulse Width (OE\ LOW)
tPWE1
tPWE2
-12
MIN MAX
-15
MIN MAX
-20
MIN MAX UNITS
Data Setup to Write End
tSD
5
---
6
---
7
---
8
---
ns
Data Hold to Write End
tHD
0
---
0
---
0
---
0
---
ns
2
---
5
---
6
---
7
---
8
ns
2
2
---
2
---
2
---
2
---
ns
WE\ LOW to High-Z Output
WE\ HIGH to Low-Z Output
tHZWE
tLZWE
NOTES:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in
Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
WRITE CYCLE #11,2 (CE\ Controlled, OE\ = HIGH or LOW)
AS5LC1008
Rev. 1.0 11/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
SRAM
Austin Semiconductor, Inc.
AS5LC1008
WRITE CYCLE #21 (WE\ Controlled, OE\ = HIGH during Write Cycle)
WRITE CYCLE #3 (WE\ Controlled, OE\ = LOW during Write Cycle)
NOTES:
1. The internal write time is defined by the overlap of CE\ LOW and WE\ LOW. All signals must be in valid states to initiate a Write, but any one can go
inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE\ • VIH.
AS5LC1008
Rev. 1.0 11/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
SRAM
Austin Semiconductor, Inc.
AS5LC1008
MECHANICAL DEFINITION*
ASI Case #906 (Package Designator DJ)
SYMBOL
A
A1
A2
B
b
C
D
E
E1
E2
e
ASI SPECIFICATIONS
MIN
MAX
0.128
0.148
0.025
--0.082
--0.015
0.020
0.026
0.032
0.007
0.013
0.820
0.830
0.435
0.445
0.395
0.405
0.370 BSC
0.050 BSC
* All measurements are in inches.
AS5LC1008
Rev. 1.0 11/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SRAM
AS5LC1008
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #501 (Package Designator DCJ)
POSSIBLE FUTURE OFFERING, CONTACT FACTORY
A
D
e
D1
B1
E2
b
E1
E
A2
SYMBOL
A
A2
B1
B1
D
D1
E
E1
E2
e
ASI SPECIFICATIONS
MIN
MAX
0.132
0.144
0.026
0.036
0.030
0.040
0.015
0.019
0.812
0.828
0.740
0.760
0.405
0.415
0.435
0.445
0.360
0.380
0.050 BSC
*All measurements are in inches.
AS5LC1008
Rev. 1.0 11/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SRAM
AS5LC1008
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS5LC1008DJ-12/XT
Device Number
Package
Type
Speed
ns
Process
AS5LC1008
DJ
-10
/*
AS5LC1008
DJ
-12
/*
AS5LC1008
DJ
-15
/*
AS5LC1008
DJ
-20
/*
EXAMPLE: AS5LC1008DCJ-10/IT
Device Number
Package
Type
Speed
ns
Process
AS5LC1008
DCJ
-10
/*
AS5LC1008
DCJ
-12
/*
AS5LC1008
DCJ
-15
/*
AS5LC1008
DCJ
-20
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Military Temperature Range
AS5LC1008
Rev. 1.0 11/02
-40oC to +85oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10