FLASH AUSTIN SEMICONDUCTOR, INC. AS8F1M32 Austin Semiconductor, Inc. FIGURE 1: PIN ASSIGNMENT (Top View) 1M x 32 FLASH 68 Lead CQFP OPTION • Timing 90ns 120ns 150ns 62 61 65 63 64 67 66 01 02 68 05 03 06 04 59 12 78 13 57 14 76 I/O5 I/O6 I/O7 GND I/O8 I/O9 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 43 42 41 40 39 38 37 I/O16 I/O17 I/O18 A17 WE2\ WE3\ WE4\ A18 A19 NC 36 35 34 VCC A11 A12 A13 A14 A15 A16 CS1\ OE\ CS2\ 33 44 32 45 26 31 25 27 I/O10 I/O11 I/012 I/O13 I/O14 I/O15 GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8F1M32 is a 32 Mbit, 5.0 voltonly Flash memory. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. The AS8F1M32 offers an access time of 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE\), write enable (WE\) and output enable (OE\) controls. The device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply FLASH standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-matching that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other FLASH or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically time the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the DQ7 (DATA\ Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. MARKING -90 -120 -150 • Packages Ceramic Quad Flat Pack (0.88" sq) - MAX height .140" - Stand-off Height .035" min 60 11 30 • Fast access times of 90ns, 120ns, and 150ns • 5.0V ±10%, single power supply operation • Low power consumption typical: 4µA typical CMOS stand-by * ICC(active) <120mA for READ/WRITE • 20 year DATA RETENTION at 125oC • 1,000,000 program/erase cycles • 16 equal sectors of 64 Kbytes each • Any combination of sectors can be erased • Group sector protection • Supports FULL chip erase • Compatible with JEDEC standards • Embedded erase and program algorithms • Data\ polling and toggle bits for detection of program or erase cycle completion. • Erase suspend/resume • Hardware reset pin (RESET\) • Built in decoupling caps and multiple ground pins for low noise operation • Separate power and ground planes to improve noise immunity 07 09 FEATURES 10 29 • Military Processing (MIL-PRF-38534, para 1.2) • Temperature Range -55oC to 125oC I/O0 I/O1 I/02 I/O3 I/O4 28 AVAILABLE AS MILITARY SPECIFICATIONS 08 RESET\ A0 A1 A2 A3 A4 A5 CS3\ GND CS4\ WE1\ A6 A7 A8 A9 A10 VCC FLASH MEMORY MODULE QT For more products and information please visit our web site at www.austinsemiconductor.com (continued on page 2) AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F1M32 GENERAL DESCRIPTION (cont.) The Sector Erase Architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware Data Protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The Hardware Sector Protection feature disables both program and erase operations in any combinations of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The Hardware RESET\ pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET\ pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the FLASH memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. FIGURE 2: FUNCTIONAL BLOCK DIAGRAM WE 1\, CS1\ WE 2\, CS2\ WE 3\, CS3\ WE 4\, CS4\ RESET\ OE\ A0 - A19 1M x 8 1M x 8 8 8 I/O0-7 I/O8-15 1M x 8 8 I/O16-23 1M x 8 8 I/O24-31 PIN DESCRIPTION PIN DESCRIPTION I/O0-31 Data Inputs/Outputs A0-19 Address Inputs WE\ 1-4 Write Enables CS\1-4 Chip Selects OE\ Output Enable VCC Power Supply GND Ground RESET\ Reset AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F1M32 Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS..........................-2.0V to +7.0V Power Dissipation, PT.................................................................4W Storage Temperature, Tstg....................................-65°C to +125°C Operating Temperature.........................................-55°C to +125°C Short Circuit Output Current, IOS(1 output at a time)......100mA Endurance - Write/Erase Cycles ...................1,000,000 min cycles Data Retention...................................................................20 years *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics). ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (4.5V < VCC < 5.5V , -55°C < TA < +125°C) CONDITIONS SYMBOL MIN MAX UNITS Input Leakage Current DESCRIPTION VCC = 5.5, VIN = GND to V CC ILI -10 10 µA Output Leakage Current -10 VCC = 5.5, VIN = GND to V CC ILO 10 µA VCC Active Current for Read CS\ = VIL, OE\ = V IH ICC1 160 mA VCC Active Current for Program or Erase CS\ = VIL, OE\ = V IH ICC2 160 mA ISB 4 mA ICC3 8 mA 0.45 V VCC = 5.5V, All Inputs @ V CC - 0.2V or VSS +0.2V, VCC CMOS Standby RESET\ = CS\ 1-4 = VCC -0.2V VCC Standby Current VCC = 5.5, CS\ = V IH, RESET\ = V CC ± 0.3V, f=0 Output Low Voltage IOL = 12.0 mA, V CC = 4.5 VOL Output High Voltage IOH = -2.5 mA, V CC = 4.5 VOH 0.85 x VCC VLKO 3.2 Low VCC Lock-Out Voltage PARAMETER SYMBOL MIN TYP MAX UNIT Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 --- VCC + 0.5 V Input Low Voltage VIL -0.5 --- +0.8 V V 4.2 V CAPACITANCE (TA = +25°C)* PARAMETER SYM OE\ CONDITIONS MAX UNITS COE 50 pF WE\ 1-4 CWE 20 pF CS\1-4 CCS 20 pF Data I/O CI/O 50 pF Address input CAD 50 pF VIN = 0V, f = 1.0 MHz *Parameter is guaranteed, but not tested. AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F1M32 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (VCC = 5.0V, -55°C < TA < +125°C) PARAMETER SYM MIN WE\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) -90 MAX -120 MIN MAX -150 UNITS MIN MAX Write Cycle Time tAVAV tWC 90 120 150 ns Chip Select Setup Time tELWL tCS 0 0 0 ns Write Enable Pulse Width tWLWH tWP 45 50 50 ns Address Setup Time tAVWL tAS 0 0 0 ns Data Setup Time tDVWH tDS 45 50 50 ns Data Hold Time tWHDX tDH 0 0 0 ns Address Hold Time tWLAX tAH 45 50 50 ns tWHWL tWPH 20 Write Enable Pulse Width High Duration of Byte Progreamming Operation 1 2 Read Recovery Time before Write VCC Setup Time Chip Programming Time Chip Erase Time 20 300 8 tWHWH2 Sector Erase 20 300 tWHWH1 8 ns 300 µs 8 sec tGHWL 0 0 0 µs tVCS 50 50 50 µs 3 4 5 Output Enable Hold Time RESET\ Pulse Width READ-ONLY OPERATIONS 44 44 44 sec 256 256 256 sec tOEH 10 10 10 ns tRP 500 500 500 ns 90 Read Cycle Time tAVAV tRC Address Access Time tAVQV tACC 90 120 150 ns Chip Select Access Time tELQV tCE 90 120 150 ns Output Enable to Output Valid Chip Select High to Output High 6 6 Output Enable High to Output High Output Hold from Adresses, CS\ or OE\ Change, whichever is First 120 150 ns tGLQV tOE 40 50 55 ns tEHQZ tDF 20 30 35 ns tGHQZ tDF 20 30 35 ns tAXQX tOH 0 6 tReady RST Low to Read Mode CS\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) 0 20 0 20 ns 20 µs Write Cycle Time tAVAV tWC 90 120 150 ns Write Enable Setup Time tWLEL tWS 0 0 0 ns Chip Select Pulse Width tELEH tCP 45 50 50 ns Address Setup Time tAVEL tAS 0 0 0 ns Data Setup Time tDVEH tDS 45 50 50 ns Data Hold Time tEHDX tDH 0 0 0 ns Address Hold Time tELAX tAH 45 50 50 ns tEHEL tCPH 20 Chip Select Pulse Width High Duration of Byte Progreamming Operation Sector Erase Time 2 1 0 tGHEL Chip Programming Time Chip Erase Time 5 Output Enable Hold Time AS8F1M32 Rev. 1.5 09/05 8 0 44 256 4 tOEH 10 20 300 8 tWHWH2 Read Recovery Time 20 300 tWHWH1 µs 8 sec 44 256 µs sec sec 0 44 256 10 ns 300 10 ns Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F1M32 NOTES: 1. 2. 3. 4. 5. 6. Typical value for tWHWH1 is 7µs. Typical value for tWHWH2 is 1 sec. Typical value for Chip Programming is 14 sec. Typical value for Chip Erase Time is 32 sec. For Toggle and Data Polling. This parameter is guaranteed, but not tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels TYP UNIT V VIL = 0, VIH = 3.0 Input Rise and Fall 5 Input and Output Reference Level 1.5 Output Timing Reference Level 1.5 ns V V FIGURE 3: AC TEST CURRENT FIGURE 4: RESET Timing Diagram AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F1M32 Austin Semiconductor, Inc. Figure 5: AC Waveforms for READ Operations tRC Addresses Stable ADDRESS tACC CS\ tDF tOE OE\ tOEH WE\ tCE tOH High Z High Z Output Valid Outputs FIGURE 6: WE\ Controlled, WRITE/ERASE/PROGRAM Operation Program Command Sequence (last two cycles) tAS tWC ADDRESS Read Status Data ( last two cycles) PA PA 555h PA tAH CS\ tCH OE\ tWP tWHWH1 WE\ tCS tWPH tDS tDH A0h DATA Status PD DOUT tVCS 5.0 V NOTES: 1. 2. 3. 4. 5. PA is the address of the memory location to be programmed. PD is the data to be programmed at byte address. D7\ is the output of the complement of the data written to each chip. DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence. AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F1M32 Austin Semiconductor, Inc. Figure 7: AC Waveforms Chip/Sector Erase Operations Chip Sector Erase Erase 555H/SA tAH 555H ADDRESS 2AAH 2AAH 555H 555H tAS CS\ tGHWL OE\ tWP WE\ tWPH tCS tDH AAH tDS Data 55H 80H 55H AAH 10H/30H Chip Erase Vcc Sector Erase tVCS NOTES: 1. SA is the sector address for Sector ERASE. Figure 8: AC Waveforms for DATA\ Polling During Embedded Algorithm Operations ADDRESS VA VA tCH CS\ tDF tOH tOE OE\ tOEH WE\ tCE tOH Outputs D7 D7\ D7=Valid Data D0-D6=Status D0-D6= Valid Data High Z tWHWH 1 or 2 D0-D6 AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F1M32 Austin Semiconductor, Inc. FIGURE 9: Alternate CS\ Controlled Programming Operation Timings Program Command Sequence (last two cycles) tAS tWC ADDRESSES Read Status Data ( last two cycles) PA PA 555h PA tAH WE\ OE\ tWH tCP CS\ tWS tWHWH1 tCPH tDH A0H DATA D7\ PD DOUT tDS 5.0 V NOTES: 1. 2. 3. 4. 5. PA is the address of the memory location to be programmed. PD is the data to be programmed at byte address. D7\ is the output of the complement of the data written to each chip. DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence. AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F1M32 MECHANICAL DEFINITIONS* (Package Designator QT) AS8F1M32 Rev. 1.5 09/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F1M32 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS8F1M32QT-90/MIL Device Number Package Type Speed ns Process AS8F1M32 QT - 90 /* AS8F1M32 QT - 120 /* AS8F1M32 QT - 150 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range Q = MIL-PRF-38534, para 1.2 AS8F1M32 Rev. 1.5 09/05 Temperature -40oC to +85oC -55oC to +125oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10