AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 FIGURE 1: PIN ASSIGNMENT (Top View) 2M x 32 FLASH 68 Lead CQFP FLASH MEMORY MODULE AVAILABLE AS MILITARY SPECIFICATIONS • Military Processing (MIL-STD-883C para 1.2.2) • Temperature Range -55C to 125C FEATURES • Fast access times of 90ns, 120ns, and 150ns • 5.0V ±10%, single power supply operation • Low power consumption(TYP): 4µA CMOS stand-by * TYP ICC(active) <120mA for READ/WRITE • 20 year DATA RETENTION • Minimum 1,000,000 Program/Erase Cycles per sector guaranteed • 32 equal sectors of 64 Kbytes each • Any combination of Sectors can be Erased • Group Sector Protection • Supports FULL Chip Erase • Compatible with JEDEC standards • Embedded Erase and Program Algorithms • Data\ Polling and Toggle bits for detection of program or erase cycle completion. • Erase Suspend/Resume • Hardware Reset pin (RESET\) • Built in Decoupling Caps and Multiple Ground Pins for Low Noise Operation • Separate Power and Ground Planes to improve noise immunity OPTION • Timing 90ns 120ns 150ns GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8F2M32 is a 64 Mbit, 5.0 voltonly Flash memory. This device is designed to be programmed insystem with the standard system 5.0 volt VCC supply. The AS8F2M32 offers an access time of 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE\), write enable (WE\) and output enable (OE\) controls. The device requires only a single 5.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply FLASH standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-matching that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reaching data out of the device is similar to reading from other FLASH or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically time the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY\ pin, or by reading the DQ7 (DATA\ Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. MARKING -90 -120 -150 • Packages Ceramic Quad Flat Pack (0.88" sq) - MAX height .140" - Stand-off Height .035" min Q For more products and information please visit our web site at www.austinsemiconductor.com (continued on page 2) AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 GENERAL DESCRIPTION (cont.) The Sector Erase Architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware Data Protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The Hardware Sector Protection feature disables both program and erase operations in any combinations of the sectors of memory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data form, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The Hardware RESET\ pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET\ pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the FLASH memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. FIGURE 2: FUNCTIONAL BLOCK DIAGRAM WE 1\, CS1\ WE 2\, CS2\ WE 3\, CS3\ WE 4\, CS4\ RESET\ OE\ A0 - A20 2M x 8 2M x 8 8 8 I/O0-7 I/O8-15 2M x 8 8 I/O16-23 2M x 8 8 I/O24-31 PIN DESCRIPTION PIN I/O0-31 DESCRIPTION Data Inputs/Outputs A0-20 Address Inputs WE\1-4 Write Enables CS\1-4 Chip Selects OE\ Output Enable VCC Power Supply GND Ground RESET\ Reset AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F2M32 Austin Semiconductor, Inc. ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS, VT**..............-2.0V to +7.0V Power Dissipation, PT...............................................................4W Storage Temperature, Tstg..................................-65°C to +125°C Short Circuit Output Current, IOS(1 output at a time)......100mA Endurance - Write/Erase Cycles ....................100,000 min cycles Data Retention...................................................................20 years *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow, and humidity (plastics). ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (4.5V < VCC < 5.5V , -55°C < TA < +125°C) CONDITIONS SYMBOL MIN MAX UNITS Input Leakage Current DESCRIPTION VCC = 5.5, VIN = GND to V CC ILI -10 10 µA Output Leakage Current -10 VCC = 5.5, VIN = GND to V CC ILOx32 10 µA VCC Active Current for Read CS\ = VIL, OE\ = V IH ICC1 160 mA VCC Active Current for Program or Erase CS\ = VIL, OE\ = V IH ICC2 240 mA ISB 4 mA ICC3 8 mA 0.45 V VCC = 5.5V, All Inputs @ V CC - 0.2V or VSS +0.2V, VCC CMOS Standby RESET\ = CS\ 1-4 = VCC -0.2V VCC Standby Current VCC = 5.5, CS\ = V IH, RESET\ = V CC ± 0.3V, f=0 Output Low Voltage IOL = 12.0 mA, V CC = 4.5 VOL Output High Voltage IOH = -2.5 mA, V CC = 4.5 VOH 0.85 x VCC VLKO 3.2 Low VCC Lock-Out Voltage PARAMETER SYMBOL MIN TYP MAX UNIT Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 --- VCC + 0.5 V Input Low Voltage VIL -0.5 --- +0.8 V V 4.2 V CAPACITANCE (TA = +25°C)* PARAMETER SYM OE\ CONDITIONS MAX UNITS COE 50 pF WE\ 1-4 CWE 50 pF CS\1-4 CCS 20 pF Data I/O CI/O 20 pF Address input CAD 50 pF VIN = 0V, f = 1.0 MHz *Parameter is guaranteed, but not tested. AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F2M32 Austin Semiconductor, Inc. ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (VCC = 5.0V, -55°C < TA < +125°C) PARAMETER SYM MIN WE\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) Write Cycle Time tAVAV -90 MAX 90 tWC -120 MIN MAX -150 UNITS MIN MAX 120 150 ns Chip Select Setup Time tELWL tCS 0 0 0 ns Write Enable Pulse Width tWLWH tWP 45 50 50 ns Address Setup Time tAVWL tAS 0 0 0 ns Data Setup Time tDVWH tDS 45 50 50 ns Data Hold Time tWHDX tDH 0 0 0 ns Address Hold Time tWLAX tAH 45 50 50 ns tWHWL tWPH 20 20 20 ns Write Enable Pulse Width High 1 Duration of Byte Progreamming Operation 2 Sector Erase Read Recovery Time before Write VCC Setup Time tWHWH1 300 300 300 µs tWHWH2 15 15 15 sec tGHWL 0 0 0 µs tVCS 50 50 50 µs 3 Chip Programming Time 4 Chip Erase Time 5 Output Enable Hold Time RESET\ Pulse Width 44 44 44 sec 256 256 256 sec tOEH 10 10 10 ns tRP 500 500 500 ns 90 READ-ONLY OPERATIONS Read Cycle Time tAVAV tRC Address Access Time tAVQV tACC 90 120 150 ns tELQV tCE 90 120 150 ns Chip Select Access Time Output Enable to Output Valid 6 Chip Select High to Output High 6 Output Enable High to Output High Output Hold from Adresses, CS\ or OE\ Change, whichever is First 120 150 ns tGLQV tOE 40 50 55 ns tEHQZ tDF 20 30 35 ns tGHQZ tDF 20 30 35 ns tAXQX tOH 0 6 0 20 tReady RST Low to Read Mode CS\ CONTROLLED (WRITE/ERASE/PROGRAM OPERATIONS) 0 20 ns 20 µs Write Cycle Time tAVAV tWC Write Enable Setup Time tWLEL tWS 0 0 0 ns Chip Select Pulse Width tELEH tCP 45 50 50 ns 90 120 150 ns Address Setup Time tAVEL tAS 0 0 0 ns Data Setup Time tDVEH tDS 45 50 50 ns Data Hold Time tEHDX tDH 0 0 0 ns Address Hold Time tELAX tAH 45 50 50 ns Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns 1 Duration of Byte Progreamming Operation 2 Sector Erase Time Read Recovery Time tWHWH1 300 300 300 µs tWHWH2 15 15 15 sec 44 sec 256 sec 0 tGHEL 3 4 5 Output Enable Hold Time 10 tOEH 0 44 256 Chip Erase Time AS8F2M32 Rev. 2.5 05/09 0 44 Chip Programming Time 256 10 10 µs ns Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 NOTES: 1. 2. 3. 4. 5. 6. Typical value for tWHWH1 is 7µs. Typical value for tWHWH2 is 1 sec. Typical value for Chip Programming is 14 sec. Typical value for Chip Erase Time is 32 sec. For Toggle an Data Polling. This parameter is guaranteed, but not tested. AC TEST CONDITIONS PARAMETER Input Pulse Levels TYP UNIT V VIL = 0, VIH = 3.0 Input Rise and Fall 5 Input and Output Reference Level 1.5 Output Timing Reference Level 1.5 ns V V FIGURE 3: AC TEST CURRENT FIGURE 4: RESET Timing Diagram AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 FIGURE 5: AC Waveforms for READ Operations FIGURE 6: WE\ Controlled, WRITE/ERASE/PROGRAM Operation NOTES: 1. 2. 3. 4. 5. PA is the address of the memory location to be programmed. PD is the data to be programmed at byte address. D7\ is the output of the complement of the data written to each chip. DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence. AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 FIGURE 7: AC Waveforms Chip/Sector ERASE Operations NOTES: 1. SA is the sector address for Sector ERASE. FIGURE 8: AC Waveforms for DATA\ Polling During Embedded Algorithm Operations AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 FIGURE 9: Alternate CS\ Controlled Programming Operation Timings NOTES: 1. 2. 3. 4. 5. PA is the address of the memory location to be programmed. PD is the data to be programmed at byte address. D7\ is the output of the complement of the data written to each chip. DOUT is the output of the data written to the device. Figure indicates last two bus cycles of four bus cycle sequence. AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 MECHANICAL DEFINITION ASI Case #703 (Package Designator QW) NOTES: 1. Dimensions are shown as millimeters(inches). AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 MECHANICAL DEFINITIONS* (Package Designator QT) AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 FLASH AUSTIN SEMICONDUCTOR, INC. AS8F2M32 Austin Semiconductor, Inc. ORDERING INFORMATION EXAMPLE: AS8F2M32QW-120/XT Device Number Package Type Speed ns Process AS8F2M32 QW - 90 /* AS8F2M32 QW - 120 /* AS8F2M32 QW - 150 /* EXAMPLE: AS8F2M32QT-90/MIL Device Number Package Type Speed ns Process AS8F2M32 Q - 90 /* AS8F2M32 Q - 120 /* AS8F2M32 Q - 150 /* *AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range MIL = MIL-STD-883C para 1.2.2 Processing Temperature -40oC to +85oC -55oC to +125oC -55oC to +125oC NOTE: QW package is planned future offering AS8F2M32 Rev. 2.5 05/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. FLASH AS8F2M32 DOCUMENT TITLE 64Mb, 2M x 32 Flash Memory Module REVISION HISTORY Rev # 2.5 AS8F2M32 Rev. 2.5 05/09 History Updated Order Chart (QT to Q) Release Date May 2009 Status Release Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12