SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 128K x 16 SRAM & PIN ASSIGNMENT (Top View) 512K x 16 FLASH SRAM / FLASH MEMORY ARRAY 68 Lead CQFP (QT) NC A0 A1 A2 A3 A4 A5 FCS\1 GND FCS\2 SWE\1 A6 A7 A8 A9 A10 VCC FEATURES • Operation with single 5V supply • High speed: 35ns SRAM, 90ns FLASH • Built in decoupling caps and multiple ground pins for low noise • Organized as 128K x 16 SRAM and 512K x 16 FLASH • Low power CMOS • TTL Compatible Inputs and Outputs • Both blocks of memory are user configurable as 256K x 8 FLASH MEMORY FEATURES • • • Operation with single 5V (±10%) Eight equal sectors of 64K bytes Any combination of sectors can be concurrently erased Supports full chip erase Embedded erase and program algorithms 20,000 program/erase cycles Hardware write protection OPTIONS MARKINGS • Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) • Timing SRAM 35ns NC NC A18 FWE\2 FWE\1 SWE\2 A17 SCS\2 OE\ SCS\1 A16 A15 A14 A13 A12 A11 VCC • • • • FI/O 0 FI/O 1 FI/O 2 FI/O 3 FI/O 4 FI/O 5 FI/O 6 FI/O 7 GND FI/O 8 FI/O 9 FI/O 10 FI/O 11 FI/O 12 FI/O 13 FI/O 14 FI/O 15 SI/O 0 SI/O 1 SI/O 2 SI/O 3 SI/O 4 SI/O 5 SI/O 6 SI/O 7 GND SI/O 8 SI/O 9 SI/O 10 SI/O 11 SI/O 12 SI/O 13 SI/O 14 SI/O 15 FLASH 90ns PIN DESCRIPTION XT IT -35 • Package Ceramic Quad Flatpack QT PIN A 0-18 FUNCTION Address Inputs SI/O 0-15 SRAM Data Input / Outputs FI/O 0-15 OE\ SWE\ 1-2 FLASH Data Input / Outputs Output Enable SRAM Write Enables FWE\ FLASH Write Enables 1-2 SCS\ 1-2 SRAM Chip Selects FCS\ 1-2 FLASH Chip Selects VCC GND NC Power Supply Ground No Connect GENERAL DESCRIPTION The Austin Semiconductor, Inc. AS8SF384K32 is a 2 MEG CMOS SRAM and 8 MEG CMOS FLASH Module organized as 128K x 16 (SRAM) and 512K x 16 (FLASH). These devices achieve high speed access, low power consumption and high reliability by employing advanced CMOS memory technology. For more detailed information regarding the FLASH internal operations, programming, command definitions and functional descriptions, please see the AS8F512K32 data sheet located on our website at www.austinsemiconductor.com AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. FCS\2 FEW\2 AS8SF384K32 SRAM 128K x 8 M1 SCS\2 SWE\2 / A0-A16 / A0-A16 FI/O 8 - FI/O 15 FI/O 0 -FI/O 7 SI/O 8 - SI/O 15 SRAM 128K x 8 M0 SCS\1 SWE\1 OE\ A0 - A18 FLASH 512K x 8 M2 FCS\1 FWE\1 FLASH 512K x 8 M3 SI/O 0 - SI/O 7 BLOCK DIAGRAM SRAM TRUTH TABLE MODE Read OE\ L SCS\ L SWE\ H I\0 DOUT POWER Active Write Standby X X L H L X DIN High Z Active Standby FLASH TRUTH TABLE OPERATION Read Output Disable Standby and Write Inhibit Write Sector Protect Verify Sector Protect Sector Unprotect Verify Sector Unprotect Erase Operations USER BUS OPERATIONS FCS\1-4 OE\ FWE\1-4 A0 A1 A6 A9 L L H X X X X L H H X X X X H X X X X X X L H L A0 A1 A6 A9 L VID L X X X VID L L H H H L VID see note 2 see note 2 L H H H see note 2 L L H H H H VID L H see note 1 see note 1 see note 1 see note 1 see note 1 I/O Data Out High Z High Z Data In X Data Out Data Out Data Out see note 1 LEGEND: L = VIL, H = VIH, X = Don't Care, VID = 12V, See DC Charateristics for voltage levels NOTE: 1. See Chip/Sector Erase Operation Timings and Alternate CE\ Controlled Write Operation Timings of AS8F512K32 data sheet. 2. See Chart 1 (pg. 6) of AS8F512K32 data sheet. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 2 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. This is a stress rating only and functional operation on the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See the Application Information section at the end of this datasheet for more information. ABSOLUTE MAXIMUM RATINGS* Voltage of Vcc Supply Relative to Vss......................-.5V to +7V Storage Temperature............................................-65°C to +150°C Short Circuit Output Current(per I/O).................................20mA Voltage on Any Pin Relative to Vss....................-.5V to Vcc+1V Maximum Junction Temperature**...................................+150°C *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. PARAMETER Flash Data Retention Flash Endurance (write / erase cycles) AS8SF384K32 10 years 20,000 ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < 125oC and -40oC to +85oC; Vcc = 5V +10%) SRAM SRAM PARAMETER Input High (Logic 1) Voltage Input Low (Logic 1) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Power Supply Operating Current: Power Supply Current: Standby CONDITION SYMBOL VIH VIL ILI ILO VOH VOL Vcc OV < VIN < Vcc Output(s) disabled, OV < VOUT < Vcc IOH = -4.0 mA, Vcc = 4.5 IOL = 8.0 mA, Vcc = 4.5 SCS\<VIL; VCC = MAX f = MAX = 1/ tRC (MIN) Outputs Open, X16 SCS\>VIH; VCC = MAX f = MAX = 1/ tRC (MIN) Outputs Open, X16 MIN 2.2 -0.5 -10 -10 2.4 -4.5 MAX VCC +0.3 0.8 10 10 -0.4 5.5 UNITS V V P$ P$ V V V NOTES 1 1, 2 Icc 325 mA 3 ISBT1 20 mA 3 1 1 1 1. All voltages referenced to VSS (GND). 2. -2V for pulse width <20ns. 3. ICC is dependent on output loading and cycle rates. The specified value applies with the outputs FLASH PARAMETER Vcc Active Current Vcc Active Current1, 2 Output Low Voltage CONDITION SYMBOL CE\ = VIL, OE\ = VIH, Vcc = Vcc ICC1 Max, f = 5MHz CE\ = VIL, OE\ = VIH, Vcc = Vcc Max, f = 5MHz IOL = 8mA, Vcc = Vcc Min MIN MAX UNITS NOTES -- 120 mA ICC2 -- 140 mA VOL -- 0.45 V 0.85 x Vcc VCC-0.4 -- V -- V V Output High Voltage IOH = -2.5mA, Vcc = Vcc Min VOH1 Output High Voltage Low VCC Lock Out Voltage IOH = -100m$VCC = Vcc Min VOH1 VLKO 3.2 NOTES: 1. Icc active while Embedded Program or Embedded Erase Algorithm is in progress. 2. Not 100% tested. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 3 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)1 CADD SYMBOL PARAMETER A0 - A18 Capacitance MAX 50 UNITS pF COE OE\ Capacitance 50 pF CWE, CCS WE\ and CS\ Capacitance 20 pF CIO I/O 0- I/O 31 Capacitance 20 pF NOTE: 1. This parameter is sampled. AC TEST CONDITIONS Test Specifications Input pulse levels.........................................VSS to 3V Input rise and fall times.........................................5ns Input timing reference levels...............................1.5V Output reference levels........................................1.5V Output load..............................................See Figure 1 IOL Current Source Device Under Test - + Vz = 1.5V (Bipolar Supply) + Ceff = 50pf Current Source NOTES: Vz is programmable from -2V to + 7V. IOL and IOH programmable from 0 to 16 mA. Vz is typically the midpoint of VOH and VOL. IOL and IOH are adjusted to simulate a typical resistive load circuit. AS8SF384K32 Rev. 1.2 06/05 IOH Figure 1 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTE 5) (-55oC<TA < 125oC and -40oC to +85oC; VCC = 5V +10%) SRAM AC DESCRIPTION SYMBOL READ CYCLE READ cycle time Address access time Chip select access time Output hold from address change Output enable to output valid 1 Chip select to output in low Z 1 Output enable to output in low Z 1 Chip disable to output in high Z 1 Output disable to output in high Z t RC AA t ACS t OH t AOE t LZCS t LZOE t HZCS t HZOE -35 UNITS MIN MAX 35 t 35 35 2 20 3 0 20 20 ns ns ns ns ns ns ns ns ns SRAM AC (SWE\ & SCS\ controlled) DESCRIPTION SYMBOL WRITE CYCLE WRITE cycle time Chip select to end of write Address valid to end of write Address setup time Address hold from end of write Data valid to end of write Data hold time WRITE pulse width 1 Output active from end of write 1 Write enable to output in High-Z t WC CW t AW t AS t AH t DS t DH t WP1 t LZWE t HZWE t -35 UNITS MIN MAX 35 25 25 0 0 20 0 25 2 20 ns ns ns ns ns ns ns ns ns ns 1. This parameter is guaranteed but not tested. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 SRAM READ CYCLE NO. 1 tRC A0-A16 SI/O0-15 tAA 1234 112345 1234 1 1234 12345 1 1234 1 DATA VALID PREVIOUS DATA VALID 1234 12345 1 1234 1 tOH SRAM READ CYCLE NO. 2 tRC ADDRESS tAA 1234 12345 12345678 1234 12345 12345678 12345 1234 12345678 SCS\ 12345 1234 12345678 1234 12345678 tACS t 1234 123456789012 1234 123456789012 LZCS 12345 1234 12345 123456789012 1234 123456789012 SOE\ 12345 12345 1234 123456789012 SI/O0-15 AS8SF384K32 Rev. 1.2 06/05 tAOE tLZOE HIGH IMPEDANCE 1234 1123 1234 1 1234 1123 1234 1 1234 11234 1 123 1234 11234 1 123 123456789 1234567 123456 123456789 1234567 123456 1234567 123456 123456789 123456789 1234567 123456 123456789 123456 t 123456789012 1234567 123456 HZCS 123456789012 1234567 123456 123456789012 1234567 123456 123456789012 1234567 123456 123456789012 1234567 123456 tHZOE DATA VALID Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 6 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 SRAM WRITE CYCLE NO. 1 (Chip Select Controlled) tWC A0-A16 t AW 12345 1234 12345678 1234 12345 12345678 12345 1234 12345678 SCS\ 12345 1234 12345678 12345 1234 12345678 tAS SWE\ SI/O0-15 tAH 1234567 123456789012 12345 123456789012 1234567 12345 123456789012 1234567 12345 1234567 12345 123456789012 123456789012 1234567 12345 tCW t WP1 1 123456 123456 123456 123456 tHZWE 1 12345678901234 1234 1 12345678901234 1 1234 1 12345678901234 1 1234 1 tDS tLZWE tDH DATA VALID 1234 1234 1234 1234 1234 1234 1234 WRITE CYCLE NO. 2 (Write Enable Controlled) tWC A0-A16 SCS\ SWE\ tAS 123456 123456 123456 123456 12345678 12345678 12345678 12345678 t AW tAH tCW 123456789012 123456 12345 123456789012 123456 12345 123456789012 123456 12345 123456789012 123456 12345 t WP2 1 tDS SI/O0-15 AS8SF384K32 Rev. 1.2 06/05 tDH DATA VALID Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 7 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 FLASH ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (READ ONLY) (-55°C < TA < 125°C; VCC = 5V -5%/+10%) Parameter Symbol JEDEC Std. Speed Options Parameter Description Test Setup CE\=VIL, OE\=VIL -35 Units Min 90 ns Max 90 ns tAVAV tRC Read Cycle Time (Note 3) tAVQV tACC Address to Output Delay tELQV tCE Chip Enable Low to Output Valid Max 90 ns tGLQV tOE Output Enable to Output Delay Max 35 ns Read Toggle and Data\Polling Chip Enable High to Output High Z (Note 2, 3) Output Enable to Output High Z (Note 2,3) Output Hold Time from Addresses, CE\ or OE\, Whichever Occurs First Min 0 ns Min 10 ns Max 20 ns 20 ns 0 ns tOEH tEHQZ tHZ tGHQZ tDF tAXQX tOH CE\=VIL, OE\=VIL Output Enable Hold Time (Note 3) Min NOTES: 1. See Test Specification for test conditions. 2. Output driver disable time. 3. Guaranteed but not Tested. Read Operation Timings t RC Addresses Stable Addresses t ACC FCS\ t t CE OE\ DF t OEH t CE FWE\ High-Z Outputs t Output Valid OH High-Z OV AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 8 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (-55°C < TA < 125°C; VCC = 5V +/- 10%) WRITE / ERASE / PROGRAM Erase and Program FWE\ Controlled Parameter Symbol JEDEC Std. tAVAV tWC Write Cycle Time Min Speed Options -90 90 tAVWL tAS Address Setup Time Min 0 ns Units ns tWLAX tAH Address Hold Time Min 45 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH tOES Write Enable High to Input Transition Output Enable Setup Time Read Recover time Before Write (OE\ high to FWE\ low) Min 0 0 ns Min ns tGHWL tGHWL tELWL tCS FSC\ Setup Time Min 0 ns tWHEH tCH FSC\ Hold Time Min ns tWLWH tWP Write Pulse Width Min 0 45 ns tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH2 tWHWH3 tVCHEL AS8SF384K32 Rev. 1.2 06/05 Parameter Description Min 0 ns tWHWH1 Programming Operation tWHWH2 Sector Erase Operation Min 300 us Max 15 sec tWHWH3 Chip Erase Operation VCC Setup Time Chip Program Time Max Min Max 120 50 11 sec us sec Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 Program Operation Timings t t WC 555h Addresses AS 123456 1234 12 12345 11 123456 1234 12 12345 123456 12 1234 12345 1 1234 123456 12 12345 1 PA t PA PA AH FCS\ t t GHWL CH OE\ t t WP WHWH1 FWE\ t CS FI/O0 - FI/O15 t DS AOh t t WPH DH Status PD DOUT t VCS Vcc NOTE: PA= Program Address, PD= Program data, DOUT is the true data at the program address. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 10 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 Chip/Sector Erase Operation Timings t t WC 2AAh Addresses SA 555h for Chip Erase FCS\ 123456 1234 12 12345 11 123456 1234 12 12345 123456 12 1234 12345 1 1234 123456 12 12345 1 AS t VA VA AH t t CH GHWL OE\ t t WP WHWH2 FWE\ t CS FI/O0 - FI/O7 or FI/O8 - FI/O15 t DS 55h t t t WPH DH In Progress 30th Complete 10 for Chip Erase VCS Vcc NOTE: SA= Sector Address. VA = Valid Address for reading status data. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 Data Polling Timings (During Embedded Algorithms) t RC Addresses VA t 12345 1234 1 12345 11 12345 1234 1 12345 1234 1 12345 12345 1 12345 1234 1 12345 1 12345 11234 12345 11 12345 11234 12345 12345 11234 12345 1 12345 11234 12345 1 VA VA ACC t CE FCS\ t CH t OE OE\ t t OEH FWE\ t FI/O7 or FI/O15 FI/O0 - FI/O6 or FI/O8 - FI/O14 DF OH Complement Complement True Valid Data High-Z Status Data Status Data True Valid Data High-Z NOTE: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Toggle Bit Timings ( During Embedded Algorithms) t RC Addresses VA t 12345 12345 12 1 12345 12345 12 1 1 1 12345 12345 12 1 12345 12345 12 1 1 12345 12345 12 1 1 123456 123456 123456 123456 VA VA VA ACC t CE FCS\ t CH t OE OE\ t FWE\ FI/O6 / FI/O2 or FI/O14 / FI/O10 t OEH t DF OH Valid Status Valid Status Valid Status Valid Status (first read) NOTE: VA=Valid address; not required for FI/O6 or FI/O14. Illustration shows first two status cycles after command sequence, last status read cycle, and array data read cycle. AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 12 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 MECHANICAL DEFINATIONS* Package Designator QT AS8SF384K32 Rev. 1.2 06/05 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 13 SRAM & FLASH Mixed Module Austin Semiconductor, Inc. AS8SF384K32 ORDERING INFORMATION EXAMPLE's: AS8SF384K32QT-35/XT or AS8SF384K32QT-35/MIL Package Device Number Speed ns Type AS8SF384K32 QT -35 Process /* *AVAILABLE PROCESSES /IT = Industrial Temperature Range /XT = Extended Temperature Range /MIL = MIL-STD-883 para.1.2.2. NC AS8SF384K32 Rev. 1.2 06/05 -40oC to +85oC -55oC to +125oC -55oC to +125oC Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 14