Features • Low-voltage and Standard-voltage Operation • • • • • • • • – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) Internally Organized 16,384 x 8 and 32,768 x 8 2-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 1 MHz (5V) and 400 kHz (2.7V) Compatibility 64-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms Typical) High Reliability – Endurance: 100,000 Write Cycles – Data Retention: 40 Years – ESD Protection: > 4000V 2-wire Serial EEPROM Smart Card Modules Description 128K (16,384 x 8) The AT24C128SC/256SC provides 131,072/262,144 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The devices are optimized for use in smart card applications where lowpower and low-voltage operation may be essential. The devices are available in several standard ISO 7816 smart card modules (see Ordering Information). The entire family is available in both high-voltage (4.5V to 5.5V) and low-voltage (2.7V to 5.5V) versions. All devices are functionally equivalent to Atmel Serial EEPROM products offered in standard IC packages (PDIP, SOIC, EIAJ, LAP), with the exception of the slave address and Write Protect functions which are not required for smart card applications. 256K (32,768 x 8) AT24C128SC AT24C256SC Pin Configurations Pad Name Description ISO Module Contact VCC Power Supply Voltage C1 GND Ground C5 SCL Serial Clock Input C3 SDA Serial Data Input/Output C7 NC No Connect C2, C4, C6, C8 Card Module Contact VCC NC Rev. 1661A–10/00 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Block Diagram Pin Description Memory Organization SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. AT24C128SC/256SC, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as 256/512 pages of 64bytes each. Random word addressing requires a 14/15-bit data word address. 2 AT24C128SC/256SC Powered by ICminer.com Electronic-Library Service CopyRight 2003 AT24C128SC/256SC Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +2.7V. Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (SCL) 6 pF VIN = 0V This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted). Symbol Parameter VCC1 Supply Voltage VCC2 Supply Voltage ICC1 Supply Current VCC = 5.0V Read at 400 kHz ICC2 Supply Current VCC = 5.0V Write at 400 kHz ISB1 Standby Current (2.7V option) VCC = 2.7V ISB2 Standby Current (5.0V option) VCC = 4.5 - 5.5V ILI Input Leakage Current VIN = VCC or GND ILO Output Leakage Current VOUT = VCC or GND VIL Input Low Level(1) VIH Input High Level(1) VOL Note: Output Low Level Test Condition VCC = 5.5V VCC = 3.0V Min Typ Max Units 2.7 5.5 V 4.5 5.5 V 1.0 2.0 mA 2.0 3.0 mA 0.5 µA VIN = VCC or GND 6.0 VIN = VCC or GND IOL = 2.1 mA 6.0 µA 0.10 3.0 µA 0.05 3.0 µA -0.6 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V 0.4 V 1. VIL min and VIH max are reference only and are not tested 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 AC Characteristics Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 2.7-volt Min 5.0-volt Symbol Parameter Max Min fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low 1.3 0.6 µs tHIGH Clock Pulse Width High 1.0 0.4 µs tAA Clock Low to Data Out Valid 0.05 tBUF Time the bus must be free before a new transmission can start(1) 1.3 0.5 µs tHD.STA Start Hold Time 0.6 0.25 µs tSU.STA Start Set-up Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Set-up Time 100 100 ns 400 (1) 0.9 0.05 Max Units 1000 kHz 0.55 µs 0.3 0.3 µs 300 100 ns tR Inputs Rise Time tF Inputs Fall Time(1) tSU.STO Stop Set-up Time 0.6 0.25 µs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time Endurance(1) 5.0V, 25°C, Page Mode Notes: 10 100K 10 100K ms Write Cycles 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ (2.7V, 5V), Input pulse voltages: 0.3VCC to 0.7VCC Input rise and fall times: ≤ 50ns Input and output timing reference voltages: 0.5VCC Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). 4 AT24C128SC/256SC ICminer.com Electronic-Library Service CopyRight 2003 ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C128SC/256SC features a low power standby mode which is enabled: a) upon powerup and b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition as SDA is high. AT24C128SC/256SC Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O tWR(1) Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Data Validity Start and Stop Definition Output Acknowledge 6 AT24C128SC/256SC Powered by ICminer.com Electronic-Library Service CopyRight 2003 AT24C128SC/256SC Device Addressing The 128K/256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices. The next three bits of the device address word are unused. These three unused bits should be set to “0”. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2). PAGE WRITE: The 128K/256K EEPROM is capable of 64byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3). The data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6). 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Figure 1. Device Address Figure 2. Byte Write Figure 3. Page Write Notes: 1. * = DON’T CARE bit 2. 8 † = DON’T CARE bit for the 128K AT24C128SC/256SC Powered by ICminer.com Electronic-Library Service CopyRight 2003 AT24C128SC/256SC Figure 4. Current Address Read Figure 5. Random Read Notes: 1. * = DON’T CARE bit 2. † = DON’T CARE bit for the 128K Figure 6. Sequential Read 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 AT24C128SC Ordering Information Package(1) Voltage Range Temperature Range AT24C128SC - 09AT - 2.7 AT24C128SC - 09BT - 2.7 AT24C128SC - 09CT - 2.7 AT24C128SC - 09DT - 2.7 M2 - A Module M2 - B Module M4 - C Module M4 - D Module 2.7V to 5.5V Commercial (0°C to 70°C) AT24C128SC - 09AT AT24C128SC - 09BT AT24C128SC - 09CT AT24C128SC - 09DT M2 - A Module M2 - B Module M4 - C Module M4 - D Module 4.5V to 5.5V Commercial (0°C to 70°C) Package(1) Voltage Range Temperature Range AT24C256SC - 09AT - 2.7 AT24C256SC - 09BT - 2.7 AT24C256SC - 09CT - 2.7 AT24C256SC - 09DT - 2.7 M2 - A Module M2 - B Module M4 - C Module M4 - D Module 2.7V to 5.5V Commercial (0°C to 70°C) AT24C256SC - 09AT AT24C256SC - 09BT AT24C256SC - 09CT AT24C256SC - 09DT M2 - A Module M2 - B Module M4 - C Module M4 - D Module 4.5V to 5.5V Commercial (0°C to 70°C) Ordering Code AT24C256SC Ordering Information Ordering Code Package Type(1) Note: 10 M2 - A Module M2 ISO 7816 Smart Card Module M2 - B Module M2 ISO 7816 Smart Card Module with Atmel Logo M4 - C Module M4 ISO 7816 Smart Card Module M4 - D Module M4 ISO 7816 Smart Card Module with Atmel Logo Formal drawings may be obtained from an Atmel Sales Office. AT24C128SC/256SC Powered by ICminer.com Electronic-Library Service CopyRight 2003 AT24C128SC/256SC Smart Card Modules M4 - C Module - Ordering Code: 09CT M2 - A Module - Ordering Code: 09AT Module Size: M2 Dimension(1): 12.6 x 11.4 mm Glob Top: Square: 8.6 x 8.6 mm Thickness: 0.58 mm max. Pitch: 14.25 mm Module Size: M4 Dimension(1): 12.6 x 12.6 mm Glob Top: Square: 8.6 x 8.6 mm Thickness: 0.58 mm Pitch: 14.25 mm M4 - D Module - Ordering Code: 09DT M2 - B Module - Ordering Code: 09BT Module Size: M2 Dimension(1): 12.6 x 11.4 mm Glob Top: Square: 8.6 x 8.6 mm Thickness: 0.58 mm max. Pitch: 14.25 mm Module Size: M4 Dimension(1): 12.6 x 12.6 mm Glob Top: Square: 8.6 x 8.6 mm Thickness: 0.58 mm max. Pitch: 14.25 mm Note: 1. The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e. a punched M2 module will yield 13.0 x 11.8 mm). 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-803-000 FAX (44) 1355-242-743 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail [email protected] Web Site http://www.atmel.com BBS 1-(408) 436-4309 © Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Printed on recycled paper. Terms and product names in this document may be trademarks of others. 1661A–10/00/xM Powered by ICminer.com Electronic-Library Service CopyRight 2003