AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller AT3210 16 Gray scales 160X160 STN LCD Controller REV 1.11 February 2002 Aimtron reserves the right without notice to change this circuitry and specifications. AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 1 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller Revision History Revision 1.11 (February 1,2002) . Modify FIRSTL register address from 2DH to 1DH . Modify some description of the frame rate and mod rate Revision 1.1 (January 29,2002) . Change pin numbers . Modify current consumption spec. Revision 1.0 (January 22,2002) . Add revision information . Modify the sequence the D1,D0 of the DFORMT register . Changes of the Aimtron address information AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 2 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller General Description The AT3210 is a dot matrix graphics STN LCD controller LSI that can be connected directly to the microprocessor. It can support up to 160X160/16 grayscales for B/W and color STN module with drivers. The AT3210 displays the data directly from the internal 160X160X4 graphic RAM. The microprocessor interface is 6800/8080-series compatible 8-bit interface or 4-wire serial interface. Features . Supports up to 160X160 / 16 grayscales graphic display . Directly interface to 4-bit interface LCD driver . Hardware pin selectable for 8-bit 6800-series Parallel Interface, 8-bit 8080-series Parallel Interface, or 4-wire Serial Peripheral Interface . Programmable gamma table . Auto increasement of the RAM address inside the display window . Single supply operation VDD=3.3V . 28 Pin SSOP package Functional Block Diagram VDD VSS RESET* PS1-0 FPDATA3-0 CS0* System RS Interface Data RAM 16 Grayscale .8-bit Bus 160X160X4Bits controller E/WR*/SCK FPSHIFT RW/RD*/SDA FPLINE FPFRAME MOD DB7-DB0 Timing Generator CS1 OSC XTALI XTALO AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 3 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller System Block Diagram CS1 CS* RS E RW 6800 series MPU FPSHIFT FPLINE AT3210 DB7-0 FPFRAME STN LCD MOD RESET FPDATA4-0 Fig 1. 6800 series MPU interface application CS1 CS* RS WR* RD* 8080 series MPU FPSHIFT FPLINE AT3210 DB7-0 FPFRAME STN LCD MOD RESET FPDATA4-0 Fig 2. 8080 series MPU interface application 3.3V Controller ROW DRIVER STN LCD DSC AT3210 COLUMN DRIVER V2 V3 V4 V5 Re -+ VLCD R -+ R -+ R -+ R R Contrast Adjust Fig 3. DSC system reference design AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 4 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller Pin Description Pin Name RESET* CS1 Pin Number I/O 19 Input 18 Input PS1,PS0 20, 21 Input CS0* RS 22 23 Input Input Pin Description Reset: logical ‘0’. Chip select. logical ‘0’ disable the crystal oscillator. logical ‘1’ enable the crystal oscillator. Select MPU interface. PS1 PS0 Mode ‘00’ : Reserved ‘01’ : 4-wire serial interface ‘10’ : 8080 8-bit mode ‘11’ : 6800 8-bit mode Chipselect : logical ‘0’ enable the MPU interface. Select register. Logical ‘0’: control index & data. Logical ‘1’: image data. E/WR*/SCK 24 Input For a 68-system bus interface, serves as an enable signal to activate data read/write operation. For an 80-system bus interface, serves as a write strobe signal and writes data at the low level For the serial interface,serves as a clock signal RW/RD*/SDA 25 Input For a 68-system bus interface, serves as a signal to select data read/write operation. Low: Write High: Read. For an 80-system bus interface, serves as a read strobe signal and reads data at the low level. For the serial interface,serves as a data signal. DB7-DB0 26,27,28,29, Bidirection Serves as a 8-bit bidirectional data bus. Fix 1,2,3,4,5 unused DB7-DB0 to the VDD or VSS level. FPDATA3-FPDATA0 9,8,7,6 Output LCD 4-bit data. FPSHIFT 10 Output LCD horizontal shift clock. FPLINE 12 Output LCD line pulse. FPFRAME 13 Output LCD frame pulse. MOD 11 Output LCD AC input. XTALI 16 Input Oscillator input/clock input. XTALO 17 Output Oscillator Output. VDD 14 Power 3.3V Power supply. VSS 15 Ground Ground pin. * All unused input pins must be tied to VDD or VSS AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 5 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller Package 209 ± 12 307 ± 16 402 ± 12 SSOP28 49 6± 2 Dimension in MIL 69 ± 4 2(min.) 12 ± 3 26 25*13=338 VSS XTALI XTALO CS1 RESET 22 PS1 PS0 23 CS0 24 RS 25 WR 26 RD 27 DB7 DB6 DB5 28 21 20 19 18 17 16 15 10 11 12 13 14 AT3210 6 7 8 9 DB4 DB3 DB2 DB1 DB0 FPDATA0 FPDATA1 FPDATA2 FPDATA3 VDD 5 FPFRAME 4 FPLINE 3 MOD 2 FPSHIFT 1 Functional Description AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 6 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller MPU interface The chip identifies the data bus signals by a combination of RS, RD(E), WR(RW) signals. The Interpretation and execution of command depends on the external clock. In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 series MPU interface, the interface is placed in a read mode when an ‘H’ signal is input to the RW terminal and placed in a write mode when a ‘L’ signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. (See the timming diagram regarding the timing.) When the serial interface is selected, the data is input in sequence starting with D7. The MPU data bus is used as the display data input when the RS pin is ‘1’. The interpretation of the data format depends on the DFORMAT command. If DFORMAT=0, the high nibble is the first pixel and the low nibble is the second pixel. If DFORMAT=1, the high nibble is the second pixel and the low nibble is the first pixel. If DFORMAT=2, the high nibble is the current pixel data and the low nibble is don’t care. If DFORMAT=3, the low nibble is the current pixel data and the high nibble is don’t care. Each MPU write cycle latches 2 pixel data when DFORMAT=0 or 1and 1 pixel data when DFORMAT=2 or 3. See Fig.6 and Fig. 7. The internal RAM will write these data only after 32 bits data is latched The write pulses of the MPU must be the multiples of 4 or 8 which depends on the DFORMAT. The read pulses of the MPU must be the multiples of 4 which is independant of the DFORMAT. If you want to read data from memory, one dummy read cycle must be asserted before the wanted data output. The first read/write data is determined by the internal row and column counter. See Fig. 8. The input/output direction of the MPU data bus is determined by the read/write operation. The data bus is at input state when the AT3210 detects a write operation. The data bus is at output state when the AT3210 detects a read operation. See Fig. 14. Note that the output state after a read operation will hold until the next write operation is detected. AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 7 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller Gamma look-up table Each pixel data is represented by 4-bit and the maximum gray scales can be shown at the same time is 16. The AT3210 has a 4-bit to 5-bit look-up table. User can select the desired 16 gray scales from the available 32 gray scales when the GAMMA32 command is set to ‘1’. If the GAMMA32 command is set to 0, there are only 16 gray scales can be selected. See Fig. 4. Each display data is modulated by 32 frames when GAMMA32=1. If GAMMA32=0, there is only 16 frames per picture. Pixel data (4 bits) ADDRESS LUT DATA Display data (5 bits) Fig.4 Gamma look-up table Panel size and window size Fig.5 is the illustration of the panel size and the display window. The maximum width and height of the panel size are both limited to 160. The display window is also adjustable by setting the (XWS,YWS) and ending (XWE,YWE). The column number indicated by the XWS or the XWE is (XWS*8) or (XWE*8). The panel size indicated by the XP is (XP*8). The XWS and XWE must be smaller than the XP and the YWS and YWE must be smaller than YP. The internal column counter will automatically increase between the XWS and XWE. The internal row counter will automatically increase between the YWS and YWE. Any write operation outside the window will not be displayed and overlaid by the background color. Address counter There are two address counters, row and column counter. The column and row counter will automatically increase according to the window setting during successive read/wrire of display memory (RS pin=’1’) if the ACINC command is set to ‘1’. User can directly write to the counters by the COLADR and ROWADR command. These counters will be update when the value of the COLADR or ROWADR is different from the internal value. The width of the data bus of the internal data ram is 32 bits. The display data will be written AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 8 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller into the memory after the 32 bits data is full. After the 32 bit data is written, the column counter is automatically increased by 1 if the ACINC is set to ‘1’. If DFORMAT is set as 0 or 1, the memory write operation will be executed after four successive MPU write cycles. If the DFORMAT is set as 2 or 3, the memory write operation will be executed after eight successive MPU write cycles. See Figure 6 and Figure 7.. Display mode There are two display modes : reverse and off. The display data will be reversed when DISPREV=1. The display data will be set to (15-BKCOLOR) when DISPOFF=1 and DISPREV=0. The display data will be set to BKCOLOR when DISPOFF=1 and DISPREV=1. Frame rate and MOD rate Each display data is modulated by 32 frames when GAMMA32=1. If GAMMA32=0, there is only 16 frames per picture. Frame rate can be adjusted by setting CLINE0—CLINE2. Lower frame rate consumes lower power. The display is likely to flick at low frame rate. Setting MODRATE register changes the MOD rate. The MODRATE is ideally the same value as the YP. AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 9 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller L X ( column) R (0,0) U Background (Xws*8,Yws) window start Y ( row) DISPLAY WINDOW (Xwe*8,Ywe) window end D (Xp*8,Yp) panel size Fig. 5 Panel size and display window AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 10 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller RS WR 1 (8080 series) 2 8-bits DB[7:0] (8-bits) 3 8-bits 4 8-bits 5 6 8-bits 8-bits 7 8-bits 8 8-bits 9 8-bits 8-bits Internal SRAM write (DFORMAT=0/1) Column counter n n+1 n+2 Fig. 6 Illustration of the MPU and internal SRAM write cycle (DFORMAT=0/1) RS WR 1 (8080 series) DB[7:0] (4-bits) Internal SRAM write 2 4-bits 3 4-bits 4 4-bits 5 4-bits 6 4-bits 7 4-bits 8 4-bits 9 4-bits 4-bits (DFORMAT=2/3) Column counter n n+1 Fig. 7 Illustration of the MPU and internal SRAM write cycle (DFORMAT=2/3) RS RD (8080 series) DB[7:0] (8-bits) dummy P[n] P[n+1] P[n+2] P[n+3] P[n+4] P[n+5] P[n+6] P[n+7] Fig. 8 Illustration of the dummy read cycle during read internal SRAM (Note: n is determined by the internal column counter and row counter) AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 11 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller Command Descriptions Double Byte Command (8080-series interface) *First byte command is the index of command register. Second byte command is the value of command register Command Command code (See Note 3) RS RD WR D7 D6 D5 D4 D3 D2 D1 D0 Display data write 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 Display data read 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a3 a2 a1 a0 0 0 0 d4 d3 d2 d1 d0 0 0 0 1 0 0 0 0 0 0 0 d4 d3 d2 d1 d0 0 0 0 1 0 0 0 1 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 0 1 0 0 0 0 d4 d3 d2 d1 d0 0 0 0 1 0 0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 1 0 0 0 0 0 d4 d3 d2 d1 d0 0 0 0 1 0 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1/0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1/0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1/0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1/0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1/0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 d1 d0 1 0 0 0 0 1 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 CLINE0 0 1 0 1 0 0 0 0 0 1 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 CLINE1 0 1 0 1 0 0 CLINE2 0 1 0 1 BKCOLOR 0 1 0 1 LUT XWS YWS XWE YWE XP YP ADC DISPREV DISPOFF SRESET COMDIR TEST FIRSTL 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 d3 d2 d1 d0 d15 d14 d13 d12 d11 0 0 0 0 0 0 1 0 d16 d10 d9 d8 Function Write display data into SRAM (One byte command). The write pulse of the MPU must be the multiples of 4 or 8 is dependant on the DFORMAT. (See Note 5) Read display data from SRAM (One byte command). The read pulse of the MPU must be the multiples is independant on the DFORMAT. (See Note 5) Set gamma table. Address(a3—a0) is from 0 to 15. Data(d4—d0) is from 0 to 31. (See Note 2) Window start column address = XWS * 8. Window start row address. Range is from 0 to 159. Window end column address = XWE*8. Window end row address. Range is from 0 to 159. Panel column size= XP *8. The minmum value of the XP is 3. Panel row size. Segment direction. (See Note 5) 0: LÆR 1: RÆL Display mode. 0:normal 1:reverse Display mode. 0:normal 1: off Set 0 then reset. (Note 1) After reset, all registers return to their default value. Row direction. 0: UÆD 1: DÆU Test mode. Set to 0 for normal operation. First line address. Frame rate=Fosc / (CLINE * (YP+1) ) Cline must be greater than 4*XP+12. (Note 4) Background color. AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 12 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller The pixel sequence of the 8-bit MPU data bus. (See Note 5) D1 D0 DB7--DB4 DB3--DB0 0 0 P0 P1 DFORMAT 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 d1 d0 0 1 P1 P0 1 0 P0 X 1 1 x P0 FPDIR 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1/0 GAMMA32 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1/0 ACINC 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1/0 COLADR 0 1 0 0 0 0 0 1 0 0 0 1 1 1 d4 d3 d2 d1 d0 ROWADR 0 1 0 0 0 1 0 1 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 MODRATE FPDATA direction. (See Note 5) MSB LSB ‘0’ : D3 D2 D1 D0 ‘1’ : D0 D1 D2 D3 The maxinum gray scales that LCD can be shown. ‘0: 16 gray scales. The gamma value written to the gamma table will be from 0 to 15. ‘1’: 32 gray scales. The gamma value written to the gamma table will be from 0 to 31. ‘0’Æ internal address counter is fixed when seccessive read/write data memory ‘1’Æ internal address counter automatically increases when seccessive read/write data memory Column address counter This value is written into the internal column counter when the COLADR or ROWADR is different from their old value. Row address counter This value is written into the internal row counter when the COLADR or ROWADR is different from their old value. (MODRATE + 1) is the number of FPLINEs between toggles of the MOD output signal. Note: 1. When software/hardware reset command is set,the register values return to their default value, but the contents of the SRAM do not change. AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 13 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller 2. Default value of gamma LUT GAMA[0] GAMA[1] GAMA[2] GAMA[3] 0 2 4 6 GAMA[8] GAMA[9] GAMA[10] GAMA[11] 8 9 10 11 GAMA[4] GAMA[5] GAMA[6] GAMA[7] 12 13 14 15 GAMA[12] GAMA[13] GAMA[14] GAMA[15] 19 23 27 31 3. Register default values( after software and hardware reset) XWS YWS XWE YWE XP YP ADC 0 0 19 159 19 159 0 DISPREV DISPOFF SRESET COMDIR TEST FIRSTL CLINE0 0 0 1 0 0 0 95 CLINE1 CLINE2 CLINE2 BKCOLOR DFORMAT GAMMA32 FPDIR 1 0 0 0 1 1 0 ACINC COLADR ROWADR MODRATE 1 0 0 159 4. The defaul LCD frame rate=27000000(Hz)/(159+1)(351) ~= 480 . Each picture needs 32 LCD frames(GAMMA32) for 16 grey levels display. The refresh rate of the image is 480/32=15 images/per second. 5. The order of the pixels displayed on the LCD depends on the setting of the ADC and FPDIR . See the following Table. The order of the input data from the MPU data bus follows the setting of the DFORMAT. If DFORMAT=0/1, two pixels is launched at each MPU write operation. If DFORMAT=2/3, only one pixel is launched at each MPU write operation. AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 14 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller ADC 0 0 1 1 FPDIR 0 1 0 1 0 1 P0 P1 P3 P2 P159 P158 P156 P157 2 P2 P1 P157 P158 3 P3 P0 P156 P159 COLUMN No. ……………………………… ……………………………… ……………………………… ……………………………… ……………………………… 156 P156 P159 P3 P0 157 P157 P158 P2 P1 158 P158 P157 P1 P2 159 P159 P156 P0 P3 AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 15 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller Timing Diagram 1 clks(min.) 1 clks(min.) RS RW 12clks(min.)(RW=1) 8clks(min.)(RW=0) E 4 clks(min.)(RW=1) 3 clks(min.)(RW=0) CS* D7-D0 (INPUT) D7-D0 (OUTPUT) Fig.9 Parallel 6800 series interface timing diagram RS CS* 1 clk(min.) 1 clk(min.) 8 clks(min.) WR 3 clks(min.) D7-D0 (INPUT) 12 clks(min.) 4 clks(min.) RD D7-D0 (OUTPUT) Fig.10_1 Parallel 8080 series interface timing diagram (RS=0/ RS=1,DFORMAT=0,1) AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 16 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller RS CS* 1 clk(min.) 1 clk(min.) 4 clks(min.) WR 2 clks(min.) D7-D0 (INPUT) 12 clks(min.) 4 clks(min.) RD D7-D0 (OUTPUT) Fig.10_2 Parallel 8080 series interface timing diagram (RS=1,DFORMAT=2,3) RS CS* 1 clk+10ns (min.) 1 clk+10ns (min.) SCK SDA Fig.11 Serial 4-wire interface timing diagram RS CS* SCK SDA D7 D6 D5 D4 D3 D2 D1 D0 Fig.12 Serial 4-wire data format AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 17 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller FPFRAME FPLINE MOD FPDATA[3:0] LINEn LINE1 LINE2 LINE3 LINE4 LINEM LINE1 FPLINE 2 clks 2 clks FPSHIFT FPDATA[3:0] 1 2 N-1 3 N **N=40 when horizontal resolution is 160 pixels N=30 when horizontal resolution is 120 pixels ** M=160 when vertical resolution is 160 lines M=120 when vertical resolution is 120 lines Fig.13 LCD Timing Diagram WR# RD# DB[7:0] input output input output Fig.14 The I/O direction of the MPU data bus (8080 interface) AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 18 AT3210 Preliminary Product Information 16 GrayScales 160X160 STN LCD Controller Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Operating Temperature Symbol Vdd Vt Topr Condictions Min 0 0 -20 Max 4 Vdd 70 Units V V ℃ Parameter Power Supply Voltage Current Consumption Symbol Vdd Icp Condictions Min 3.0 VDD=3.3V Clock=27MHz Typ 3.3 10 Max Units 3.6 V 11 mA Digital Outputs Output Currents(High) Output Currents(Low) Output Voltage(high) Output Voltage(high) Output Capacitance IoH IoL VoH VoL Co VDD=3.3V VDD=3.3V VDD=3.3V VDD=3.3V VDD=3.3V -1.1 2 Digital Inputs Input Voltage(High) Input Voltage(Low) Input Cuttent(High) Input Voltage(Low) Input capacitance ViH ViL IiH IiL Ci VDD=3.3V VDD=3.3V VDD=3.3V VDD=3.3V VDD=3.3V DC Characteristics 0 2 0 3.3 0.8 3 3.3 1 5 5 4 MA MA V V pF V uA uA PF AIMTRON TECHNOLOGY CORP. 2F,NO.10, Prosperity Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C Email: [email protected] Homepage:http://www.aimtron.com.tw Tel: 886-3-563-0878 Fax: 886-3-563-0879 Rev 1.11 Feb. 2002 19