ATMEL AT78C5009

Features
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Operates as Host Bridge Between Serial ATA and Parallel ATA interfaces
Ultra ATA100 Mode Supported with Rates up to 100 MB/s
Data is Transferred on Both Edges of the STROBE when in Ultra DMA Mode
16-bit CRC is Calculated on a Per-burst Basis
Ultra DMA5 Compliant Drive Interfaces
Compatible with 48-bit LBA Methods of Addressing
Dual 1024-byte Transmit/Receive FIFO for Overrun Prevention
8B/10B Encoding and Decoding in Serial ATA Link Layer
Low Power: < 380 mW
Supports PIO Modes 0, 1, 2, 3 and 4
Supports UDMA Modes 0, 1, 2, 3, 4, and 5
Supports 80-conductor Cable for UDMA Modes 4, and 5
Serial ATA Host
Bridge
Overview
The AT78C5009 SATA Controller bridges the conventional Parallel ATA devices with
Serial ATA PHY transceivers. It includes a Serial ATA Link layer, a Transport layer, a
Command Layer, two 256 x 32 FIFOs and an IDE Host/Target Controller, a Serial ATA
Core and an IDE Controller, and is fully compliant with Serial ATA Gen1. The PHY
block is connected to the ATA block by a 20-bit transmit and a 20-bit receive data bus.
This host bridge is intended to adapt a Serial ATA Device interface to an Ultra ATA100
Host interface. Ultra DMA is a data transfer protocol used with the READ DMA,
WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED, and PACKET
commands.
AT78C5009
Summary
3511AS–NETST–8/04
Note: This is a summary document. A complete document
is available under NDA. For more information, please contact your local Atmel sales office.
Figure 1. AT78C5009 Block/PAD Interconnect
Alternate PHY
Test Pin Functions
Rx[19:0], Receive Data Bus
ATA_DATA[15:0]
PHY_DATA[15:0]
ATA_ADR[2:0]
PHY_DATA[18:16]
RX+
Tx[19:0], Transmit Data Bus
RX-
PHY_TBC
ATA_IORDN
PHY_RBC
TBC (transmit byte clock 75 MHz)
ATA_HCS0
RX+
TX_ENABLE
ATA_HCS1
RX-
RBC (receive byte clock 75 MHZ)
ATA_IOCHRDY
COMMA_DETECT
1.5Gb/s
Transceiver
PHY_COMDET
ATA_PDIAGN
REALIGN
ATA_DASPN
PHY_DATA[19]
COMWAKE
ATA_CS
COMRI
ATA_INTRQ
ATA_DMARQ
PHY_RXLOCKED
PARTIAL
ATA_DMACKN
PHY_DIRECTION
SLUMBER
ATA_RESETN
STOP
ATA/Serial ATA
Controler
PHY_SLV
ATA_HOST
PHY_SLOP
RX_LOCKED
SCLK
TEST_MUX0
PHY_SCLK
RX_ERROR
SDEN
TEST_MUX1
PHY_SDEN
SDATA
TEST_MUX2
PHY_SDATA
EEPROM
TEST_MUX3
PHY_EWRAP
RESET
SCLK
SDEN
SDATA
TEST_ENABLE0N
ASIC_CKRATE
TEST_ENABLE1N
ASICLK
TEST_ENABLE2N
OSC
AMP
RESET
COMPARE
2
ATA_IOWRN
XTAL_IN
XTAL_OUT
PRESETN
PHY_RESET
AT78C5009
3511AS–NETST–8/04
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3511AS–NETST–8/04