Features • • • • • • • • • • • PLL Transmitter IC with Single-ended Output High Output Power (6 dBm) Low Current Consumption at 8.1 mA (315 MHz) and 8.5 mA (433 MHz) Divide by 24 (ATA8404) and 32 (ATA8405) Blocks for 13 MHz Crystal Frequencies and for Low XTO Start-up Times ASK/FSK Modulation with Internal FSK Switch Up to 20 kBaud Manchester Coding, Up to 40 kBaud NRZ Coding Power-down ENABLE Input for Parallel Usage of Controlling Pins Supply Voltage 2.0V to 3.6V ESD Protection at all Pins (4 kV HBM) Small Package TSSOP10 UHF ASK/FSK Industrial Transmitter Benefits ATA8404 ATA8405 • Low Parasitic FSK Switch Integrated • Fast Settling Time < 0.85 ms • Small Form Factor Applications • • • • • Preliminary Remote Control Systems Alarm, Telemetering, and Energy Metering Systems Home Entertainment and Home Automation Industrial/Aftermarket Remote Keyless Entry Systems Toys 1. Description The ATA8404/ATA8405 is a PLL transmitter IC, which has been developed for the demands of RF low-cost transmission systems at data rates up to 20 kBaud Manchester coding and 40 kBaud NRZ coding. The transmitting frequency range is 313 MHz to 317 MHz (ATA8404) and 432 MHz to 448 MHz (ATA8405), respectively. It can be used in both FSK and ASK systems. Figure 1-1. System Block Diagram UHF ASK/FSK TPM and Remote control transmitter UHF ASK/FSK Remote control receiver 1 Li cell ATA8201 ATA8202 Demod. ATA8203 ATA8204 ATA8404 ATA8405 Keys Encoder ATARx9x PLL Control 1...3 µC IF Amp Antenna Antenna XTO VCO Power amp. PLL LNA XTO VCO 9136C–INDCO–10/09 2. Pin Configuration Figure 2-1. Table 2-1. Pin 1 Pinning TSSOP10 CLK 1 10 ENABLE ASK 2 9 GND FSK 3 8 VS ANT2 4 7 XTO1 ANT1 5 6 XTO2 ATA8404 ATA8405 Pin Description Symbol CLK Function Configuration VS Clock output signal for the microcontroller. The clock output frequency is set by the crystal to fXTAL/8. The CLK output stays Low in power-down mode and after enabling of the PLL. The CLK output switches on if the oscillation amplitude of the crystal has reached a certain level. 100 100 200k ASK 2 ASK Switches on the power amplifier for ASK modulation and enables the PLL and XTO if the ENABLE pin is open. 50k 200k FSK 3 2 FSK CLK Switches off the FSK switch (switch has high Z if signal at pin FSK is High) and enables the PLL and the XTO if the ENABLE pin is open VRef = 1.1V 20 µA 200k VRef = 1.1V 5 µA 200k ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Table 2-1. Pin Description (Continued) Pin Symbol 4 ANT2 Function Configuration Emitter of antenna output stage ANT1 5 ANT1 Open collector antenna output ANT2 (FSK < 0.25V) AND (ENABLE > 1.7V) 6 XTO2 Diode switch, used for FSK modulation 210 µA XTO2 VS 1.2k 1.5k 7 XTO1 VS Connection for crystal XTO1 182 µA 8 VS 9 GND Supply voltage See ESD protection circuitry (see Figure 4-9 on page 14) Ground See ESD protection circuitry (see Figure 4-9 on page 14) VS ENABLE input 30 µA 10 ENABLE If ENABLE is connected to GND and the ASK or FSK pin is High, the device stays in idle mode. In normal operation ENABLE is left open and ASK or FSK is used to enable the device. (FSK >1.7 V ) OR (ASK > 1.7 V) ENABLE 150k 250k 3 9136C–INDCO–10/09 Figure 2-2. Block Diagram ATA8405 Power up/down CLK EN f 1 ENABLE 10 8 f 24/ 32 ASK GND 2 9 OR PFD FSK VS 3 8 CP Ampl. OK XTO1 ANT2 4 XTO 7 LF EN XTO2 ANT1 5 VCO PA 6 PLL 3. General Description This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature transmitters for remote control and other industrial applications. The VCO is locked to 24 × fXTAL/32 × fXTAL for ATA8404/ATA8405. Thus, a 13.125 MHz/13.56 MHz crystal is needed for a 315 MHz/433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance (current mode) oscillator. Only one capacitor and a crystal connected in series to GND are needed as external elements in an ASK system. The internal FSK switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator needs typically 0.6 ms until the CLK output is activated if a crystal as defined in the electrical characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter time will result. The CLK output is switched on if the amplitude of the current flowing through the crystal has reached 35% to 80% of its final value. This is synchronized with the 1.64/1.69 MHz CLK output. As a result, the first period of the CLK output is always a full period. The PLL is then locked < 250 µs after CLK output activation. This means an additional wait time of ≥ 250 µs is necessary before the PA can be switched on and the data transmission can start. This results in a significantly lower time of about 0.85 ms between enabling the ATA8404/ATA8405 and the beginning of the data transmission which saves battery power. 4 ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance and can therefore be controlled via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high power efficiency for the power amplifier results if an optimized load impedance of ZLoad, opt = 380Ω + j340Ω (ATA8404) at 315 MHz and ZLoad, opt = 280Ω + j310Ω (ATA8405) at 433.92 MHz is used at the 3-V supply voltage. 4. Functional Description If ASK = Low, FSK = Low, and ENABLE = open or Low, the circuit is in power-down mode consuming only a very small amount of current so that a lithium cell used as power supply can work for many years. If the ENABLE pin is left open, ENABLE is the logical OR operation of the ASK and FSK input pins. This means, the IC can be switched on by either the FSK of the ASK input. If the ENABLE pin is Low and ASK or FSK are High, the IC is in idle mode where the PLL, XTO, and power amplifier are off and the microcontroller ports controlling the ASK and FSK inputs can be used to control other devices. This can help to save ports on the microcontroller in systems where other devices with 3-wire interface are used. With FSK = High, ASK = Low, and ENABLE = open or High, the PLL and the XTO are switched on and the power amplifier is off. When the amplitude of the current through the crystal has reached 35% to 80% of its final amplitude, the CLK driver is automatically activated. The CLK output stays Low until the CLK driver has been activated. The driver is activated synchronously with the CLK output frequency, hence, the first pulse on the CLK output is a complete period. The PLL is then locked within < 250 µs after the CLK driver has been activated, and the transmitter is then ready for data transmission. With ASK = High, the power amplifier is switched on. This is used to perform the ASK modulation. During ASK modulation, the IC is enabled with the FSK or the ENABLE pin. With FSK = Low the switch at pin XTO2 is closed, with FSK = High the switch is open. To achieve a faster start-up of the crystal oscillator, the FSK pin should be High during start-up of the XTO because the series resistance of the resonator seen from pin XTO1 is lower if the switch is off. The different modes of the ATA8404/ATA8405 are listed in Table 4-1, the corresponding current consumption values can be found in the table “Electrical Characteristics” on page 15. Table 4-1. ATA8404/ATA8405 Modes ASK Pin FSK Pin ENABLE Pin Mode Low Low Low/open Power-down mode, FSK switch High Z Low Low High Power-up, PA off, FSK switch Low Z Low High High/open Power-up, PA off, FSK switch High Z High Low High/open Power-up, PA on, FSK switch Low Z High High High/open Power-up, PA on, FSK switch High Z Low/High High Low Idle mode, FSK switch High Z High Low/High Low Idle mode, FSK switch High Z 5 9136C–INDCO–10/09 4.1 4.1.1 Transmission with ENABLE = open ASK Mode The ATA8404/ATA8405 is activated by ENABLE = open, FSK = High, ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with FSK = Low. Figure 4-1. Timing ASK Mode with ENABLE not Connected to the Microcontroller ΔTXTO > 250 µs FSK ASK CLK Power-down 4.1.2 Power-up, PA off Power-up, PA on (High) Power-up, PA off (Low) Power-down FSK Mode The ATA8404/ATA8405 is activated by FSK = High, ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready. After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The ATA8404/ATA8405 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower; if FSK = H the output frequency is higher. After transmission, FSK stays High and ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with FSK = Low. Figure 4-2. Timing FSK Mode with ENABLE not Connected to the Microcontroller ΔTXTO > 250 µs FSK ASK CLK Power-down 6 Power-up, PA off Power-up, Power-up, PA on PA off (fRF = High) (fRF = Low) Power-down ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 4.2 4.2.1 Transmission with ENABLE = High FSK Mode The ATA8404/ATA8405 is activated by ENABLE = High, FSK = High, and ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The ATA8404/ATA8405 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower, if FSK = H output frequency is higher. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with ENABLE = Low and FSK = Low. Figure 4-3. Timing FSK Mode with ENABLE Connected to the Microcontroller ΔTXTO > 250 µs ENABLE FSK ASK CLK Power-down 4.2.2 Power-up, PA off Power-up, Power-up, PA off PA on (fRF = High) (fRF = Low) Power-down ASK Mode The ATA8404/ATA8405 is activated by ENABLE = High, FSK = High and ASK = Low. After activation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (the microcontroller waits until the XTO and CLK are ready). After another time period of ≤ 250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA8404/ATA8405 is switched to power-down mode with ENABLE = Low and FSK = Low. 7 9136C–INDCO–10/09 Figure 4-4. Timing ASK Mode with ENABLE Connected to the Microcontroller ΔTXTO > 250 µs ENABLE FSK ASK CLK Power-down 4.3 Power-up, Power-up, PA on PA off (High) (Low) Power-up, PA off Power-down Accuracy of Frequency Deviation The accuracy of the frequency deviation using the XTAL pulling method is about ±20% if the following tolerances are considered. One important aspect is that the values of C0 and CM of typical crystals are strongly correlated, which reduces the tolerance of the frequency deviation. Figure 4-5. Tolerances of Frequency Modulation ~ VS C Stray XTAL ~ CM LM RS C0 Crystal equivalent circuit C4 C5 CSwitch Using a crystal with a motional capacitance of CM = 4.37 fF ±15%, a nominal load capacitance of C LNOM = 18 pF and a parallel capacitance of C0 = 1.30 pF correlated with C M results in C0 = 297 × CM (the correlation has a tolerance of 10%, so C0 = 267 to 326 × CM). If using the internal FSK switch with CSwitch = 0.9 pF ±20% and estimated parasitics of CStray = 0.7 pF ±10%, the resulting C4 and C5 values are C4 = 10 pF ±1% and C5 = 15 pF ±1% for a nominal frequency deviation of ±19.3 kHz with worst case tolerances of ±15.8 kHz to ±23.2 kHz. 8 ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 4.4 Accuracy of the Center Frequency The imaginary part of the impedance in large signal steady state oscillation IMXTO, seen into the pin 7 (XTO1), causes some additional frequency tolerances, due to pulling of the XTO oscillation frequency. These tolerances have to be added to the tolerances of the crystal itself (adjustment tolerance, temperature stability and ageing) and the impact on the center frequency due to tolerances of C4, C5, CSwitch and CStray. The nominal value of IMXTO = 110Ω, CSwitch and CStray should be absorbed into the C4 and C5 values by using a crystal with known frequency and choosing C4 and C5, so that the XTO center frequency equals the crystal frequency, and the frequency deviation is as expected. Then, from the nominal value, the IMXTO has ±90Ω tolerances, using the pulling formula P = –IM X T O × C M × π × f X T O with f XTO = 13.56 MHz and C M = 4.4 fF an additional frequency tolerance of P = ±16.86 ppm results. If using crystals with other CM the additional frequency tolerance can be calculated in the same way. For example, a lower C M = 3.1 fF will reduce the frequency tolerance to 11.87 ppm, where a higher CM = 5.5 fF increases the tolerance to 21.07 ppm. 4.5 CLK Output An output CLK signal of 1.64 MHz (ATA8404 operating at 315 MHz) and 1.69 MHz (ATA8405 operating at 433.92 MHz) is provided for a connected microcontroller. The delivered signal is CMOS-compatible with a High and Low time of >125 ns if the load capacitance is lower than 20 pF. The CLK output is Low in power-down mode due to an internal pull-down resistor. After enabling the PLL and XTO the signal stays Low until the amplitude of the crystal oscillator has reached 35% to 80% of its amplitude. Then, the CLK output is activated synchronously with its output signal so that the first period of the CLK output signal is a full period. 4.5.1 Clock Pulse Take-over by Microcontroller The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s ATARx9x microcontroller family provides the special feature of starting with an integrated RC oscillator to switch on the ATA8404/ATA8405’s external clocking and to wait automatically until the CLK output of the ATA8404/ATA8405 is activated. After a time period of 250 µs the message can be sent with crystal accuracy. 4.5.2 Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad, opt = 380Ω + j340Ω (ATA8404) at 315 MHz and ZLoad, opt = 280Ω + j310Ω (ATA8405) at 433.92 MHz. A low resistive path to VS is required to deliver the DC current (see Figure 4-6 on page 10). The power amplifier delivers a current pulse and the maximum output power is delivered to a resistive load if the 0.66 pF output capacitance of the power amplifier is compensated by the load impedance. At the ANT1 pin, the RF output amplitude is about VS – 0.5V. The load impedance is defined as the impedance seen from the ATA8404’s ANT1, ANT2 into the matching network. Do not mix up this large-signal load impedance with a small-signal input impedance delivered as an input characteristic of RF amplifiers. The latter is measured from the application into the IC instead of from the IC into the application for a power amplifier. 9 9136C–INDCO–10/09 The output capacitance of 0.66 pF will be absorbed into the load impedance, so a real impedance of 684Ω (ATA8404) at 315 MHz and 623Ω (ATA8405) at 433.92 MHz should be measured with a network analyses at pin 5 (ANT1) with the ATA8404/ATA8405 soldered, an optimized antenna connected, and the power amplifier switched off. Less output power is achieved by lowering the real parallel part where the parallel imaginary part should be kept constant. Lowering the real part of the load impedance also reduces the supply voltage dependency of the output power. Output power measurement can be done with the circuit as shown in Figure 4-6. Please note that the component values must be changed to compensate for the individual board parasitics until the ATA8404/ATA8405 has the right load impedance. Also, the damping of the cable used to measure the output power must be calibrated. Figure 4-6. Output Power Measurement ATA8404/ATA8405 VS C1 = 1n ~ L1 = 68 nH/ 39 nH Power meter Z = 50 Ω Z Lopt C2 = 2.2 pF/1.8 pF ANT1 ANT2 Rin 50 Ω ~ Table 4-2 and Table 4-3 show the output power and the supply current versus temperature and supply voltage. Table 4-2. Ambient Temperature VS = 2.0V (dBm/mA) VS = 3.0V (dBm/mA) VS = 3.6V (dBm/mA) Tamb = –40°C 3.1 ±1.5 / 7.2 6.1 +2/–3 / 7.7 7.1 +2/–3 / 7.9 Tamb = +25°C 3.0 ±1.5 / 7.5 6.0 ±2 / 8.1 7.4 ±2 / 8.3 Tamb = +85°C 3.0 ±1.5 / 7.5 5.8 +2/–3 / 8.2 7.2 +2/–3 / 8.5 Table 4-3. 10 Output Power and Supply Current versus Temperature and Supply Voltage for the ATA8404 with ZLoad = 380Ω + j340Ω (Correlation Tested) Output Power and Supply Current versus Temperature and Supply Voltage for the ATA8405 with ZLoad = 280Ω + j310Ω (Correlation Tested) Ambient Temperature VS = 2.0V (dBm/mA) VS = 3.0V (dBm/mA) VS = 3.6V (dBm/mA) Tamb = –40°C 3.3 ±1.5 / 7.6 6.2 +2/–3 / 8.1 7.1 +2/–3 / 8.4 Tamb = +25°C 3.0 ±1.5 / 8.0 6.0 ±2 / 8.5 7.5 ±2 / 8.8 Tamb = +85°C 2.8 ±1.5 / 8.0 5.7 +2/–3 / 8.6 6.8 +2/–3 / 8.8 ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 4.6 Application Circuits For the supply voltage blocking capacitor C3, a value of 68 nF/X7R is recommended (see Figure 4-7 on page 12 and Figure 4-8 on page 13). C1 and C2 are used to match the loop antenna to the power amplifier. For C2, two capacitors in series should be used to achieve a better tolerance value and to enable it to realize ZLoad,opt by using capacitors with standard values. Together with the pins of ATA8404 and the PCB board wires, C1 forms a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally, the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (50 nH to 100 nH) can be printed on the PCB. C4 should be selected so that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 10 pF results in a 12 pF load-capacitance crystal due to the board parasitic capacitances and the inductive impedance of the XTO1 pin. 11 9136C–INDCO–10/09 Figure 4-7. ASK Application Circuit S1 BPXY S2 AVR® (ATtiny) VDD 1 VS VSS BPXY 20 BPXY OSC1 BPXY 7 ATA8404/ATA8405 Power up/down CLK 1 ENABLE EN f 10 8 f 24/ 32 ASK GND 2 9 OR C3 PFD FSK VS 3 8 CP C2 VS Ampl. OK ANT2 XTO1 XTO 4 Loop Antenna XTAL 7 LF C1 C4 EN ANT1 5 L1 XTO2 VCO PA 6 PLL VS 12 ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] Figure 4-8. FSK Application Circuit BPXY S1 S2 VDD AVR (ATtiny) 1 VS VSS BPXY 20 BPXY OSC1 BPXY 7 ATA8404/ATA8405 Power up/down CLK 1 ENABLE EN f 10 8 f 24/ 32 ASK GND 9 2 OR C3 PFD FSK VS 3 8 CP C2 VS Ampl. OK XTO1 ANT2 XTO 4 Loop Antenna XTAL 7 LF C1 EN ANT1 5 L1 XTO2 VCO PA PLL C5 6 C4 VS 13 9136C–INDCO–10/09 Figure 4-9. ESD Protection Circuit VS ANT1 CLK ASK FSK XTO2 ANT2 XTO1 ENABLE GND 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Minimum Maximum Unit Supply voltage VS 5 V Power dissipation Ptot 100 mW Junction temperature Tj 150 °C Storage temperature Tstg –55 +85 °C Ambient temperature Tamb1 –55 +85 °C Ambient temperature in power-down mode for 15 minutes without damage with VS ≤ 3.2V VENABLE < 0.25V or ENABLE is open, VASK < 0.25V, VFSK < 0.25V Tamb2 175 °C (VS + 0.3)(1) V Input voltage Note: VmaxASK –0.3 1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V. 6. Thermal Resistance Parameters Junction ambient 14 Symbol Value Unit RthJA 170 K/W ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 7. Electrical Characteristics VS = 2.0V to 3.6V, Tamb = –40°C to +85°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60Ω Parameters Test Conditions Supply current, power-down mode VENABLE < 0.25V or ENABLE is open, VASK < 0.25V, VFSK < 0.25V Tamb = 25°C Tamb = –40° C to +85°C Supply current, idle mode VENABLE < 0.25V, VS ≤ 3.2V ASK,FSK can be Low or High IS_IDLE Supply current, power-up, PA off, FSK switch High Z VS ≤ 3.2V, VFSK > 1.7V, VASK < 0.25V ENABLE is open IS Supply current, power-up, PA on, FSK switch High Z VS ≤ 3.2V, CCLK ≤ 10 pF VFSK > 1.7V, VASK > 1.7V ENABLE is open ATA8404 ATA8405 IS_Transmit1 Supply current, power-up, PA on, FSK Low Z VS ≤ 3.2V, CCLK ≤ 10 pF VFSK< 0.25V, VASK > 1.7V ENABLE is open ATA8404 ATA8405 IS_Transmit2 Output power VS = 3.0V, Tamb = 25°C, f = 315 MHz for ATA8404, ZLoad, opt = (380 + j340)Ω f = 433.92 MHz for ATA8405, ZLoad, opt = (280 + j310)Ω POut 4 Output power for the full temperature and supply voltage range Tamb = –40°C to +85°C, VS = 2.0V to 3.2V POut 1 Spurious emission fCLK = fXT0/8 Load capacitance at pin CLK ≤ 20 pF f0 ±fCLK f0 ±fXT0 other spurious are lower Harmonics With 50Ω matching network according to Figure 4-6 on page 10 2nd 3rd Oscillator frequency XTO (= phase comparator frequency) fXTO = f0/24 ATA8404 fXTO = f0/32 ATA8405 fXTAL = resonant frequency of the XTAL, CM = 4.37 fF, load capacitance selected accordingly Tamb = –40°C to +85°C ΔfXTO Since pulling P is P = –IMXTO × CM × π × fXTO ΔfXTO can be calculated out of IMXTO with CM = 4.37 fF IMXTO Imaginary part of XTO1 Impedance in steady state oscillation Symbol Min. Typ. Max. Unit 100 350 nA nA 100 µA 3.6 4.6 mA 8.1 8.5 9.8 10.5 mA mA 8.4 8.8 10.2 11.0 mA mA 6 8 dBm 8.2 dBm 1 IS_Off Spour –42 –60 dBc –16 –15 dBc dBc –14.0 fXTAL +14.0 ppm j20 j110 j200 Ω 15 9136C–INDCO–10/09 7. Electrical Characteristics (Continued) VS = 2.0V to 3.6V, Tamb = –40°C to +85°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60Ω Parameters Test Conditions Symbol Min. Typ. Real part of XTO1 impedance in small signal oscillation This value is important for crystal oscillator start-up REXTO –650 –1100 Crystal oscillator start-up time Time between ENABLE of the IC with FSK = H and activation of the CLK output. The CLK is activated synchronously to the output frequency if the current through the XTAL has reached 35% to 80% of its maximum amplitude. Crystal parameters: CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF, RS ≤ 60Ω ΔTXTO 0.6 XTO drive current Current flowing through the crystal in steady state oscillation (peak-to-peak value) IDXTO 300 Locking time of the PLL Time between the activation of CLK and when the PLL is locked (transmitter ready for data transmission) ΔTPLL PLL loop bandwidth Max. Unit Ω 1.4 ms µApp 250 µs fLoop_PLL 250 LPLL –85 –76 dBc/Hz Lat1M Lat36M –90 –121 –84 –115 dBc/Hz dBc/Hz 317 448 MHz MHz kHz In loop phase noise PLL 25 kHz distance to carrier Phase noise VCO at 1 MHz at 36 MHz Frequency range of VCO ATA8404 ATA8405 fVCO Clock output frequency (CMOS microcontroller compatible) ATA8404 ATA8405 fCLK Clock output minimum High and Low time CLoad ≤ 20 pF, High = 0.8 × Vs, Low = 0.2 × VS, fCLK < 1.7 MHz TCLKLH Series resonance resistance of the resonator seen from pin XTO1 For proper detection of the XTO amplitude Rs_max 150 Ω CL_max 5 pF 20 kHz Capacitive load at Pin XTO1 310 432 f0/192 f0/256 125 FSK modulation frequency rate This corresponds to 20 kBaud in Manchester coding and 40 kBaud in NRZ coding fMOD_FSK 0 FSK switch OFF resistance High Z RSWIT_OFF 50 0.75 FSK switch OFF capacitance High Z capacitance CSWIT_OFF FSK switch ON resistance Low Z RSWIT_ON ASK modulation frequency rate Duty cycle of the modulation signal = 50%, this corresponds to 20 kBaud in Manchester coding and 40 kBaud in NRZ coding fMOD_ASK 16 MHz 0 ns kΩ 0.9 1.1 pF 130 175 Ω 20 kHz ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 7. Electrical Characteristics (Continued) VS = 2.0V to 3.6V, Tamb = –40°C to +85°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 9). CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60Ω Parameters Test Conditions ASK input Low level input voltage High level input voltage Input current high Symbol VIl VIh IIn FSK input Low level input voltage High level input voltage Input current high VIl VIh IIn ENABLE input Low level input voltage High level input voltage Input current high Input current Low VIl VIh IInh IInl Min. Max. Unit 1.7 0.25 VS 30 V V µA 1.7 0.25 VS 30 V V µA 0.25 VS +40 +40 V V µA µA 1.7 –40 –40 Typ. 17 9136C–INDCO–10/09 8. Ordering Information Extended Type Number Package Remarks ATA8404-6DQY TSSOP10 Pb-free ATA8405-6DQY TSSOP10 Pb-free 9. Package Information TSSOP10 Package: TSSOP 10 (acc. to JEDEC Standard MO-187) 3±0.1 3±0.1 0.25 3.8±0.3 0.5 nom. 0.15 0.85±0.1 1.1 max Dimensions in mm Not indicated tolerances ± 0.05 4.9±0.1 4 x 0.5 = 2 nom. 10 9 8 7 6 technical drawings according to DIN specifications Drawing-No.: 6.543-5095.01-4 1 2 3 4 5 18 Issue: 3; 16.09.05 ATA8404/ATA8405 [Preliminary] 9136C–INDCO–10/09 ATA8404/ATA8405 [Preliminary] 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9136C-INDCO-10/09 • Section 8 “Ordering Information” on page 18 changed 9136B-INDCO-06/09 • Figure 1-1 “System Block Diagram” on page 1 changed • Figure 4-7 “ASK Application Circuit” on page 12 changed • Figure 4-8 “FSK Application Circuit” on page 13 changed 19 9136C–INDCO–10/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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