Features
• High-density, High-performance, Electrically-erasable
•
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•
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•
Complex Programmable Logic Device
– 3.0V to 3.6V Operating Range
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
Advanced Power Management Features
– Automatic 5 µA Standby for “L” Version
– Pin-controlled 100 µA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 84-lead PLCC and 100-lead PQFP and TQFP and
160-lead PQFP Packages
Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
Security Fuse Feature
Highperformance
EE PLD
ATF1508ASV
ATF1508ASVL
Enhanced Features
•
•
•
•
•
•
•
•
•
•
•
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
VCC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
Rev. 1408E–09/00
1
100-lead TQFP
Top View
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
26
27
28
29
30
31
33
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O/PD1
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
84-lead PLCC
Top View
160-lead PQFP
Top View
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O
I/O
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O/TMS
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I/O
GND
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD1
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O/PD2
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
100-lead PQFP
Top View
2
ATF1508ASV(L)
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O/TCK
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
ATF1508ASV(L)
Block Diagram
6 to 12
3
Description
The ATF1508ASV(L) is a high-performance, high-density
complex programmable logic device (CPLD) that utilizes
Atmel’s proven electrically-erasable technology. With 128
logic macrocells and up to 100 inputs, it easily integrates
logic from several TTL, SSI, MSI, LSI and classic PLDs.
The ATF1508ASV(L)’s enhanced routing switch matrices
increase usable gate count and increase odds of successful pin-locked design modifications.
The ATF1508ASV(L) has up to 96 bi-directional I/O pins
and four dedicated input pins, depending on the type of
device package selected. Each dedicated pin can also
serve as a global control signal, register clock, register
reset or output enable. Each of these control signals can be
selected for use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback
that goes to the global bus. Each input and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term that
goes to a regional bus. Cascade logic between macrocells
in the ATF1508ASV(L) allows fast, efficient generation of
complex logic functions. The ATF1508ASV(L) contains
eight such logic chains, each capable of creating sum term
logic with a fan-in of up to 40 product terms.
The ATF1508ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly-complex logic functions operating at high-speed. The macrocell consists of five
sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select
and enable, and logic array inputs.
Unused macrocells are automatically disabled by the compiler to decrease power consumption. A security fuse,
when programmed, protects the contents of the
ATF1508ASV(L). Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the security fuse.
The ATF1508ASV(L) device is an in-system programmable
(ISP) device. It uses the industry-standard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP
allows the device to be programmed without removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.
4
ATF1508ASV(L)
Product Terms and Select Mux
Each ATF1508ASV(L) macrocell has five product terms.
Each product term receives as its inputs all signals from
both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the
five product terms as needed to the macrocell logic gates
and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum
macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1508ASV(L)’s logic structure is designed to efficiently support all types of logic. Within a single macrocell,
all the product terms can be routed to the OR gate, creating
a 5-input AND/OR sum term. With the addition of the
CASIN from neighboring macrocells, this can be expanded
to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic functions. One input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.
Flip-flop
The ATF1508ASV(L)’s flip-flop has very flexible data and
control functions. The data input can come from either the
XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and
SR operation, the flip-flop can also be configured as a flowthrough latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The clock itself can either be the Global CLK Signal (GCK)
or an individual product term. The flip-flop changes state on
the clock's rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be
selected as a clock enable. When the clock enable function
is active and the enable signal (product term) is low, all
clock edges are ignored. The flip-flop’s asynchronous reset
signal (AR) can be either the Global Clear (GCLEAR), a
product term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous preset
(AP) can be a product term or always off.
ATF1508ASV(L)
Figure 1. ATF1508ASV(L) Macrocell
Output Select and Enable
The ATF1508ASV(L) macrocell output can be selected as
registered or combinatorial. The buried feedback signal can
be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output
enable signals. Any buffer can be permanently enabled for
simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configuration. all the macrocell resources are still available,
including the buried feedback, expander and CASCADE
logic. The output enable for each macrocell can be
selected as one of the global OUTPUT enable signals. The
device has six global OE signals.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 128 macrocells.
The switch matrix in each logic block receives as its inputs
all signals from the global bus. Under software control, up
to 40 of these signals can be selected as inputs to the logic
block.
Foldback Bus
Each macrocell also generates a foldback product term.
This signal goes to the regional bus and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each
region allow generation of high fan-in sum terms (up to 21
product terms) with little additional delay.
Open-collector Output Option
This option enables the device output to provide control
signals such as an interrupt that can be asserted by any of
the several devices.
5
Programmable Pin-keeper Option for
Inputs and I/Os
I/O Diagram
The ATF1508ASV(L) offers the option of programming all
input and I/O pins so that “pin-keeper” circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or lowlevel. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.
Input Diagram
Speed/Power Management
The ATF1508ASV(L) has several built-in speed and power
management features. The ATF1508ASV(L) contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This
not only reduces power consumption during inactive periods, but also provides proportional power-savings for most
applications running at system speeds below 5 MHz.
To further reduce power, each ATF1508ASV(L) macrocell
has a reduced-power bit feature. This feature allows individual macrocells to be configured for maximum powersavings. This feature may be selected as a design option.
6
ATF1508ASV(L)
All ATF1508 also have an optional power-down mode. In
this mode, current drops to below 10 mA. When the powerdown option is selected, either PD1 or PD2 pins (or both)
can be used to power down the part. The power-down
option is selected in the design source file. When enabled,
the device goes into power-down when either PD1 or PD2
is high. In the power-down mode, all internal logic signals
are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought
low. When the power-down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power
bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder,
tRPA, must be added to the AC parameters, which include
the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
ATF1508ASV(L)
Design Software Support
ATF1508ASV(L) designs are supported by several thirdparty tools. Automated fitters allow logic synthesis using a
variety of high-level description languages and formats.
Power-up Reset
The ATF1508ASV is designed with a power-up reset, a
feature critical for state machine initialization. At a point
delayed slightly from VCC crossing VRST, all registers will be
initialized, and the state of each output will depend on the
polarity of its buffer. However, due to the asynchronous
nature of reset and uncertainty of how VCC actually rises in
the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin
high, and,
3. The clock must remain stable during TD.
The ATF1508ASV has two options for the hysteresis about
the reset level, VRST, Small and Large. To ensure a robust
operating environment in applications where the device is
operated near 3.0V, Atmel recommends that during the fitting process users configure the device with the Power-up
Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on
the command line after “filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced
by several hundred microamps as well.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF1508ASV(L) fuse patterns. Once programmed,
fuse verify is inhibited. However, User Signature and
device ID remains accessible.
Programming
ATF1508ASV(L) devices are in-system programmable
(ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for
programming and facilitates rapid design iterations and
field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1508ASV(L) via the PC. ISP is performed by using either a download cable, a comparable
board tester or a simple microprocessor interface.
To allow ISP programming support by the Automated Test
Equipment (ATE) vendors, Serial Vector Format (SVF) files
can be created by the Atmel ISP software. Conversion to
other ATE tester format beside SVF is also possible
ATF1508ASV(L) devices can also be programmed using
standard third-party programmers. With third-party programmer, the JTAG ISP port can be disabled thereby
allowing four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD
applications for details.
ISP Programming Protection
The ATF1508ASV(L) has a special feature that locks the
device and prevents the inputs and I/O from driving if the
programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper option preserves the former
state during device programming.
All ATF1508ASV(L) devices are initially shipped in the
erased state thereby making them ready to use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs” application
note.
7
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Ambient)
0°C - 70°C
-40°C - 85°C
VCC (3.3V) Power Supply
3.0V - 3.6V
3.0V - 3.6V
DC Characteristics
Symbol
Parameter
Condition
IIL
Input or I/O Low
Leakage Current
VIN = VCC
IIH
Input or I/O High
Leakage Current
IOZ
Tri-State Output
Off-State Current
Min
VO = VCC or GND
Typ
Max
Units
-2
-10
µA
2
10
µA
40
µA
-40
Com.
115
mA
Ind.
135
mA
Com.
5
µA
Ind.
5
µA
Std Mode
ICC1
Power Supply
Current, Standby
VCC = Max
VIN = 0, VCC
“L” Mode
ICC2
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode
ICC3(2)
Reduced-power Mode
Supply Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
1.7
VCCIO + 0.3
V
Output Low Voltage (TTL)
VOH
Notes:
5
mA
Com.
60
mA
Ind.
80
mA
VIN = VIH or VIL
VCC = Min, IOL = 8 mA
Com.
0.45
V
Ind.
0.45
V
VIN = VIH or VIL
VCC = Min, IOL = 0.1 mA
Com.
0.2
V
Ind.
0.2
V
VOL
Output Low Voltage (CMOS)
0.1
Output High Voltage
– 3.3V (TTL)
VIN = VIH or VIL
VCC = Min, IOH = -2.0 mA
Output High Voltage
– 3.3V (CMOS)
VIN = VIH or VIL
VCCIO = Min, IOH = -0.1 mA
2.4
V
VCCIO - 0.2
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
Pin Capacitance
Typ
Max
Units
CIN
8
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
pF
VOUT = 0V; f = 1.0 MHz
Note:
8
Conditions
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin
during programming) has a maximum capacitance of 12 pF.
ATF1508ASV(L)
ATF1508ASV(L)
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
1.
Timing Model
U
9
AC Characteristics(1)
-15
Symbol
Parameter
tPD1
-20
Min
Max
Input or Feedback to Non-registered Output
3
tPD2
I/O Input or Feedback to Non-registered Feedback
3
tSU
Global Clock Setup Time
11
13.5
ns
tH
Global Clock Hold Time
0
0
ns
tFSU
Global Clock Setup Time of Fast Input
3
3
ns
tFH
Global Clock Hold Time of Fast Input
1.0
2.0
MHz
tCOP
Global Clock to Output Delay
tCH
Global Clock High Time
5
6
ns
tCL
Global Clock Low Time
5
6
ns
tASU
Array Clock Setup Time
5
7
ns
tAH
Array Clock Hold Time
4
4
ns
tACOP
Array Clock Output Delay
tACH
Array Clock High Time
6
8
ns
tACL
Array Clock Low Time
6
8
ns
tCNT
Minimum Clock Global Period
fCNT
Maximum Internal Global Clock Frequency
tACNT
Minimum Array Clock Period
fACNT
Maximum Internal Array Clock Frequency
76.9
58.8
MHz
fMAX
Maximum Clock Frequency
100
83.3
MHz
tIN
Input Pad and Buffer Delay
2
2.5
ns
tIO
I/O Input Pad and Buffer Delay
2
2.5
ns
tFIN
Fast Input Delay
2
2
ns
tSEXP
Foldback Term Delay
8
10
ns
tPEXP
Cascade Logic Delay
1
1
ns
tLAD
Logic Array Delay
6
8
ns
tLAC
Logic Control Delay
3.5
4.5
ns
tIOE
Internal Output Enable Delay
3
3
ns
tOD1
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF)
3
4
ns
tOD2
Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
3
4
ns
tOD3
Output Buffer and Pad Delay
(Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF)
5
6
ns
tZX1
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF)
7
9
10
ATF1508ASV(L)
Min
Max
Units
15
20
ns
12
16
ns
9
12
15
18.5
13
76.9
17
66
13
ns
ns
ns
MHz
17
ns
ATF1508ASV(L)
AC Characteristics(1) (Continued)
-15
Symbol
Parameter
Max
Units
tZX2
Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF)
7
9
ns
tZX3
Output Buffer Enable Delay
(Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF)
10
11
ns
tXZ
Output Buffer Disable Delay
(CL = 5 pF)
6
7
ns
tSU
Register Setup Time
5
6
ns
tH
Register Hold Time
4
5
ns
tFSU
Register Setup Time of Fast Input
2
2
ns
tFH
Register Hold Time of Fast Input
2
2
ns
tRD
Register Delay
2
2.5
ns
tCOMB
Combinatorial Delay
2
3
ns
tIC
Array Clock Delay
6
7
ns
tEN
Register Enable Time
6
7
ns
tGLOB
Global Control Delay
2
3
ns
tPRE
Register Preset Time
4
5
ns
tCLR
Register Clear Time
4
5
ns
tUIM
Switch Matrix Delay
2
2.5
ns
10
13
ns
tRPA
Notes:
Min
-20
(2)
Reduced-Power Adder
Max
Min
1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode.
Input Test Waveforms and
Measurement Levels
Output AC Test Loads
3.0V
703
8060
tR, tF = 1.5 ns typical
11
Power-down Mode
The ATF1508ASV(L) includes two pins for optional pincontrolled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the
PD1 and PD2 pin is high, the device supply current is
reduced to less than 5 mA. During power-down, all output
data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset
will remain at high-Z. During power-down, all input signals
except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to
indeterminate levels, further reducing system power. The
power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD
pin logic array input. However, buried logic resources in
this macrocell may still be used.
Power Down AC Characteristics(1)(2)
-15
Symbol
Parameter
tIVDH
Valid I, I/O before PD High
(2)
Min
-20
Max
Min
Max
Units
15
20
ns
Valid OE
before PD High
15
20
ns
tCVDH
Valid Clock
(2)
15
20
ns
tDHIX
I, I/O Don’t Care after PD High
25
30
ns
tDHGX
OE(2) Don’t Care after PD High
25
30
ns
25
30
ns
tGVDH
(2)
before PD High
tDHCX
Clock
tDLIV
PD Low to Valid I, I/O
1
1
µs
tDLGV
PD Low to Valid OE (Pin or Term)
1
1
µs
tDLCV
PD Low to Valid Clock (Pin or Term)
1
1
µs
tDLOV
PD Low to Valid Output
1
1
µs
Notes:
Don’t Care after PD High
1. For slow slew outputs, add tSSO.
2. Pin or product term.
12
ATF1508ASV(L)
ATF1508ASV(L)
JTAG-BST Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled
by the Test Access Port (TAP) controller in the
ATF1508ASV(L). The boundary-scan technique involves
the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals
at component boundaries can be controlled and observed
using scan testing principles. Each input pin and I/O pin
has its own Boundary-scan Cell (BSC) in order to support
boundary-scan testing. The ATF1508ASV(L) does not currently include a Test Reset (TRST) input pin because the
TAP controller is automatically reset at power-up. The six
JTAG-BST modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the
ATF1508ASV(L) is implemented using the Boundary-scan
Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party tool that
supports the BSDL format can be used to perform BST on
the ATF1508ASV(L).
The ATF1508ASV(L) also has the option of using four
JTAG-standard I/O pins for in-system programming (ISP).
The ATF1508ASV(L) is programmable through the four
JTAG pins using programming-compatible with the IEEE
JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG
ISP interface. The JTAG feature is a programmable option.
If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins.
BSCs, one for input or I/O pin, and one for the macrocells.
The BSCs in the device are chained together through the
(BST) capture registers. Input to the capture register chain
is fed in from the TDI pin while the output is directed to the
TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device
and to load data into the update registers. Control signals
are generated internally by the JTAG TAP controller. The
BSC configuration for the input and I/O pins and macrocells
are shown below.
BSC Configuration Pins and
Macrocells (Except JTAG TAP Pins)
Note:
JTAG Boundary-scan Cell (BSC)
Testing
The ATF1508ASV(L) contains up to 96 I/O pins and four
input pins, depending on the device type and package type
selected. Each input pin and I/O pin has its own boundaryscan cell (BSC) in order to support boundary-scan testing
as described in detail by IEEE Standard 1149.1. A typical
BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of
The ATF1508ASV(L) has pull-up option on TMS and TDI
pins. This feature is selected as a design option.
Boundary-scan Definition Language
(BSDL) Models for the ATF1508
These are now available in all package types via the Atmel
web site. These models can be used for Boundary-scan
Test Operation in the ATF1508ASV(L) and have been
scheduled to conform to the IEEE 1149.1 standard.
13
BSC Configuration for Macrocell
Pin BSC
TDO
0
1
Pin
DQ
Capture
DR
Clock
TDI
Shift
TDO
OEJ
0
0
1
D Q
D Q
1
OUTJ
0
0
Pin
1
D Q
D Q
Capture
DR
Update
DR
1
Mode
TDI
Shift
Clock
Macrocell BSC
14
ATF1508ASV(L)
ATF1508ASV(L)
ATF1508ASV(L) Dedicated Pinouts
Dedicated Pin
84-lead J-lead
100-lead PQFP
100-lead TQFP
160-lead PQFP
INPUT/OE2/GCLK2
2
92
90
142
INPUT/GCLR
1
91
89
141
INPUT/OE1
84
90
88
140
INPUT/GCLK1
83
89
87
139
I/O/GCLK3
81
87
85
137
12,45
3,43
1,41
63,159
I/O/TDI(JTAG)
14
6
4
9
I/O/TMS(JTAG)
23
17
15
22
I/O/TCK(JTAG)
62
64
62
99
I/O/TDO(JTAG)
71
75
73
112
GND
7,19,32,42,
47,59,72,82
13,28,40,45,
61,76,88,97
11,26,38,43,
59,74,86,95
17,42,60,66,95,
113,138,148
VCC
3,13,26,38,
43,53,66,78
5,20,36,41,
53,68,84,93
3,18,34,39,
51,66,82,91
8,26,55,61,79,104,133,143
I/O/PD (1, 2)
-
-
-
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
# of SIGNAL PINS
68
84
84
100
# USER I/O PINS
64
80
80
96
N/C
OE (1, 2)
GCLR
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
VCC
Global OE pins
Global Clear pin
Global Clock pins
Power-down pins
JTAG pins used for boundary-scan testing or in-system programming
Ground pins
VCC pins for the device
15
ATF1508ASV(L) I/O Pinouts
MC
PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
1
A
-
4
2
160
33
C
-
27
25
41
2
A
-
-
-
-
34
C
-
-
-
-
3
A/
PD1
12
3
1
159
35
C
31
26
24
33
4
A
-
-
-
158
36
C
-
-
-
32
5
A
11
2
100
153
37
C
30
25
23
31
6
A
10
1
99
152
38
C
29
24
22
30
7
A
-
-
-
-
39
C
-
-
-
-
8
A
9
100
98
151
40
C
28
23
21
29
9
A
-
99
97
150
41
C
-
22
20
28
10
A
-
-
-
-
42
C
-
-
-
-
11
A
8
98
96
149
43
C
27
21
19
27
12
A
-
-
-
147
44
C
-
-
-
25
13
A
6
96
94
146
45
C
25
19
17
24
14
A
5
95
93
145
46
C
24
18
16
23
15
A
-
-
-
-
47
C
-
-
-
-
16
A
4
94
92
144
48
C/
TMS
23
17
15
22
17
B
22
16
14
21
49
D
41
39
37
59
18
B
-
-
-
-
50
D
-
-
-
-
19
B
21
15
13
20
51
D
40
38
36
58
20
B
-
-
-
19
52
D
-
-
-
57
21
B
20
14
12
18
53
D
39
37
35
56
22
B
-
12
10
16
54
D
-
35
33
54
23
B
-
-
-
-
55
D
-
-
-
-
24
B
18
11
9
15
56
D
37
34
32
53
25
B
17
10
8
14
57
D
36
33
31
52
26
B
-
-
-
-
58
D
-
-
-
-
27
B
16
9
7
13
59
D
35
32
30
51
28
B
-
-
-
12
60
D
-
-
-
50
29
B
15
8
6
11
61
D
34
31
29
49
30
B
-
7
5
10
62
D
-
30
28
48
31
B
-
-
-
-
63
D
-
-
-
-
32
B/
TDI
14
6
4
9
64
D
33
29
27
43
65
E
44
42
40
62
97
G
63
65
63
100
66
E
-
-
-
-
98
G
-
-
-
-
16
ATF1508ASV(L)
ATF1508ASV(L)
ATF1508ASV(L) I/O Pinouts (Continued)
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
MC
PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
E/
PD2
45
43
41
63
99
G
64
66
64
101
68
E
-
-
-
64
100
G
-
-
-
102
69
E
46
44
42
65
101
G
65
67
65
103
70
E
-
46
44
67
102
G
-
69
67
105
71
E
-
-
-
-
103
G
-
-
-
-
72
E
48
47
45
68
104
G
67
70
68
106
73
E
49
48
46
69
105
G
68
71
69
107
74
E
-
-
-
-
106
G
-
-
-
-
75
E
50
49
47
70
107
G
69
72
70
108
76
E
-
-
-
71
108
G
-
-
-
109
77
E
51
50
48
72
109
G
70
73
71
110
78
E
-
51
49
73
110
G
-
74
72
111
79
E
-
-
-
-
111
G
-
-
-
-
80
E
52
52
50
78
112
G/
TDO
71
75
73
112
81
F
-
54
52
80
113
H
-
77
75
121
82
F
-
-
-
-
114
H
-
-
-
-
83
F
54
55
53
88
115
H
73
78
76
122
84
F
-
-
-
89
116
H
-
-
-
123
85
F
55
56
54
90
117
H
74
79
77
128
86
F
56
57
55
91
118
H
75
80
78
129
87
F
-
-
-
-
119
H
-
-
-
-
88
F
57
58
56
92
120
H
76
81
79
130
89
F
-
59
57
93
121
H
-
82
80
131
90
F
-
-
-
-
122
H
-
-
-
-
91
F
58
60
58
94
123
H
77
83
81
132
92
F
-
-
-
96
124
H
-
-
-
134
93
F
60
62
60
97
125
H
79
85
83
135
94
F
61
63
61
98
126
H
80
86
84
136
95
F
-
-
-
-
127
H
-
-
-
-
96
F/
TCK
62
64
62
99
128
H/
GCLK3
81
87
85
137
MC
PLB
67
17
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(T A = 25°C, F = 0)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(T A = 25°C, F = 0)
200
800
STANDARD POWER
STANDARD & REDUCED POWER MODE
ICC (uA)
ICC (mA)
700
100
600
REDUCED POWER
500
0
2.50
2.75
3.00
3.25
3.50
3.75
400
2.50
4.00
SUPPLY VOLTAGE (V)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
2.75
3.00
3.25
3.50
SUPPLY VOLTAGE (V)
3.75
4.00
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
(TA = 25°C)
250.0
125.0
STANDARD POWER
200.0
100.0
ICC (mA)
ICC (mA)
STANDARD POWER
150.0
100.0
75.0
REDUCED POWER
50.0
REDUCED POWER MODE
25.0
50.0
0.0
0.0
0.00
0.00
20.00
40.00
60.00
80.00
100.00
FREQUENCY (MHz)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW POWER ("L") MODE
(T A = 25°C, F = 0)
10
9
8
ICC (uA)
7
6
5
4
3
2
1
0
2.50
18
2.75
3.00
3.25
3.50
SUPPLY VOLTAGE (V)
3.75
ATF1508ASV(L)
4.00
5.00
10.00
FREQUENCY (MHz)
15.00
20.00
ATF1508ASV(L)
OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (V OH = 2.4V, T A = 25°C)
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE (VCC = 3.3V,T A = 25°C)
0
10
0
-4
-10
-6
-20
IOH (mA)
IOH (mA)
-2
-8
-10
-30
-40
-50
-12
-60
-14
-70
-16
2.75
3.00
3.25
3.50
3.75
0.0
4.00
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
OUTPUT VOLTAGE (V)
SUPPLY VOLT AGE (V)
OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V, T A = 25°C)
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 3.3V, T A = 25°C)
100
40
80
IOL (mA)
IOL (mA)
35
30
25
60
40
20
0
20
2.75
3.00
3.25
3.50
3.75
0
4.00
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT CURRENT vs. INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
15
INPUT CURRENT (uA)
INPUT CURRENT (mA)
0
-20
-40
-60
-80
-100
10
5
0
-5
-10
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
INPUT VOLTAGE (V)
-0.3
-0.2
-0.1
0
0
0.5
1
1.5
2
2.5
3
3.5
INPUT VOLTAGE (V)
19
ATF1508ASV(L) Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
15
8
100
8
20
Ordering Code
Package
Operation Range
ATF1508ASV-15 JC84
ATF1508ASV-15 QC100
ATF1508ASV-15 AC100
ATF1508ASV-15 QC160
84J
100Q
100A
160Q
Commercial
(0°C to 70°C)
100
ATF1508ASV-15 JI84
ATF1508ASV-15 QI100
ATF1508ASV-15 AI100
ATF1508ASV-15 QI160
84J
100Q
100A
160Q
Industrial
(-40°C to +85°C)
12
83.3
ATF1508ASVL-20 JC84
ATF1508ASVL-20 QC100
ATF1508ASVL-20 AC100
ATF1508ASVL-20 QC160
84J
100Q
100A
160Q
Commercial
(0°C to 70°C)
12
83.3
ATF1508ASVL-20 JI84
ATF1508ASVL-20 QI100
ATF1508ASVL-20 AI100
ATF1508ASVL-20 QI160
84J
100Q
100A
160Q
Industrial
(-40°C to +85°C)
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are
the same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use
commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
84J
84-lead, Plastic J-leaded Chip Carrier (PLCC)
100Q
100-lead, Plastic Quad Pin Flat Package (PQFP)
100A
100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160Q
160-lead, Plastic Quad Pin Flat Package (PQFP)
20
ATF1508ASV(L)
ATF1508ASV(L)
Packaging Information
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AF
100Q, 100-lead, Plastic Gull Wing Quad Flat
Package (PQFP)
Dimensions in Millimeters and (Inches)
17.44 (0.687)
16.95 (0.667)
PIN 1 ID
20.12 (.792)
19.87 (.782)
0.65 (0.026) BSC
0.41 (0.016)
23.45 (0.923)
0.22 (0.009)
22.95 (0.904)
0.25 (0.010)
0.10 (0.004)
7
0
14.12 (0.556)
13.87 (0.546)
3.40 (.134) MAX
1.03 (0.041)
0.73 (0.028) 0.10 (0.004) MIN
*Controlling dimension: Millimeters
100A, 100-lead, Very Thin (1.0mm) Plastic Gull
Wing Quad Flat Package (TQFP)
Dimensions in Millimeters and (Inches)*
16.25(0.640)
15.75(0.620)
160Q, 160-lead, Plastic Gull Wing Quad Flat
Package (PQFP)
Dimensions in Millimeters and (Inches)
1.238(31.45)
SQ
1.218(30.95)
PIN 1 ID
PIN 1 ID
0.27(0.011)
0.17(0.007)
.016(0.40)
.008(0.20)
.0256(0.65) BSC
0.56(0.022)
0.44(0.018)
0.20(0.008)
0.10(0.004)
1.106(28.10)
1.05(0.041)
0.95(0.037)
14.10(0.555)
13.90(0.547)
.009(0.23)
0-7
7
0
1.098(27.90)
SQ
.157(3.97)
.127(3.22)
.004(0.10)
0.75(0.030)
0.45(0.018)
*Controlling dimension: Millimeters
0.15(0.006)
0.05(0.002)
.037(0.95)
.025(0.65)
.020(0.50)
.002(0.05)
*Controlling dimension: Millimeters
21
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1408E–09/00/xM