ATMEL ATF1502ASV

Features
• High-density, High-performance, Electrically-erasable Complex Programmable
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Logic Device
– 3.0 to 3.6V Operating Range
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
– Pin-controlled 0.75 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead PLCC and TQFP
Advanced EEPROM Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
Highperformance
EEPROM CPLD
ATF1502ASV
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D Latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
Fast Registered Input from Product Term
Programmable “Pin-keeper” Option
VCC Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
– Individual Macrocell Power Option
Rev. 1615H–PLD–2/04
1
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
44-lead TQFP
Top View
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCC
I/O
I/O
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
I/O
I/O
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
6
5
4
3
2
1
44
43
42
41
40
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
GND
GCLK3/I/O
I/O
44-lead PLCC
Top View
Description
The ATF1502ASV is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32
logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI,
MSI, LSI and classic PLDs. The ATF1502ASV’s enhanced routing switch matrices
increase usable gate count and the odds of successful pin-locked design modifications.
The ATF1502ASV has up to 32 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
2
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
Block Diagram
B
32
Each of the 32 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1502ASV allows fast, efficient generation of complex logic functions. The ATF1502ASV contains four such logic chains, each capable of creating sum
term logic with a fan-in of up to 40 product terms.
The ATF1502ASV macrocell, shown in Figure 1, is flexible enough to support highly
complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1502ASV. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature
is accessible regardless of the state of the security fuse.
The ATF1502ASV device is an in-system programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s
3
1615H–PLD–2/04
Boundary-scan Description Language (BSDL). ISP allows the device to be programmed
without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
Figure 1. ATF1502ASV Macrocell
Product Terms and
Select Mux
Each ATF1502ASV macrocell has five product terms. Each product term receives as its
inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
OR/XOR/
CASCADE Logic
The ATF1502ASV’s logic structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high or low level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.
4
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
Flip-flop
The ATF1502ASV’s flip-flop has very flexible data and control functions. The data input
can come from either the XOR gate, from a separate product term or directly from the
I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented
by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be
configured as a flow-through latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.
The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signal (product term) is
low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic
OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product
term or always off.
Extra Feedback
The ATF1502ASV macrocell output can be selected as registered or combinatorial.The
extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is
automatically implemented by the fitter software.) Feedback of a buried combinatorial
output allows the creation of a second latch within a macrocell.
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be
individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is
automatically done by the fitter software when the I/O is configured as an input, all macrocell resources are still available, including the buried feedback, expander and cascade
logic.
Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 32 macrocells. The switch matrix in each logic block receives as its inputs all
signals from the global bus. Under software control, up to 40 of these signals can be
selected as inputs to the logic block.
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to four macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The four foldback terms in each region allow generation of
high fan-in sum terms (up to nine product terms) with little additional delay.
Programmable Pinkeeper Option for
Inputs and I/Os
The ATF1502ASV offers the option of programming all input and I/O pins so that pinkeeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
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1615H–PLD–2/04
Input Diagram
VCC
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
I/O Diagram
VCC
OE
I/O
DATA
VCC
100K
PROGRAMMABLE
OPTION
Speed/Power
Management
The ATF1502ASV has several built-in speed and power management features.
To further reduce power, each ATF1502ASV macrocell has a reduced-power bit feature.
To reduce power consumption this feature may be actived (by changing the default
value of OFF to ON) for any or all macrocells.
The ATF1502ASV also has an optional power-down mode. In this mode, current drops
to below 15 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
6
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
All power-down AC characteristic parameters are computed from external input or I/O
pins, with reduced-power bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC
parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.
The ATF1502ASV macrocell also has an option whereby the power can be reduced on
a per-macrocell basis. By enabling this power-down option, macrocells that are not used
in an application can be turned down, thereby reducing the overall power consumption
of the device.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
Design Software
Support
ATF1502ASV designs are supported by several third-party tools. Automated fitters allow
logic synthesis using a variety of high-level description languages and formats.
Power-up Reset
The ATF1502ASV is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the
system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before
driving the clock pin high, and,
3. The clock must remain stable during TD.
The ATF1502ASV has two options for the hysteresis about the reset level, VRST, Small
and Large. To ensure a robust operating environment in applications where the device
is operated near 3.0V, Atmel recommends that during the fitting process users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned
on again.
When the Large hysteresis option is active, ICC is reduced by several hundred microamps as well.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF1502ASV fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.
Programming
ATF1502ASV devices are in-system programmable (ISP) devices utilizing the 4-pin
JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1502ASV
via the PC. ISP is performed by using either a download cable, a comparable board
tester or a simple microprocessor interface.
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1615H–PLD–2/04
When using the ISP hardware or software to program the ATF1502ASV devices, four
I/O pins must be reserved for the JTAG interface. However, the logic features that the
macrocells have associated with these I/O pins are still available to the design for
burned logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel-provided software utilities.
ATF1502ASV devices can also be programmed using standard third-party programmers. With a third-party programmer, the JTAG ISP port can be disabled, thereby
allowing four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming
Protection
The ATF1502ASV has a special feature that locks the device and prevents the inputs
and I/O from driving if the programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condition. In addition, the pin-keeper
option preserves the previous state of the input and I/O PMS during programming.
All ATF1502ASV devices are initially shipped in the erased state, thereby making them
ready to use for ISP.
Note:
JTAG-BST/ISP
Overview
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller
in the ATF1502ASV. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundaries can be controlled and observed using scan testing
methods. Each input pin and I/O pin has its own boundary-scan cell (BSC) to support
boundary-scan testing. The ATF1502ASV does not include a Test Reset (TRST) input
pin because the TAP controller is automatically reset at power-up. The five JTAG modes
supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The
ATF1502ASV’s ISP can be fully described using JTAG’s BSDL as described in IEEE
Standard 1149.1b. This allows ATF1502ASV programming to be described and implemented using any one of the third-party development tools supporting this standard.
The ATF1502ASV has the option of using four JTAG-standard I/O pins for boundaryscan testing (BST) and in-system programming (ISP) purposes. The ATF1502ASV is
programmable through the four JTAG pins using the IEEE standard JTAG programming
protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals
from the ISP interface for in-system programming. The JTAG feature is a programmable
option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins.
JTAG Boundary-scan
Cell (BSC) Testing
8
The ATF1502ASV contains up to 32 I/O pins and four input pins, depending on the
device type and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O
pin, and one for the macrocells. The BSCs in the device are chained together through
the capture registers. Input to the capture register chain is fed in from the TDI pin while
the output is directed to the TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device and to load data into the update
registers. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells is shown below.
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
BSC Configuration
for Input and I/O Pins
(Except JTAG TAP
Pins)
Dedicated
Input
To Internal
Logic
TDO
Capture
Registers
CLOCK
SHIFT
TDI
(From Next Register)
Note:
BSC Configuration
for Macrocells
The ATF1502ASV has a pull-up option on TMS and TDI pins. This feature is selected as
a design option.
TDO
0
Q D
1
TDI
CLOCK
TDO
OEJ
0
0
1
D Q
D Q
1
OUTJ
0
0
Pin
1
D Q
D Q
Capture
DR
Update
DR
1
Mode
TDI
Shift
Clock
BSC for I/O Pins and Macrocells
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1615H–PLD–2/04
Power-down Mode
The ATF1502ASV includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the
device supply current is reduced to less than 3 mA. During power-down, all output data
and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will
remain at high-Z. During power-down, all input signals except the power-down pin are
blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is enabled
in the logic design file. Designs using the power-down pin may not use the PD pin logic
array input. However, all other PD pin macrocell resources may still be used, including
the buried feedback and foldback product term array inputs.
Power-down AC Characteristics(1)(1)
-15
Symbol
Parameter
tIVDH
Valid I, I/O before PD High
15
20
ns
tGVDH
Valid OE(1) before PD High
15
20
ns
tCVDH
Valid Clock(1) before PD High
15
20
ns
tDHIX
I, I/O Don’t Care after PD High
(1)
Min
-20
Max
Min
Max
Units
25
30
ns
25
30
ns
tDHGX
OE
tDHCX
Clock(1) Don’t Care after PD High
25
30
ns
tDLIV
PD Low to Valid I, I/O
1
1
µs
1
1
µs
tDLGV
Don’t Care after PD High
(1)
PD Low to Valid OE
(1)
tDLCV
PD Low to Valid Clock
1
1
µs
tDLOV
Notes:
PD Low to Valid Output
1. For slow slew outputs, add tSSO.
1. Pin or product term.
1
1
µs
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
10
Note:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Ambient)
0°C - 70°C
-40°C - 85°C
VCC (3.3V) Power Supply
3.0V – 3.6V
3.0V – 3.6V
DC Characteristics
Symbol
Parameter
Condition
IIL
Input or I/O Low
Leakage Current
VIN = VCC
IIH
Input or I/O High
Leakage Current
IOZ
Tri-state Output
Off-state Current
VO = VCC or GND
ICC1
Power Supply Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode
ICC2
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode
ICC3(2)
Reduced-power Mode
Supply Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VCCINT + 0.3
V
V
Output Low Voltage (TTL)
Min
Notes:
Units
-2
-10
µA
2
10
-40
40
µA
Com.
40
mA
Ind.
45
mA
0.75
5.0
mA
Com.
25
mA
Ind.
30
mA
Com.
0.45
Ind.
0.45
VIN = VIH or VIL
VCC = MIN, IOL = 0.1 mA
Com.
0.2
V
Ind.
0.2
V
Output High Voltage (TTL)
VIN = VIH or VIL
VCC = MIN, IOH = 2.0 mA
Output High Voltage (CMOS)
VIN = VIH or VIL
VCCIO = MIN, IOH = -0.1 mA
VOH
Max
VIN = VIH or VIL
VCC = MIN, IOL = 8 mA
VOL
Output Low Voltage (CMOS)
Typ
2.4
V
VCCIO - 0.2
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned on.
11
1615H–PLD–2/04
Pin Capacitance(1)
Typ
Max
Units
Conditions
CIN
8
10
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage
pin during programming) has a maximum capacitance of 12 pF.
Timing Models
Internal Output
Enable Delay
tIOE
Global Control
Delay
tGLOB
Input
Delay
tIN
Switch
Matrix
tUIM
Logic Array
Delay
tLAD
Cascade Logic
Delay
tPEXP
Register Control
Delay
tLAC
tIC
tEN
Fast Input
Delay
tFIN
Foldback Term
Delay
tSEXP
Register
Delay
tSU
tH
tPRE
tCLR
tRD
tCOMB
tFSU
tFH
Output
Delay
tOD1
tOD2
tOD3
tXZ
tZX1
tZX2
tZX3
I/O
Delay
tIO
Input Test Waveforms and Measurement Levels
tR, tF = 1.5 ns typical
Output AC Test Loads
3.0V
R1 = 703Ω
OUTPUT
PIN
R2 = 8060Ω
12
CL = 35 pF
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
AC Characteristics (1)
-15
Symbol
Parameter
tPD1
-20
Min
Max
Min
Max
Units
Input or Feedback to Non-registered Output
3
15
20
ns
tPD2
I/O Input or Feedback to Non-registered Feedback
3
12
16
ns
tSU
Global Clock Setup Time
11
16
ns
tH
Global Clock Hold Time
0
0
ns
tFSU
Global Clock Setup Time of Fast Input
3
3
ns
tFH
Global Clock Hold Time of Fast Input
1
1.5
MHz
tCOP
Global Clock to Output Delay
tCH
Global Clock High Time
5
6
ns
tCL
Global Clock Low Time
5
6
ns
tASU
Array Clock Setup Time
4
4
ns
tAH
Array Clock Hold Time
4
5
ns
tACOP
Array Clock Output Delay
tACH
Array Clock High Time
6
8
ns
tACL
Array Clock Low Time
6
8
ns
tCNT
Minimum Clock Global Period
fCNT
Maximum Internal Global Clock Frequency
tACNT
Minimum Array Clock Period
fACNT
Maximum Internal Array Clock Frequency
76.9
66
MHz
fMAX
Maximum Clock Frequency
100
83.3
MHz
tIN
Input Pad and Buffer Delay
2
2
ns
tIO
I/O Input Pad and Buffer Delay
2
2
ns
tFIN
Fast Input Delay
2
2
ns
tSEXP
Foldback Term Delay
8
10
ns
tPEXP
Cascade Logic Delay
1
1
ns
tLAD
Logic Array Delay
6
7
ns
tLAC
Logic Control Delay
6
7
ns
tIOE
Internal Output Enable Delay
3
3
ns
tOD1
Output Buffer and Pad Delay
(Slow slew rate = OFF;
VCC = 3.3V; CL = 35 pF)
5
5
ns
tZX1
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 5.0V; CL = 35 pF)
7
9
ns
tZX2
Output Buffer Enable Delay
(Slow slew rate = OFF;
VCCIO = 3.3V; CL = 35 pF)
7
9
ns
8
10
15
20
13
76.9
16
66
13
ns
ns
ns
MHz
16
ns
13
1615H–PLD–2/04
AC Characteristics (Continued)(1)
-15
Symbol
Parameter
tZX3
Output Buffer Enable Delay
(Slow slew rate = ON;
VCCIO = 5.0V/3.3V; C L = 35 pF)
tXZ
Output Buffer Disable Delay (CL = 5 pF)
tSU
Register Setup Time
4
5
ns
tH
Register Hold Time
4
5
ns
tFSU
Register Setup Time of Fast Input
2
2
ns
tFH
Register Hold Time of Fast Input
2
2
ns
tRD
Register Delay
1
2
ns
tCOMB
Combinatorial Delay
1
2
ns
tIC
Array Clock Delay
6
7
ns
tEN
Register Enable Time
6
7
ns
tGLOB
Global Control Delay
1
1
ns
tPRE
Register Preset Time
4
5
ns
tCLR
Register Clear Time
4
5
ns
tUIM
Switch Matrix Delay
2
2
ns
13
14
ns
tRPA
Note:
14
Min
-20
(2)
Reduced-power Adder
Max
Min
Max
Units
10
11
ns
6
7
ns
1. See ordering information for valid part numbers.
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
SUPPLY CURRENT VS. SUPPLY VOLTAGE
ASV VERSION (T A = 25°C, F = 0)
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE
(VOH = 2.4V, TA = 25°C)
70
0
60
-2
-4
40
-6
IOH (mA)
ICC (mA)
STANDARD POWER
50
30
20
-8
-10
-12
REDUCED POWER
10
-14
-16
2.75
0
3
3.1
3.2
3.3
3.4
3.5
3.6
3.00
3.25
3.50
3.75
4.00
SUPPLY VOLTAGE (V)
V CC (V)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
ASVL (LOW-POWER) VERSION (TA = 25°C, F = 0)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE (TA = 25°C, F = 0)
5
14
12
4
ICC (mA)
ICC (mA)
10
8
TBD
6
3
TBD
2
4
1
2
0
0
3
3.1
3.2
3.3
3.4
3.5
3
3.6
3.1
3.2
3.3
3.4
3.5
3.6
V CC (V)
V CC (V)
SUPPLY CURRENT VS. FREQUENCY
ASVL (LOW POWER) VERSION (TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
ASV VERSION (T A = 25°C)
80.0
80.0
70.0
70.0
STANDARD POWER
60.0
60.0
ICC (mA)
ICC (mA)
STANDARD POWER
50.0
40.0
30.0
40.0
30.0
REDUCED POWER
20.0
REDUCED POWER
20.0
10.0
0.0
0.00
50.0
10.0
20.00
40.00
60.00
FREQUENCY (MHz)
80.00
100.00
0.0
0.00
5.00
10.00
15.00
20.00
25.00
FREQUENCY (MHz)
15
1615H–PLD–2/04
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
100
10
0
80
-20
IOL (mA)
IOH (mA)
-10
-30
-40
60
40
-50
20
-60
-70
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
4.0
0
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE
(VOL = 0.5V, TA = 25°C)
INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
40
15
INPUT CURRENT (uA)
IOL (mA)
35
30
25
20
2.75
3.00
3.25
3.50
3.75
4.00
10
5
0
-5
-10
0
SUPPLY VOLTAGE (V)
0.5
1
1.5
2
2.5
3
3.5
INPUT VOLTAGE (V)
INPUT CLAMP CURRENT VS. INPUT VOLTAGE
(VCC = 3.3V, T A = 25°C)
INPUT CURRENT (mA)
0
-20
-40
-60
-80
-100
-1
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
INPUT VOLTAGE (V)
16
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
ATF1502ASV Dedicated Pinouts
44-lead
TQFP
44-lead
J-lead
INPUT/OE2/GCLK2
40
2
INPUT/GCLR
39
1
INPUT/OE1
38
44
INPUT/GCLK1
37
43
I/O / GCLK3
35
41
I/O / PD (1,2)
5, 19
11, 25
I/O / TDI (JTAG)
1
7
I/O / TMS (JTAG)
7
13
I/O / TCK (JTAG)
26
32
I/O / TDO (JTAG)
32
38
GND
4, 16, 24, 36
10, 22, 30, 42
VCCI
9, 17, 29, 41
3, 15, 23, 35
# of Signal Pins
36
36
# User I/O Pins
32
32
Dedicated Pin
OE (1, 2)
Global OE pins
GCLR
Global Clear pin
GCLK (1, 2, 3)
Global Clock pins
PD (1, 2)
Power-down pins
TDI, TMS, TCK, TDO
JTAG pins used for boundary-scan testing or in-system programming
GND
Ground pins
VCCI
VCC pins for the device (+3.3V)
17
1615H–PLD–2/04
ATF1502ASV I/O Pinouts
18
MC
PLC
44-lead PLCC
44-lead TQFP
1
A
4
42
2
A
5
43
3
A
6
44
4/TDI
A
7
1
5
A
8
2
6
A
9
3
7/PD1
A
11
5
8
A
12
6
9/TMS
A
13
7
10
A
14
8
11
A
16
10
12
A
17
11
13
A
18
12
14
A
19
13
15
A
20
14
16
A
21
15
17
B
41
35
18
B
40
34
19
B
39
33
20/TDO
B
38
32
21
B
37
31
22
B
36
30
23
B
34
28
24
B
33
27
25/TCK
B
32
26
26
B
31
25
27
B
29
23
28
B
28
22
29
B
27
21
30
B
26
20
31/PD2
B
25
19
32
B
24
18
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
Ordering Information
tPD
(ns)
tCO1
(ns)
fMAX
(MHz)
15
8
15
Ordering Code
Package
100
ATF1502ASV-15 AC44
ATF1502ASV-15 JC44
44A
44J
Commercial
(0°C to 70°C)
8
100
ATF1502ASV-15 AI44
ATF1502ASV-15 JI44
44A
44J
Industrial
(-40°C to +85°C)
20
12
83.3
ATF1502ASV-20 AC44
ATF1502ASV-20 JC44
44A
44J
Commercial
(0°C to 70°C)
20
12
83.3
ATF1502ASV-20 AI44
ATF1502ASV-20 JI44
44A
44J
Industrial
(-40°C to +85°C)
Note:
Operation Range
1. Shaded area indicates preliminary data.
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the V CC conditions for 3.3V products are
the same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use
commercial product for industrial temperature ranges, de-rate ICC by 15%.
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
19
1615H–PLD–2/04
Packaging Information
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
20
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
ATF1502ASV
1615H–PLD–2/04
ATF1502ASV
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
21
1615H–PLD–2/04
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
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Atmel Sarl
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Fax: (49) 71-31-67-2340
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Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
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Fax: 1(719) 540-1759
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Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Literature Requests
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Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
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Printed on recycled paper.
1615H–PLD–2/04
xM