Features
• Advanced, High-speed, Electrically-erasable Programmable Logic Device
•
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•
•
•
•
•
•
•
•
•
•
•
– Superset of 22V10
– Enhanced Logic Flexibility
– Backward Compatible with ATV750B/BL and ATV750/L
Low-power Edge-sensing “L” Option with 1 mA Standby Current
D- or T-type Flip-flop
Product Term or Direct Input Pin Clocking
7.5 ns Maximum Pin-to-pin Delay with 5V Operation
Highest Density Programmable Logic Available in 24-pin Package
– Advanced Electrically-erasable Technology
– Reprogrammable
– 100% Tested
Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-flops
Enhanced Output Logic Flexibility
– All 20 Flip-flops Feed Back Internally
– 10 Flip-flops are also Available as Outputs
Programmable Pin-keeper Circuits
Dual-in-line and Surface Mount Package in Standard Pinouts
Commercial and Industrial Temperature Ranges
20-year Data Retention
2000V ESD Protection
1000 Erase/Write Cycles
High-speed
Complex
Programmable
Logic Device
ATF750C
ATF750CL
Block Diagram
(OE PRODUCT TERMS)
PROGRAMMABLE
INTERCONNECT
AND
COMBINATORIAL
LOGIC ARRAY
12
INPUT
PINS
LOGIC
OPTION
4 TO 8
PRODUCT
TERMS
10
I/O
PINS
OUTPUT
OPTION
(UP T0 20
FLIP-FLOPS)
(CLOCK PIN)
Description
The ATF750C(L)s are twice as powerful as most other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform, predictable delays
(continued)
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
*
No Internal Connection
VCC
+5V Supply
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
IN
IN
CLK/IN
*
VCC
I/O
I/O
CLK
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
IN
IN
IN
*
IN
IN
IN
4
3
2
1
28
27
26
Function
PLCC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
12
13
14
15
16
17
18
Pin Name
DIP/SOIC/TSSOP
IN
IN
GND
*
IN
I/O
I/O
Pin Configurations
I/O
I/O
I/O
*
I/O
I/O
I/O
Rev. 0776F–01/00
1
guarantee fast in-system performance. The ATF750C(L) is
a high-performance CMOS (electrically-erasable) complex
programmable logic device (CPLD) that utilizes Atmel’s
proven electrically-erasable technology.
Each of the ATF750C(L)’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms available. There are two
sum terms per output, providing added flexibility. A variable
format is used to assign between four to eight product
terms per sum term. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flipflops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power-up.
The ATF750C(L) is a low-power device with speeds
as fast as 15 ns. The ATF750C(L) provides the optimum
low-power CPLD solution. This device significantly
reduces total system power, thereby allowing batterypowered operations.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
1.
DC and AC Operating Conditions
All members of the family are specified to operate in either one of two voltage ranges. Parameters are specified as noted to
be either 2.7V to 3.6V, 5V ± 5% or 5V ± 10%.
5V Operation
Operating Temperature (Ambient)
VCC Power Supply
2
ATF750C(L)
Commercial
-7.5, -10, -15
Industrial
-10, -15
0°C - 70°C
-40°C - +85°C
5V ± 5%
5V ± 10%
ATF750C(L)
Logic Options
Combinatorial Output
Combined Terms
Registered Output
Combined Terms
Separate Terms
Separate Terms
Clock Mux
CKMUX
CKi
CLOCK
PRODUCT
TERM
CLK
PIN
TO
LOGIC
CELL
SELECT
Output Options
3
Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750C(L) have programmable “pin-keeper” circuits. If activated, when any pin is driven
high or low and then subsequently left floating, it will stay at
that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled
by the device type chosen in the logic compiler device
selection menu. Please refer to the software compiler table
for more details. Once the pin-keeper circuits are disabled,
normal termination procedures are required for unused
inputs and I/Os.
Table 1. Software Compiler Mode Selection
Synario
WINCUPL
Pin-keeper Circuit
ATF750C
V750C
Disabled
ATF750C (PPK)
V750CPPK
Enabled
Input Diagram
VCC
INPUT
100K
ESD
PROTECTION
CIRCUIT
PROGRAMMABLE
OPTION
I/O Diagram
VCC
OE
DATA
I/O
VCC
100K
PROGRAMMABLE
OPTION
4
ATF750C(L)
ATF750C(L)
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Output Leakage
Current
Min
Typ
Max
Units
VIN = -0.1V to VCC + 1V
10
µA
VOUT = -0.1V to VCC + 0.1V
10
µA
Com.
125
180
mA
Ind., Mil.
135
190
mA
Com.
125
180
mA
Ind., Mil.
135
190
mA
Com.
0.12
1
mA
Ind., Mil.
0.15
2
mA
-120
mA
-0.6
0.8
V
2.0
VCC + 0.75
V
C-7, -10
ICC
Power Supply
Current, Standby
VCC = Max,
VIN = Max,
Outputs Open
C-15
CL-15
IOS(1)
Output Short
Circuit Current
VOUT = 0.5V
VIL
Input Low Voltage
4.5 ≤ VCC ≤ 5.5V
VIH
Input High Voltage
VOL
Output Low
Voltage
VOH
Note:
Output High
Voltage
VIN = VIH or VIL,
VCC = Min
VIN = VIH or VIL,
VCC = Min
IOL = 16 mA
Com., Ind.
0.5
V
IOL = 12 mA
Mil.
0.5
V
IOL = 24 mA
Com.
0.8
V
IOH = -4.0 mA
2.4
V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and
Measurement Levels
Output Test Load
VCC
300
(390 MIL.)
tR, tF < 3 ns (10% to 90%)
390
(750 MIL.)
5
AC Waveforms, Product Term Clock(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock(1)
-7
Max
Min
C/CL-15
Symbol
Parameter
tPD
Input or Feedback to Non-registered Output
7.5
tEA
Input to Output Enable
tER
Input to Output Disable
tCO
Clock to Output
3
7.5
4
10
tCF
Clock to Feedback
1
5
4
7.5
tS
Input Setup Time
3
4
8/12
ns
tSF
Feedback Setup Time
3
4
7
ns
tH
Hold Time
1
2
5
ns
tP
Clock Period
7
11
14
ns
tW
Clock Width
3.5
5.5
7
ns
FMAX
Min
-10
Max
Min
Max
Units
10
15
ns
7.5
10
15
ns
7.5
10
15
ns
5
12
ns
5
9
ns
External Feedback 1/(tS + tCO)
95
71
50/41
MHz
Internal Feedback 1/(tSF + tCF)
125
86
62
MHz
No Feedback 1/(tP)
142
90
71
MHz
tAW
Asynchronous Reset Width
5
10
15
ns
tAR
Asynchronous Reset Recovery Time
3
10
15
ns
tAP
Asynchronous Reset to Registered Output Reset
tSP
Setup Time, Synchronous Preset
Note:
6
1. See ordering information for valid part numbers.
ATF750C(L)
8
4
12
7
15
8
ns
ns
ATF750C(L)
AC Waveforms, Input Pin Clock(1)
Notes:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Input Pin Clock
-7
Max
Min
C/CL-15
Symbol
Parameter
tPD
Input or Feedback to Non-registered Output
7.5
tEA
Input to Output Enable
tER
Input to Output Disable
tCOS
Clock to Output
0
6.5
0
7
tCFS
Clock to Feedback
0
3.5
0
5
tSS
Input Setup Time
4
5
8/12.5
ns
tSFS
Feedback Setup Time
4
5
7
ns
tHS
Hold Time
0
0
0
ns
tPS
Clock Period
7
10
12
ns
tWS
Clock Width
3.5
5
6
ns
FMAXS
Min
-10
Max
Min
Max
Units
10
15
ns
7.5
10
15
ns
7.5
10
15
ns
0
10
ns
0
5.5
ns
External Feedback 1/(tSS + tCOS)
95
83
55/44
MHz
Internal Feedback 1/(tSFS + tCFS)
133
100
80
MHz
No Feedback 1/(tPS)
142
100
83
MHz
tAW
Asynchronous Reset Width
5
10
15
ns
tARS
Asynchronous Reset Recovery Time
5
10
15
ns
tAP
Asynchronous Reset to Registered Output Reset
tSPS
Setup Time, Synchronous Preset
8
5
10
5/9
15
11
ns
ns
7
Functional Logic Diagram ATF750C, Upper Half
8
ATF750C(L)
ATF750C(L)
Functional Logic Diagram ATF750C, Lower Half
9
Preload of Registered Outputs
The ATF750C(L)’s registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the I/O pin will force the register
high; a VIL will force it low, independent of the output polarity. The PRELOAD state is entered by placing a 10.25V to
10.75V signal on pin 8 on DIPs, and lead 10 on SMDs.
When the clock term is pulsed high, the data on the I/O
pins is placed into the register chosen by the select pin.
Level Forced on Registered
Output Pin during Preload Cycle
Select Pin State
Register #0 State after Cycle
Register #1 State after Cycle
VIH
Low
High
X
VIL
Low
Low
X
VIH
High
X
High
VIL
High
X
Low
Power-up Reset
The registers in the ATF750C(L)s are designed to reset
during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock terms or
pin high, and
3. The clock pin, or signals from which clock terms are
derived, must remain stable during tPR.
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1000
ns
VRST
Power-up Reset Voltage
3.8
4.5
V
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
Units
CIN
5
8
pF
VIN = 0V
COUT
6
8
pF
VOUT = 0V
Note:
10
Conditions
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
ATF750C(L)
ATF750C(L)
Using the ATF750C’s Many Advanced
Features
Synchronous Preset and
Asynchronous Reset
The ATF750C(L)’s advanced flexibility packs more usable
gates into 24 pins than any other logic device. The
ATF750C(L)s start with the popular 22V10 architecture,
and add several enhanced features:
• Selectable D- and T-type Registers
Each ATF750C(L) flip-flop can be individually configured
as either D- or T-type. Using the T-type configuration, JK
and SR flip-flops are also easily created. These options
allow more efficient product term usage.
• Selectable Asynchronous Clocks
Each of the ATF750C(L)’s flip-flops may be clocked by
its own clock product term or directly from Pin 1 (SMD
Lead 2). This removes the constraint that all registers
must use the same clock. Buried state machines,
counters and registers can all coexist in one device while
running on separate clocks. Individual flip-flop clock
source selection further allows mixing higher
performance pin clocking and flexible product term
clocking within one design.
• A Full Bank of Ten More Registers
The ATF750C(L) provides two flip-flops per output logic
cell for a total of 20. Each register has its own sum term,
its own reset term and its own clock term.
• Independent I/O Pin and Feedback Paths
Each I/O pin on the ATF750C(L) has a dedicated input
path. Each of the 20 registers has its own feedback
terms into the array as well. This feature, combined with
individual product terms for each I/O’s output enable,
facilitates true bi-directional I/O design.
One synchronous preset line is provided for all 20 registers
in the ATF750C(L). The appropriate input signals to cause
the internal clocks to go to a high state must be received
during a synchronous preset. Appropriate setup and hold
times must be met, as shown in the switching waveform
diagram.
An individual asynchronous reset line is provided for each
of the 20 flip-flops. Both master and slave halves of the flipflops are reset when the input signals received force the
internal resets high.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF750C(L) fuse patterns. Once the security fuse
is programmed, all fuses will appear programmed during
verify.
The security fuse should be programmed last, as its effect
is immediate.
11
ATF750CL SUPPLY CURRENT
VS. SUPPLY VOLTAGE (TA = 25°C)
ATF750C SUPPLY CURRENT VS.
SUPPLY VOLTAGE (TA = 25°C)
140
100
120
80
100
ICC (µA)
160
120
ICC (mA)
140
60
80
40
60
20
40
20
0
4.50
4.75
5.00
5.25
5.50
0
4.50
SUPPLY VOLTAGE (V)
5.00
SUPPLY VOLTAGE (V)
5.25
5.50
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION (TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
160
4.75
140
120
100
ICC (mA)
ICC (mA)
120
80
80
60
40
40
20
0
0
0
5
10
25
50
75
0
100
5
10
50
75
100
ATF750C/CL OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
0
0.00
-5
-10.00
-10
-20.00
-15
-30.00
-20
IOH (mA)
IOH (mA)
ATF750C/CL OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VOH = 2.4V)
-25
-30
-40.00
-50.00
-60.00
-35
-70.00
-40
-80.00
-45
-50
4
4.5
5
5.5
SUPPLY VOLTAGE (V)
12
25
FREQUENCY (MHz)
FREQUENCY (MHz)
ATF750C(L)
6
-90.00
0.00
0.50
1.00
1.50
2.00
2.50
VOH (V)
3.00
3.50
4.00
4.50
5.00
ATF750C(L)
ATF750C/CL OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V)
ATF750C/CL OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
140
44
43
120
42
100
40
IOL (mA)
IOL (mA)
41
39
38
37
80
60
40
36
20
35
34
0
4
4.5
5
5.5
6
0
0.5
1
1.5
2
90
30
80
25
INPUT CURRENT (uA)
70
60
IOL (mA)
3
3.5
4
4.5
5
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V,TA = 25°C)
ATF750C/CL OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)
50
40
30
20
20
15
10
5
0
-5
-10
-15
10
-20
-25
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0
1
0.5
1
1.5
VOL (V)
ATF750C/CL INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V,TA = 25°C)
WITHOUT PIN-KEEPER
2
2.5
3
3.5
4
INPUT VOLTAGE (V)
4.5
5
5.5
6
ATF750C/CL INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 5V,TA = 35°C)
1.8
0
1.6
-10
INPUT CURRENT (mA)
INPUT CURRENT (uA)
2.5
VOL (V)
SUPPLY VOLTAGE (V)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-0.2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-0.2
-0.4
-0.6
-0.8
-1
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
13
ATF750C(L) Ordering Information
tPD
(ns)
tCOS
(ns)
Ext.
fMAXS
(MHz)
7.5
6.5
10
7
15
15
10
10
Ordering Code
Package
95
ATF750C-7JC
28J
Commercial
(0°C to 70°C)
83
ATF750C-10JC
ATF750C-10PC
ATF750C-10SC
ATF750C-10XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF750C-10JI
ATF750C-10PI
ATF750C-10SI
28J
24P3
24S
Industrial
(-40°C to 85°C)
ATF750C-15JC
ATF750C-15PC
ATF750C-15SC
ATF750C-15XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF750C-15JI
ATF750C-15PI
ATF750C-15SI
28J
24P3
24S
Industrial
(-40°C to 85°C)
ATF750CL-15JC
ATF750CL-15PC
ATF750CL-15SC
ATF750CL-15XC
28J
24P3
24S
24X
Commercial
(0°C to 70°C)
ATF750CL-15JI
ATF750CL-15PI
ATF750CL-15SI
28J
24P3
24S
Industrial
(-40°C to 85°C)
55
44
Operation Range
Using “C” Product for Industrial
To use commercial product for industrial ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” =
10 ns “I”) and de-rate power by 30%.
Package Type
28J
28-lead, Plastic J-leaded Chip Carrier (PLCC)
24P3
24-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
24S
24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
24X
24-lead, 0.173" Wide, Thin Shrink Small Outline (TSSOP)
14
ATF750C(L)
Packaging Information
28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AB
24P3, 24-lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AF
.045(1.14) X 45° PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
PIN
1
.430(10.9)
SQ
.390(9.91)
.021(.533)
.013(.330)
.456(11.6)
SQ
.450(11.4)
.032(.813)
.026(.660)
1.27(32.3)
1.25(31.7)
.012(.305)
.008(.203)
.495(12.6)
SQ
.485(12.3)
.266(6.76)
.250(6.35)
.090(2.29)
MAX
1.100(27.94) REF
.050(1.27) TYP
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.300(7.62) REF SQ
.180(4.57)
.165(4.19)
.200(5.06)
MAX
.005(.127)
MIN
SEATING
PLANE
.070(1.78)
.020(.508)
.023(.584)
.014(.356)
.151(3.84)
.125(3.18)
.022(.559) X 45° MAX (3X)
.110(2.79)
.090(2.29)
.065(1.65)
.040(1.02)
.325(8.26)
.300(7.62)
.012(.305)
.008(.203)
0 REF
15
.400(10.2) MAX
24S, 24-lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)
24X, 24-lead, 0.173" Wide, Thin Shrink Small Outline
(TSSOP)
Dimensions in Millimeters and (Inches)*
.020(.508)
.013(.330)
.299(7.60) .420(10.7)
.291(7.39) .393(9.98)
PIN 1 ID
.050(1.27) BSC
.616(15.6)
.598(15.2)
.105(2.67)
.092(2.34)
.012(.305)
.003(.076)
.013(.330)
.009(.229)
0 REF
8
15
.050(1.27)
.015(.381)
ATF750C(L)
*Controlling dimension: millimeters
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