Features • • • • • • • • • • • • • 3.0V to 5.5V Operating Range Advanced Low Voltage, Zero Power, Electrically Erasable Programmable Logic Device Edge-Sensing “Zero” Power Low Voltage Equivalent of ATF22V10CZ “Zero” Standby Power (25 µA Maximum) Ideal for Battery Powered Systems 25 ns Maximum Propagation Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Hold Inputs to Previous Logic States Advanced E2 Technology Reprogrammable 100% Tested High Reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-Line and Surface Mount Standard Pinouts High Performance E2 PLD ATF22LV10CZ Block Diagram Pin Configurations Pin Name Function CLK Clock IN Logic Inputs I/O Bidirectional Buffers VCC (3 to 5.5V) Supply DIP/SOIC ATF22LV10CZ TSSOP Top View CLK/IN IN IN IN IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN PLCC Top view Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. Rev. 0779E/LV10CZ-E–05/98 Description The ATF22LV10CZ is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technology and provides 25 ns speed with stand-by current of 25 µA maximum. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. operating at supply voltages down to 3.0V. Pin “keeper” circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The ATF22LV10CZ macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all 10 registers and are automatically cleared upon power up. Register Preload simplifies testing. A Security Fuse prevents unauthorized copying of programmed fuse patterns. The ATF22LV10CZ provides a low voltage and edgesensing “zero” power CMOS PLD solution with “zero” standby power (5 µA typical). The ATF22LV10CZ powers down automatically to the zero power mode through Atmel’s patented Input Transition Detection (ITD) circuitry when the device is idle. The ATF22LV10CZ is capable of Absolute Maximum Ratings* Temperature Under Bias................... -40°C to +85°C Storage Temperature...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......................... -2.0V to +7.0V (1) Voltage on Input Pins with Respect to Ground During Programming.................... -2.0V to +14.0V (1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Programming Voltage with Respect to Ground....................... -2.0V to +14.0V (1) 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns. DC and AC Operating Conditions 2 Commercial Industrial Operating Temperature (Case) 0°C - 70°C -40°C - 85°C VCC Power Supply 3.0V - 5.5V 3.0V - 5.5V ATF22LV10CZ ATF22LV10CZ Functional Logic Diagram Description The Functional Logic Diagram describes the ATF22LV10CZ architecture. The ATF22LV10CZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four output configurations: active-high/low or registered/combinatorial. The universal architecture of the ATF22LV10CZ can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the contents of the ATF22LV10CZ. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse. DC Characteristics Symbol Parameter Condition Min Typ Max Units IIL Input or I/O Low Leakage Current 0 ≤ VIN ≤ VIL(MAX) -10 µA IIH Input or I/O High Leakage Current VCC - 0.7V ≤ VIN ≤ VCC 10 µA ICC Clocked Power Supply Current VCC = MAX, Outputs Open, f = 15 MHz Com. 55 85 mA Ind. 60 90 mA ISB Power Supply Current, VCC = MAX, Standby VIN = MAX, Outputs Open Com. 5 25 µA Ind. 5 50 µA IOS (1) Output Short Circuit Current -130 mA VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.75 V VOL Output Low Voltage 0.5 V VOH Note: Output High Voltage VOUT = 0.5V VIN = VIH or VIL VCC = MIN, IOL = 8 mA VIN = VIH or VIL, VCC = MIN, IOH = -4.0 mA Com. Ind. 2.4 V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 3 AC Waveforms INPUTS, I/O REG. FEEDBACK SYNCH. PRESET tS tH tW tW CP tP tAW tAR ASYNCH. RESET tCO tAP REGISTERED OUTPUTS VALID tER VALID tPD COMBINATORIAL OUTPUTS tEA OUTPUT DISABLED tER VALID VALID VALID tEA OUTPUT DISABLED VALID AC Characteristics (1) -25 Symbol Min Max Units 3 25 ns 13 ns 15 ns tPD Input to Feedback to Non-Registered Output tCF Clock to Feedback tCO Clock to Output 2 tS Input or Feedback Setup Time 15 ns tH Input Hold Time 0 ns tP Clock Period 25 ns tW Clock Width 12.5 ns FMAX External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) 33.3 35.7 40.0 MHz MHz MHz tEA Input to Output Enable 3 25 ns tER Input to Output Disable 3 25 ns tAP Input or I/O to Asynchronous Reset of Register 3 25 ns tSP Setup Time, Synchronous Preset 15 ns tAW Asynchronous Reset Width 25 ns tAR Asynchronous Reset Recovery Time 25 ns tSPR Synchronous Preset to Clock Recovery Time 15 ns Note: 4 Parameter 1. See ordering information for valid part numbers. ATF22LV10CZ ATF22LV10CZ Input Test Waveforms and Measurement Levels Output Test Loads Note: Similar competitors’ devices are specified with slightly different loads. These load differences may affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions. Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ Max Units CIN 5 8 pF VIN = 0V COUT 6 8 pF VOUT = 0V Note: Conditions 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 5 Power Up Reset Electronic Signature Word The registers in the ATF22LV10CZ are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22LV10CZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. 1. The VCC rise must be monotonic and start below 0.7V 3. The clock must remain stable during TPR. The security fuse should be programmed last, as its effect is immediate. 2. After TPR, all input and feedback setup times must be met before driving the clock pin high. Programming/Erasing Preload of Register Outputs Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming. The ATF22LV10CZ’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. Parameter 6 Description Typ Max Units TPR Power-Up Reset Time 600 1,000 ns VRST Power-Up Reset Voltage 2.3 2.7 V ATF22LV10CZ ATF22LV10CZ Input and I/O Pin Keepers All ATF22LV10CZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). Input Diagram I/O Diagram 7 Functional Logic Diagram ATF22LV10CZ 8 ATF22LV10CZ ATF22LV10CZ tPD (ns) tS (ns) tCO (ns) 25 15 15 Ordering Code Package Operation Range 15 ATF22LV10CZ-25JC ATF22LV10CZ-25PC ATF22LV10CZ-25SC ATF22LV10CZ-25XC 28J 24P3 24S 24X Commercial (0°C to 70°C) 15 ATF22LV10CZ-25JI ATF22LV10CZ-25PI ATF22LV10CZ-25SI ATF22LV10CZ-25XI 28J 24P3 24S 24X Industrial (-40°C to +85°C) Package Type 28J 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24P3 24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP) 24S 24-Lead, 0.300" Wide, Plastic Gull WIng Small Outline (SOIC) 24X 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 9