INTEGRATED CIRCUITS DATA SHEET TZA3004HL SDH/SONET data and clock recovery unit STM1/4 OC3/12 Objective specification File under Integrated Circuits, IC19 1998 Feb 09 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL FEATURES DESCRIPTION • Data and clock recovery up to 622 Mbits/s (STM1/OC3 and STM4/OC12) The TZA3004HL is a data and clock recovery IC intended for use in SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) systems. The circuit recovers data and extracts the clock signal from an incoming bitstream up to 622 Mbits/s. It can be configured for use in STM1/OC3 and STM4/OC12 systems. • Differential data input with 2.5 mV peak-to-peak typical sensitivity • Differential CML (Current-Mode Logic) data and clock outputs with 50 Ω driving capability • Adjustable CML output level • Loop mode for system testing APPLICATIONS • BER related LOS detection • Data and clock recovery in STM1/OC3 and STM4/OC12 transmission systems (up to 622 Mbits/s). • Few external components needed • LQFP48 plastic package • Power dissipation typical 370 mW • Single supply voltage. ORDERING INFORMATION TYPE NUMBER TZA3004HL 1998 Feb 09 PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 2 VERSION SOT313-2 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL BLOCK DIAGRAM LOS handbook, full pagewidth 30 39 DCSQ AREF SEL155 ENL 1 48 FREQUENCY DIVIDER 1 4/16 36 42 43 45 DATA AND CLOCK OUTPUT 33 DIN ALEXANDER PHASE DETECTOR 34 DINQ CREFQ 21 FREQUENCY WINDOW DETECTOR (1000 ppm) + 9 24 LOCK REF19 REF39 POWER CONTROL 37 2 16 15 CAPDOQ CAPUPQ Fig.1 Block diagram. 1998 Feb 09 3 DLOOP DLOOPQ CLOOP CLOOPQ 130 pF 25, 31 MGK140 GND COUTQ integrating path FREQUENCY DIVIDER 2 64/128 12 COUT VCRO 130 pF 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47 DOUTQ proportional path ∫ dt 17 7 4 enable 22 6 3 TZA3004HL CREF 46 DOUT VEE PC Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 PINNING SYMBOL PIN DESCRIPTION ENL 1 loop mode enable input (active low) GND 2 ground CLOOP 3 clock output in loop mode (differential) CLOOPQ 4 inverted clock output in loop mode (differential) GND 5 ground DLOOP 6 data output in loop mode (differential) DLOOPQ 7 inverted data output in loop mode (differential) GND 8 ground REF19 9 reference frequency select input (see Table 2) GND 10 ground GND 11 ground LOCK 12 phase lock detection output i.c 13 internally connected (leave open) GND 14 ground CAPUPQ 15 external loop filter capacitor CAPDOQ 16 external loop filter capacitor return GND 17 ground i.c. 18 internally connected (leave open) i.c. 19 internally connected (leave open) GND 20 ground CREF 21 reference clock input (differential) CREFQ 22 inverting reference clock input (differential) GND 23 ground REF39 24 reference frequency select input (see Table 2) VEE 25 negative supply voltage GND 26 ground VEE 27 negative supply voltage VEE 28 negative supply voltage GND 29 ground SEL155 30 STM mode select input (see Table 1) VEE 31 negative supply voltage GND 32 ground DIN 33 data input (differential) DINQ 34 inverting data input (differential) GND 35 ground i.c. 36 internally connected (leave open) PC 37 negative power supply control signal output GND 38 ground LOS 39 loss-of-signal detection output i.c. 40 internally connected (leave open) 1998 Feb 09 4 TZA3004HL Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 SYMBOL PIN TZA3004HL DESCRIPTION COUT 45 clock output in normal mode (differential) COUTQ 46 inverted clock output in normal mode (differential) GND 47 ground AREF 48 reference voltage input for controlling voltage swing on data and clock outputs ENL 42 DOUT 48 AREF handbook, full pagewidth 37 PC ground 38 GND 44 39 LOS GND 40 n.c. inverted data output in normal mode (differential) 41 GND data output in normal mode (differential) 43 43 DOUTQ 42 DOUTQ 44 GND DOUT 45 COUT ground 46 COUTQ 41 47 GND GND i.c. 36 DCSQ 1 GND 2 35 GND CLOOP 3 34 DINQ CLOOPQ 4 33 DIN 32 GND GND 5 DLOOP 6 31 VEE TZA3004HL 30 SEL155 DLOOPQ 7 Fig.2 Pin configuration. 1998 Feb 09 5 GND 23 REF39 24 CREFQ 22 CREF 21 GND 20 25 VEE n.c. 19 LOCK 12 n.c. 18 26 GND GND 17 VEE 27 n.c. GND 11 CAPUPQ 15 GND 10 CAPDOQ 16 VEE 28 n.c. GND 14 29 GND n.c. 13 GND 8 REF19 9 MGK139 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 of the clock signal, while the integrating path adjusts the centre frequency. FUNCTIONAL DESCRIPTION The TZA3004HL recovers data and clock signals from an incoming high speed bitstream. The input signal on DIN, DINQ is buffered and amplified by the input circuitry. The frequency window detector checks that the VCRO frequency is within a 1000 ppm (parts per million) window around the required frequency. It compares the output of frequency divider 2 with the reference frequency at CREF, CREFQ (19.44 MHz or 38.88 MHz as available; see Table 2). If the VCRO frequency is found to be outside this window, the frequency window detector disables the Alexander phase detector and forces the VCRO output to a frequency within the window. The phase detector then starts acquiring lock again. Because of the loose coupling (1000 ppm), the reference frequency doesn’t need to be highly accurate or stable. Any crystal based oscillator that generates a reasonably accurate frequency (e.g. 100ppm) )will do. The signal is then fed to the Alexander phase detector where the phase of the incoming data is compared with that of the internal clock. If the signals are out of phase, the phase detector generates (UP or DOWN) correction pulses that shift the phase of the VCRO (Voltage Controlled Ring Oscillator) output in discrete amounts, ∆ϕ, until the clock and data signals are in phase. The technique used is based on principles first proposed by J.D.H. Alexander, hence the phase detector’s name. The eye pattern of the incoming data is sampled at three instants A, T and B (see Fig.3). When clock and data signals are synchronized (locked), A is in the centre of the data bit, T is in the vicinity of the next transition, and B is in the centre of the bit following the transition. If the same level is recorded at both A and B, a transition has not occurred and no action is taken regardless of the value at T. If A and B are different, however, a transition has occurred and the phase detector uses the value at T to determine whether the clock was too early or too late with respect to the data transition. If A and T are the same, but different from B, the clock was too early and needs to be slowed down a little. The Alexander phase detector then generates a DOWN pulse which stretches a single output pulse from the ring oscillator by approximately 0.25% (or 4 ps in STM4 mode; 4 ps is 0.25% of the 1.608 ns bit period). This forces the VCRO to run at a slightly lower frequency for one bit period. The phase of the clock is thus shifted fractionally with respect to the data. Since sampling point A is always in the centre of the eye pattern when the data and clock signals are in phase (locked), the values recorded at this point are taken as the retrieved data. The data and clock signals are available at the CML output buffers, which are capable of driving a 50 Ω load. handbook, halfpage DATA A T B CLOCK MGK143 Fig.3 Data sampling. If, on the other hand, B and T are the same but different from A, the clock was too late and needs to be speeded up for synchronization. The phase detector generates an UP pulse forcing the VCRO to run at a slightly higher frequency (+0.25%) for one bit period. The phase of the clock is shifted with respect to the data (as above, but in the opposite direction). Only the proportional path is active while these phase adjustments are being made. Because the instantaneous frequency of the VCRO can be changed only in one of two discrete steps (±0.25%), this type of loop is also known as a Bang/Bang PLL. Power Control (PC) The TZA3004HL contains an on-board voltage regulator. An external power transistor is needed to deliver supply current, IEE, to this circuit. The required external circuit is straightforward, and can be built using a few components. A suitable circuit is depicted in Fig.4. A different configuration could be used, as long as the power supply rejection ratio is greater than 60 dB for all frequencies. The inductor is a (lossy) 1 µH RF-choke (EMI) with an impedance greater than 50 Ω at frequencies higher than 2 MHz. Any transistor with a β > 100 and enough current sink capability can be used. If not only the phase but also the frequency of the VCRO is incorrect, a long train of UP or DOWN pulses will be generated. This pulse train is integrated to generate a control voltage that is used to shift the centre frequency of the VCRO. Once the correct frequency has been established, the phase will need to be adjusted for synchronization. The proportional path adjusts the phase 1998 Feb 09 TZA3004HL The TZA3004HL can also be used with a -5V or -5.2V supply voltage. The only adaption that has to be made to the Power Control circuit is resistor R of 2Ω. This should be 6.8Ω with a -5V supply and 8.2Ω with a -5.2V supply. 6 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL handbook, full pagewidth BAND GAP REFERENCE POWER CONTROL 100 nF 2Ω VEE PC β > 100 1 kΩ 2Ω 1 kΩ 3.3 nF 1 µF 1 µH −4.5 V MGK141 Fig.4 Schematic diagram of TZA3004HL power control loop. This can be achieved by connecting a 7.3 kΩ resistor between AREF and VEE. Output amplitude reference (AREF) The voltage swing at the CML compatible output stages DOUT, DOUTQ; COUT, COUTQ; DLOOP, DLOOPQ and CLOOP, CLOOPQ can be controlled by adjusting the voltage at the AREF pin. An internal voltage divider of 500 Ω and16 kΩ between GND and VEE initially fixes this level. The formulae for calculating the required voltage at AREF and the external resistance needed between AREF and VEE when the outputs are AC coupled are: RL + Ro 1 V AREF = – -------------------- × --- V swing RL 2 In most applications the outputs will be DC coupled to a load, which can be as low as 50 Ω (±0.20%). The output level regulation circuit will maintain a 200 mV peak-to-peak single-ended swing across this load. The voltage at AREF is half the single-ended peak-to-peak value of the output signal (or −100 mV in this case). No adjustments are necessary with DC coupling. and: R AREF If the outputs are AC coupled, however, the voltage at AREF is half the single-ended peak-to-peak value of the RL + Ro output signal multiplied by a factor -------------------RL V EE R1 × ---------------- – 1 V AREF = --------------------------------------------------------------- R1 V EE 1 – -------- × ---------------- – 1 R2 V AREF (2) where R1 = 500 Ω, R2 = 16 kΩ and VEE = −3.3 V. RAREF is connected between AREF and VEE. where R L is the external load and Ro is the output impedance of the TZA3004HL. To maintain a 200 mV peak-to-peak single-ended swing across a 50 Ω AC coupled load, the voltage at AREF must – 100 mV × ( 50 Ω + 100 Ω ) be ------------------------------------------------------------------------- = – 300 mV . 50 Ω 1998 Feb 09 (1) 7 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL Loop mode enable (ENL) Loss-of-signal detection (LOS) Loop mode is provided for system testing. Loop mode is enabled by applying a voltage lower than 0.8 V (TTL LOW) to the ENL pin. This selects loop mode outputs DLOOP, DLOOPQ and CLOOP, CLOOPQ. If a voltage greater than 2.0 V (TTL HIGH) is applied to ENL, then DOUT, DOUTQ and COUT, COUTQ are switched in while DLOOP, DLOOPQ and CLOOP, CLOOPQ are disabled to minimize power consumption. If ENL is connected to VEE (−3.3 V), all outputs are enabled. The Loss of Signal (LOS) function is closely related to the Alexander Phase Detector functionality. Refer to Fig.3 for the meaning of A,B and T in this section. In the functional description it is described that the phase detector doesn’t take any action if the value at sample points A and B is the same, because there hasn’t been any transition. However, if the values at A and B are the same, but different from T, this still means there hasn’t been any transition, but somehow T got the wrong value. This is probably due to noise or bad signal integrity, which will lead to a Bit Error. Hence the occurrence of this particular situation is an indication for Bit Errors. If too many of these Bit Errors occur per time and the PLL is gradually losing lock, the LOS alarm is asserted. The LOS assert level is around a Bit Error Rate (BER) of 5⋅10-2 and the de-assert level is around BER of 1⋅10-3. External capacitor for loop filter (CAPUPQ; CAPDOQ) The loop filter is an integrator with a built in capacitance of 2 × 130 pF. An external 200 nF capacitance must be connected between CAPUPQ and CAPDOQ to ensure loop stability while the frequency window detector is active. The LOS detection is BER related, but neither dependent of datastream content, nor protocol. Therefore, a SDH/SONET datastream is no prerequisite for a proper LOS function. Since the LOS function of the TZA3004HL is derived from digital signals, it is a good supplement to an analog, amplitude based, LOS indication. Lock detection (LOCK) The LOCK pin should be interpreted as an indication if the reference clock (CREF) is present and if the acquisition aid (frequency window detector) is working properly. The LOCK pin is an open collector TTL output and should be pulled up with a 10kΩ resistor to the positive supply. If the VCO frequency is within a 1000 ppm window around the desired frequency the LOCK pin will go HIGH. If no reference clock is present, or the VCO is outside the 1000 ppm window, the LOCK pin will be LOW. The logic level of LOCK does not indicate if the PLL is locked onto the incoming data; this is indicated by the LOS signal. The LOS alarm is an open collector TTL compatible output. A pull-up resistor should be connected to a positive supply. LOS will be HIGH (TTL) if the data signal is absent at DIN, DINQ or BER is > 5⋅10-2, otherwise it will be LOW (BER < 1⋅10-3). Reference frequency select (REF19, REF39) A reference clock signal (either 19.44 MHz or 38.88 MHz, whichever is available) must be connected to CREF and CREFQ. Pins REF19 and REF39 are used to select the appropriate output frequency at frequency divider 2. Since the reference clock is only used as acquisition aid for the PLL (Frequency Window Detector), the quality of the reference clock is not important. There is no phase noise specification imposed on the reference clock generator and even frequency stability may be in the order of 100 ppm. In general most inexpensive crystal based oscillators are suitable. STM mode selection (SEL155) SEL155 should be connected to VEE for STM1/OC3 (155.52 Mbits/s) operation. For STM4/OC12 (622.08 Mbits/s) systems, SEL155 should be connected to GND. The connections to VEE and GND should have low resistance and inductance. Short PCB tracks are recommended. Table 1 STM Mode Select BIT RATE Mbits/s DIV # SEL155 STM1 155.52 16 VEE STM4 622.08 4 GND MODE 1998 Feb 09 Table 2 Reference Frequency Select FREQUENCY MHz 8 DIV # REF19 REF39 38.88 64 VEE VEE 19.44 128 GND VEE Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 approximately 3.3V below VCC). Beware not to connect ENL to ground, this would destroy the IC. In the positive supply application the NORMAL MODE outputs can not be selected anymore. POSITIVE SUPPLY APPLICATION Due to the versatile design of the TZA3004HL, the device can also operate in a positive supply application, although some pins have a different mode of operation. This section deals with these differences and supports the user with successful application of the TZA3004HL in a +5V environment. A sample application diagram can be found in figure 4. Note that all GND pins are now connected to VCC. All VEE pins are not connected to ground, but to pin 25, the regulated voltage from the power controller. Loss of signal detect and Lock detect (LOS & LOCK) In the negative supply application, LOS and LOCK are open collector outputs, that require pull-up resistors to a positive supply. In the positive supply application, the pull-up voltage would be higher then the positive supply and the LOS and LOCK signals would not be TTL compatible. The internal circuit at pins LOS and LOCK can however be used in a current mirror configuration. It requires only an external PNP transistor, BC857 or equivalent, to mirror the current. A 10kΩ pull-down resistor to ground yields a TTL compatible signal again, albeit inverted. The table below shows the meaning of the LOS and LOCK flag, when used according to the application schematic of figure 4. Loop mode and normal mode output select (ENL) In a positive supply application, the default RF output will be the LOOP MODE outputs. Due to the decoding logic at the ENL pin, it is only possible to select the pins DLOOP(Q) and CLOOP(Q) as outputs or enable all outputs. If ENL is connected to VCC (+5V), the LOOP MODE outputs are active. All outputs become active If ENL is connected to pin VEE (the voltage on pin 25 is Table 3 TZA3004HL LOS and LOCK indication for positive supply SIGNAL LOS active LOS inactive DESCRIPTION Loss-of-signal; BER >5 10-2 No loss-of-signal; BER < 1 10-3 LEVEL TTL 0V (ground) LOW +5V (VCC) HIGH LOCK active Reference clock present and VCO in 1000 ppm window 0V (ground) LOW LOCK inactive No reference clock present or VCO outside 1000 ppm window +5V (VCC) HIGH pins GND. In the positive supply application, this means all RF signals are referenced to VCC. Therefore a clean VCC rail is of ultimate importance for proper RF performance. The best performance is obtained when the transmission line reference plane is also decoupled to the VCC. Careful design of VCC and good decoupling schemes should be taken into account. While designing the printed circuit board, bear in mind that the VCC has become what was formerly ground. Divider settings The reference frequency dividers and the STM mode selectors still operate the same in a positive supply application. The only difference is that pins formerly connected to GND (ground) should now be connected to VCC (+5V), whereas pins connected to VEE still should be connected to pin VEE (pin 25). Connection to ground (0V) will damage the IC. RF input/outputs All RF inputs, outputs and internal signals of the TZA3004HL are referenced to the most positive supply, 1998 Feb 09 9 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MAX. UNIT −6 +0.5 V pins 3, 4, 6, 7, 21, 22, 33, 34, 42, 43, 45, 46 −1 +0.5 pins 1, 12, 39 VEE − 0.5 +5.5 V V pins 9, 24, 30, 37, 48 VEE − 0.5 +0.5 pins 15, 16 VEE + 0.5 −0.5 V pin 1 − 1 mA pins 21, 22, 33, 34 −20 +10 mA VEE negative supply voltage Vn DC voltages In MIN. V input current Ptot total power dissipation − 700 mW Tamb ambient temperature −40 +85 °C Tj junction temperature −40 +110 °C Tstg storage temperature −65 +150 °C THERMAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS Rth(j-s) thermal resistance from junction to solder point Rth(j-a) thermal resistance from junction to ambient in free air VALUE UNIT 46 K/W 67 K/W Note 1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided 57x57x1.6mm FR4 epoxy PCB with 35µm thick copper traces. The measurements are performed in free air. 1998 Feb 09 10 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL CHARACTERISTICS External supply voltage = −4.5 V; Tamb = -40°C to +85°C; Typical values at Tamb=25°C; all voltages referenced to GND. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VEE negative supply voltage note 1 −3.50 −3.30 −3.10 V IEE negative supply current open outputs − 112 155 mA P power dissipation − 370 550 mW 50 Ω measurement system 7 200 450 mV − 2.5 7 mV Data and Clock inputs: DIN, DINQ and CREF, CREFQ Vi(p-p) Vsens(p-p) input voltage (peak-to-peak) (2)(3) input sensitivity (peak-to-peak) (2)(4) VIO input offset voltage −3 0 +3 mV VI, VIQ input voltages −600 −200 +250 mV − 50 − Ω Zi single ended input impedance(2) Data and Clock outputs: DOUT, DOUTQ; DLOOP, DLOOPQ; COUT, COUTQ and CLOOP, CLOOPQ Vo(p-p) voltage swing (single ended)(6) voltage swing (single ended) 50 Ω measurement system 170 (7) 200 210 mV 50 − 400 mV VO, VOQ output voltages −600 − 0 mV Zo single ended output impedance − 100 − Ω tr, tf rise/fall time data outputs − 116 − ps clock outputs − 54 − ps note 8 50 80 110 ps floating pin −110 −100 −90 mV td data to clock delay differential Output amplitude adjustment: AREF VAREF output amplitude reference voltage Power Control output: PC gm transconductance −84 −60 −42 mA/V IO output current 1 − 3.5 mA Loop mode enable input: ENL VIL LOW-level input voltage − − 0.8 V VIH HIGH-level input voltage 2.0 − − V Phase lock and loss-of-signal indicators: LOCK and LOS VOL HIGH-level output voltage note 9 −0.6 − − V VOH LOW-level output voltage note 9 − − 3.3 V 1998 Feb 09 11 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 SYMBOL PARAMETER TZA3004HL CONDITIONS MIN. TYP. MAX. − 0.1 LOS de-assert time − 10 − µs LOS assert Bit Error Rate − 5 ⋅10−2 − BER LOS de-assert Bit Error Rate − 1 ⋅10−3 − BER CREF = 19.44 MHz − 50 200 µs CREF = 38.88 MHz − 100 200 µs f = 6.5 kHz 1.5 >5 − UI f = 65 kHz 0.15 1.3 − UI f = 1 MHz 0.15 0.8 − UI f = 25 kHz 1.5 >5 − UI f = 100 kHz 0.7 3 − UI ta LOS assert time td BERLOS note 10 − UNIT µs PLL Characteristics tacq Jtol(p-p)(5) acquisition time jitter tolerance (peak-to-peak) STM1/OC3 mode STM4/OC12 mode TDR transitionless data run f = 250 kHz 0.15 1.3 − UI f = 1 MHz 0.15 0.50 − UI f = 5 MHz 0.15 0.35 − UI − 2000 − bits note 6 Notes 1. Typical supply voltage for the voltage regulator is −4.5 V (see Fig.4). 2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value. (true differential excitation) 3. The specified input voltage range is the guaranteed and tested range for proper operation; BER <10-10. 4. An input sensitivity for BER <10-10 of 7 mVpp is guaranteed. Typical input sensitivity for BER <10-10 is 2.5mVpp. 5. CML inputs are terminated internally using 50 Ω on-chip resistors to ground (GND). 6. Output voltage range with default reference voltage on AREF (floating pin). 7. Output voltage range with adjustment of voltage on AREF (see section “Output amplitude reference (AREF)”). 8. Data to clock delay according to figure 7. Measured with 1010 data pattern, single ended output signals and rising edge of COUT to DOUT or CLOOP to DLOOP. Note that small deviations from specified value are possible if differentially measured. 9. External 10 kΩ pull-up resistor to +3.3 V. 10. LOS assert/de-assert timing and BER level are for indication only. The values are neither production tested nor guaranteed. 11. Measured according ITU specification G.958 on the OM5800 STM4 demoboard. 12. TDR is bitrate independent. 1998 Feb 09 12 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 handbook, full pagewidth CML INPUT TZA3004HL CML OUTPUT VI(max) GND GND VO(max) VIQH VOQH VOH VIH Vi (p-p) VIQL VIL Vo (p-p) VOQL VOL VIO VOO VO(min) VI(min) MGK144 Fig.5 Logic level symbol definitions for CML. GND COUT or CLOOP -200mV td GND DOUT or DLOOP -200mV Fig.6 Data to clock delay for CML outputs; COUT to DOUT or CLOOP to DLOOP. 1998 Feb 09 13 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) 1.0E+0 1.0E-1 1.0E-2 1.0E-3 BER 1.0E-4 1.0E-5 1.0E-6 1.0E-7 1.0E-8 1.0E-9 1.0E-10 0.0 0.2 0.4 0.6 0.8 1.0 Vin(p-p) in mV Fig.7 Bit Error Rate versus input signal on DI/DIQ in STM1 mode(155.52 Mbits/s). (A complementary input signal of the indicated value is applied to DI and DIQ). 1998 Feb 09 14 1.2 1.4 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) 1.0E+0 1.0E-1 1.0E-2 1.0E-3 BER 1.0E-4 1.0E-5 1.0E-6 1.0E-7 1.0E-8 1.0E-9 1.0E-10 0.0 0.2 0.4 0.6 0.8 1.0 Vin (p-p) in mV Fig.8 Bit Error Rate versus input signal on DI/DIQ in STM4 mode (622.08 Mbits/s). (A complementary input signal of the indicated value is applied to DI and DIQ.. 1998 Feb 09 15 1.2 1.4 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) 100 10 1 0.1 10 100 1000 10000 Fig.9 Jitter Tolerance in STM4 mode (622.08 Mbits/s). Measured on OM5800 demoboard TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED) Fig.10 Output waveforms on Data and Clock outputs in STM4 mode (622.08 Mbits/s). (single ended) 1998 Feb 09 16 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL APPLICATION SCHEMATIC +3.3 V handbook, full pagewidth 10 kΩ LOS CAPUPQ 15 100 nF 39 +3.3 V 100 nF 16 CAPDOQ 10 kΩ LOCK 12 DIN PREAMP (OQ2539) 33 42 34 43 DINQ DCSQ 36 45 TZA3004HL 46 6 7 CREF 38.88/19.44 MHz system clock 21 3 22 4 CREFQ 1 REF19 VEE REF39 48 9 24 30 27,28 25, 31 DOUTQ normal output COUT COUTQ DLOOP DLOOPQ loop output CLOOP CLOOPQ ENL output select AREF SEL155 37 VEE GND(1) DOUT PC 17 100 nF β > 100 2Ω 1 kΩ 2Ω 1 kΩ 3.3 nF 1 µF 1 µH −4.5 V MGK142 (1) All GND pins must be connected directly to the PCB ground plane (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). Fig.11 Application diagram showing the TZA3004HL configured for 622.08 Mbits/s DCR mode (STM4/OC12). 1998 Feb 09 17 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL APPLICATION INFORMATION (POSITIVE SUPPLY) +3.3 VCCV +3.3 V handbook, full pagewidth handbook, full pagewidth LOS 39 LOS 39 CAPUPQ CAPUPQ 15 15 100 nF 100 nF 16 CAPDOQ 16 CAPDOQ 100 nF 100 nF 10 kΩ 10 kΩ +3.3 V +3.310kΩ V 10 kΩ 10 kΩ LOCK 12 LOCK 12 LOS VCC LOCK 10kΩ PREPREAMP AMP (OQ2539) (OQ2539) 38.88/19.44 MHz 38.88/19.44 MHz system clock system clock VCC VEE VEE DIN DIN 33 DINQ 33 DINQ 34 34 DCSQ DCSQ 36 36 TZA3004HL TZA3004HL CREF CREF 21 CREFQ 21 CREFQ 22 22 REF19 REF19 9 REF39 9 REF39 24 24 17 17 GND(1) GND(1) 100 100 nF nF 2Ω 2Ω 27,28 25, 31 25, 31 VEE VEE 37 37 PC PC 42 42 43 43 45 45 46 46 6 6 7 7 3 3 4 4 1 1 48 48 30 30 DOUT DOUT DOUTQ DOUTQ COUT COUT COUTQ COUTQ DLOOP DLOOP DLOOPQ DLOOPQ CLOOP CLOOP CLOOPQ CLOOPQ ENL ENL AREF AREF SEL155 SEL155 unused output normal normal output output = loop loop output output = main output output output select select VCC β > 100 β > 100 VCC 1 1 kΩ kΩ 2Ω 2Ω 1 1 kΩ kΩ 3.3 3.3 nF nF 1 µF 1 µF1 µH 1 µH −4.5 V V MGK142 −4.5 MGK142 VCC VCC (1) All GND pins must be connected directly to the PCB +5V (VCC) plane (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47). Fig.12 Application diagram showing the TZA3004HL configured for 622.08 Mbits/s positive supply application. Note that loopmode outputs are used as outputs. ENL=HIGH selects these outputs. ENL=LOW selects loopmode and normal mode outputs simultaneously. 1998 Feb 09 18 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 94-12-19 97-08-01 SOT313-2 1998 Feb 09 EUROPEAN PROJECTION 19 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1998 Feb 09 TZA3004HL 20 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 TZA3004HL DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Feb 09 21 Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 NOTES 1998 Feb 09 22 TZA3004HL Philips Semiconductors Objective specification SDH/SONET data and clock recovery unit STM1/4 OC3/12 NOTES 1998 Feb 09 23 TZA3004HL Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 425102/200/01/pp24 Date of release: 1998 Feb 09 Document order number: 9397 750 03271