ETC OQ2541BHP

INTEGRATED CIRCUITS
DATA SHEET
OQ2541BHP; OQ2541BU
SDH/SONET data and clock
recovery unit STM1/4/16
OC3/12/48 GE
Product specification
File under Integrated Circuits, IC19
2000 Sep 18
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
FEATURES
DESCRIPTION
• Data and clock recovery up to 2.5 Gbits/s
The OQ2541B is a data and clock recovery IC intended for
use in Synchronous Digital Hierarchy (SDH) and
Synchronous Optical Network (SONET) systems. The
circuit recovers data and extracts the clock signal from an
incoming bitstream up to 2.5 Gbits/s.
• Multirate configurable (155, 622, 1250 or 2500 Mbits/s)
• Full ITU-T jitter compliance (G.958 and G.813)
• Full Bellcore jitter compliance
• Differential data input with 2.5 mV (p-p) typical
sensitivity
The OQ2541B can be configured for use in STM1/OC3,
STM4/OC12, STM16/OC48 and GE systems, with full
ITU-T G.958 and G.813 jitter compliance, or Bellcore jitter
compliance, whichever is applicable. The OQ2541B also
features a bypass mode, for non SDH/SONET or
GE bit rates, in which the clock recovery function is
bypassed.
• Differential Current-Mode Logic (CML) data and clock
outputs with 50 Ω driving capability
• Adjustable CML output level
• Bypass mode for non SDH/SONET or Gigabit
Ethernet (GE) bit rates
• Loop mode for system testing
• Bit Error Rate (BER) related Loss Of Signal (LOS)
detection
• Few external components needed
• Single supply voltage
• Power dissipation 400 mW (typical value)
• LQFP48 plastic package.
APPLICATIONS
• Data and clock recovery in STM1/OC3, STM4/OC12
and STM16/OC48 transmission systems
• Data and clock recovery in GE transmission systems
• Regenerator and repeater applications
• Wavelength conversion regenerator in Dense
Wavelength Division Multiplexing (D)WDM applications.
ORDERING INFORMATION
TYPE
NUMBER
OQ2541BHP
OQ2541BU
2000 Sep 18
PACKAGE
NAME
LQFP48
−
DESCRIPTION
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
bare die; 2360 × 2360 × 380 µm
2
VERSION
SOT313-2
−
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
BLOCK DIAGRAM
DOUT622
handbook, full pagewidth
LOS
DOUT155
DOUT1250
27
39
AREF ENL
30
28
48
1
24
FREQUENCY
DIVIDER 1
1/2/4/16
42
43
45
DATA
AND
CLOCK
OUTPUT
33
DIN
ALEXANDER
PHASE
DETECTOR
34
DINQ
46
6
7
3
OQ2541B
4
enable
10
CREF
CREFQ
21
FREQUENCY
WINDOW
DETECTOR
(1000 ppm)
22
proportional
path
+
∫ dt
i.c.
5
13, 18, 19,
36, 40
16
2, 5, 8, 11, 14, 17, 20
23, 26, 29, 32, 35, 38
41, 44, 47
130 pF
LOCK
DREF19
15
CAPDOQ
CAPUPQ
Fig.1 Block diagram.
2000 Sep 18
3
COUT
COUTQ
DLOOP
DLOOPQ
CLOOP
CLOOPQ
BYPASS
130 pF
25
31
VEE1
VEE2
37
MGT203
GND
DOUTQ
VCRO
2.5 GHz
POWER
CONTROL
16
9
DOUT
integrating
path
FREQUENCY
DIVIDER 2
64/128
12
ALLON
PC
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
PINNING
SYMBOL
PIN
DESCRIPTION
ENL
1
loop mode enable input (active LOW)
GND
2
ground; note 1
CLOOP
3
clock output in loop mode (differential)
CLOOPQ
4
inverted clock output in loop mode (differential)
GND
5
ground; note 1
DLOOP
6
data output in loop mode (differential)
DLOOPQ
7
inverted data output in loop mode (differential)
GND
8
ground; note 1
DREF19
9
reference frequency select input 1 (see Table 2)
BYPASS
10
data recovery and clock extraction bypass mode input
GND
11
ground; note 1
LOCK
12
phase lock detection output
i.c.
13
internally connected; note 2
GND
14
ground; note 1
CAPUPQ
15
external loop filter capacitor connection
CAPDOQ
16
external loop filter capacitor return connection
GND
17
ground; note 1
i.c.
18
internally connected; note 2
i.c.
19
internally connected; note 2
GND
20
ground; note 1
CREF
21
reference clock input (differential)
CREFQ
22
inverting reference clock input (differential)
GND
23
ground; note 1
ALLON
24
enable all outputs (input active LOW)
VEE1
25
negative supply voltage (−3.3 V); note 3
GND
26
ground; note 1
DOUT1250
27
STM mode select input 1 (see Table 3)
DOUT622
28
STM mode select input 2 (see Table 3)
GND
29
ground; note 1
DOUT155
30
STM mode select input 3 (see Table 3)
VEE2
31
negative supply voltage (−3.3 V); note 3
GND
32
ground; note 1
DIN
33
data input (differential)
DINQ
34
inverting data input (differential)
GND
35
ground; note 1
i.c.
36
internally connected; note 2
PC
37
control output for negative power supply
GND
38
ground; note 1
LOS
39
loss of signal detection output
i.c.
40
internally connected; note 2
2000 Sep 18
4
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
SYMBOL
PIN
OQ2541BHP; OQ2541BU
DESCRIPTION
GND
41
ground; note 1
DOUT
42
data output in normal mode (differential)
DOUTQ
43
inverted data output in normal mode (differential)
GND
44
ground; note 1
COUT
45
clock output in normal mode (differential)
COUTQ
46
inverted clock output in normal mode (differential)
GND
47
ground; note 1
AREF
48
reference voltage input for controlling voltage swing on data and clock outputs
Notes
1. All GND pins or pads must be bonded; do not leave one single GND pin or pad unconnected.
2. All pins or pads denoted ‘i.c.’ should not be connected. Connections to these pins or pads degrade device
performance.
37 PC
38 GND
39 LOS
41 GND
40 i.c.
42 DOUT
43 DOUTQ
44 GND
45 COUT
46 COUTQ
48 AREF
handbook, full pagewidth
47 GND
3. All VEE pins or pads must be bonded; do not leave one single VEE pin or pad unconnected.
ENL 1
36 i.c.
GND 2
35 GND
CLOOP 3
34 DINQ
CLOOPQ 4
33 DIN
32 GND
GND 5
DLOOP 6
31 VEE2
OQ2541BHP
30 DOUT155
DLOOPQ 7
29 GND
GND 8
DREF19 9
28 DOUT622
BYPASS 10
27 DOUT1250
Fig.2 Pin configuration.
2000 Sep 18
5
ALLON 24
GND 23
CREFQ 22
GND 20
CREF 21
i.c. 19
i.c. 18
GND 17
CAPUPQ 15
25 VEE1
CAPDOQ 16
LOCK 12
GND 14
26 GND
i.c. 13
GND 11
MGT204
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
If, on the other hand, levels B and T are the same but
different from level A, the clock was too late and needs to
be speeded up for synchronization. The phase detector
generates an up pulse, forcing the VCRO to run at a
slightly higher frequency (+0.25%) for one bit period. The
phase of the clock signal is shifted with respect to the data
signal (as above, but in the opposite direction). While
making these phase adjustments, only the proportional
path is active. Because the instantaneous frequency of the
VCRO can be changed in one of two discrete steps only
(±0.25%), this type of loop is also known as a Bang/Bang
Phase-Locked Loop (PLL).
FUNCTIONAL DESCRIPTION
The OQ2541B recovers data and clock signals from an
incoming high speed bitstream. The input signal on
pins DIN and DINQ is buffered and amplified by the input
circuit (see Fig.1). The signal is then fed into the Alexander
phase detector, where the phase of the incoming data
signal is compared with that of the internal clock. If the
signals are out of phase, the phase detector generates
correction pulses (up or down) that shift the phase of the
Voltage Controlled Ring Oscillator (VCRO) output in
discrete amounts (∆ϕ) until the clock and data signals are
in phase. The technique used is based on principles first
proposed by J.D.H. Alexander, hence the name of the
phase detector.
If not only the phase but also the frequency of the VCRO
is incorrect, a long train of up or down pulses will be
generated. This pulse train is integrated to generate a
control voltage that is used to shift the centre frequency of
the VCRO. Once the correct frequency has been
established, only the phase needs to be adjusted for
synchronization. The proportional path adjusts the phase
of the clock signal, whereas the integrating path adjusts
the centre frequency.
Data sampling
The eye pattern of the incoming data is sampled at three
instants A, T and B (see Fig.3). When clock and data
signals are synchronized (locked):
• A is the centre of the data bit
• T is in the vicinity of the next transition
Frequency window detector
• B is in the centre of the bit following the transition.
The frequency window detector checks the VCRO
frequency, which has to be within a 1000 ppm (parts per
million) window around the required frequency.
If the same level is recorded at both A and B, a transition
has not occurred and no action is taken, regardless of
level T. However, if levels A and B are different, a
transition has occurred and the phase detector uses
level T to determine whether the clock was too early or too
late with respect to the data transition.
The detector compares the output of frequency divider 2
with the reference frequency on pins CREF and CREFQ
(19.44 or 38.88 MHz; see Table 2). If the VCRO frequency
is found to be outside this window, the frequency window
detector disables the Alexander phase detector and forces
the VCRO output to a frequency within the window. Then,
the phase detector starts acquiring lock again. Due to the
loose coupling of 1000 ppm, the reference frequency does
not need to be highly accurate or stable. Any crystal-based
oscillator that generates a reasonably accurate frequency
(e.g. 100 ppm) will do.
If levels A and T are the same but different from level B,
the clock was too early and needs to be slowed down a
little. The Alexander phase detector then generates a
down pulse which stretches a single output pulse from the
ring oscillator by approximately 0.25% which is 1 ps of the
400 ps bit period in the STM16/OC48 mode. This forces
the VCRO to run at a slightly lower frequency for one bit
period. The phase of the clock signal is thus shifted
fractionally with respect to the data signal.
Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers that are capable of driving a 50 Ω
load.
handbook, halfpage
DATA
A
T
RF data and clock input circuit
B
The schematic of the input circuit is shown in Fig.4.
CLOCK
MGK143
RF data and clock output circuit
Fig.3 Data sampling.
2000 Sep 18
The schematic of the output circuit is shown in Fig.5.
6
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
handbook, halfpage
100 Ω
50 Ω
100 Ω
DOUTQ, COUTQ
DOUT, COUT
50 Ω
DIN,
CREF
DINQ,
CREFQ
VAREF
MGL669
VEE
VEE
Fig.4 RF data and clock input circuit.
MGL670
Fig.5 RF data and clock output circuit.
Power supply and power control loop
Output amplitude reference
The OQ2541B contains an on-board voltage regulator.
An external power transistor is needed to deliver the
supply to this circuit. The required external circuit is
straightforward, and can be built using a few components.
A suitable circuit with a power supply of −4.5 V is illustrated
in Fig.6. Do not omit the 2 Ω resistor in series with the
100 nF decoupling capacitor.
The voltage swing at the CML compatible output stages
(pins DOUT, DOUTQ, COUT, COUTQ, DLOOP,
DLOOPQ, CLOOP and CLOOPQ) can be controlled by
adjusting the voltage on pin AREF (see Fig.7). An internal
voltage divider of 500 Ω and 16 kΩ connected between
ground and VEE initially fixes this level.
In most applications, the outputs will be DC coupled to a
50 Ω load. The output level regulation circuit will maintain
a 200 mV (p-p) single-ended swing across this load. The
voltage on pin AREF is half the single-ended peak-to-peak
value of the output signal (−100 mV). No adjustments are
necessary with DC coupling.
A different configuration could be used, as long as the
power supply rejection ratio is greater than 60 dB for all
frequencies. The inductor is an RF choke with an
impedance greater than 50 Ω at frequencies higher than
2 MHz. Any transistor with a β of approximately 100 and
sufficient current sink capability can be used.
If the outputs are AC coupled, the voltage on pin AREF is
half the single-ended peak-to-peak value of the output
RL + Ro
signal multiplied by a factor -------------------RL
The OQ2541B can also be used with a power supply of
−5.0 or −5.2 V. The only adaptation to be made to the
power control circuit is to change the emitter resistor R1
(see Table 1).
Table 1
where RL is the external load and Ro is the output
impedance of the OQ2541B (100 Ω).
Value of resistor R1
POWER SUPPLY
RESISTOR R1
−4.5 V
6.8 Ω
−5.0 V
8.2 Ω
−5.2 V
10.0 Ω
2000 Sep 18
The resulting output amplitude with the same voltage on
pin AREF is thus different for DC and AC coupled loads.
7
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
handbook, full pagewidth
BAND GAP
REFERENCE
on chip
100 nF
PC
VEE
GND
off chip
β ≈ 100
2Ω
1 kΩ
R1
6.8 Ω
1
kΩ
3.3
nF
1 µF
L1(1)
−4.5 V
MGT205
(1) L1 = RF choke type Murata BLM21 or equivalent.
Fig.6 Schematic diagram of OQ2541B power control loop.
If the outputs are AC coupled, the formulae for calculating
the required voltage on pin AREF and the value of the
resistor connected between pins AREF and VEE are as
follows:
RL + R
V AREF = – --------------------O- × 0.5V swing
RL
handbook, halfpage
GND
500 Ω
and:
AREF
16 kΩ
VAREF
RAREF
R AREF
VEE
on chip
V EE
– 1
R1 ×  -------------- V AREF
= -----------------------------------------------------------V EE
R1
1 –  -------- ×  --------------– 1 
 R2  V AREF
where R1 = 500 Ω, R2 = 16 kΩ and VEE = −3.3 V.
off chip
MGL667
To maintain a single-ended swing of 200 mV (p-p) across
a 50 Ω AC-coupled load, the voltage on pin AREF must be
( 50 + 100 )Ω
– 100 mV × --------------------------------- = – 300 mV
50 Ω
Fig.7 Functionality of pin AREF.
2000 Sep 18
This can be achieved by connecting a 7.3 kΩ resistor
between pins AREF and VEE.
8
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
External capacitor for loop filter
Bypass mode
The loop filter is an integrator with a built-in capacitance of
2 × 130 pF. To ensure loop stability while the frequency
window detector is active, an external capacitance of
360 nF (2 times 180 nF parallel) must be connected
between pins CAPUPQ and CAPDOQ.
The bypass mode is provided to use the OQ2541B at non
standard SDH/SONET or GE bit rates. The data recovery
and clock extraction function can be bypassed if no clock
extraction is needed, or when the bit rate is different from
155, 622, 1250 or 2488 Mbit/s. Here, the incoming data
from DIN and DINQ is directly fed to the RF outputs. Clock
outputs COUT, COUTQ, CLOOP, CLOOPQ and the
LOS detection have no meaning in this mode.
Loop mode enable
The loop mode is provided for system testing (see Fig.8).
In the bypass mode, the data and clock recovery circuit is
disabled to reduce crosstalk. The bypass mode can be
activated by applying a voltage lower than −2.0 V or higher
than +2.0 V to pin BYPASS. If the voltage on this pin is
between −0.8 and +0.8 V, extracted data and recovered
clock are present on the RF outputs (normal
DCR operation). The input has the same structure as the
ENL input (see Fig.8).
The loop mode is enabled by applying a voltage between
−0.8 and +0.8 V (LOW-level TTL) to pin ENL. This selects
the loop mode: the outputs on pins DLOOP, DLOOPQ,
CLOOP and CLOOPQ are switched on.
If a voltage higher than 2.0 V (HIGH-level TTL) or lower
than −2.0 V is applied to pin ENL, then pins DOUT,
DOUTQ, COUT and COUTQ are switched on while
pins DLOOP, DLOOPQ, CLOOP and CLOOPQ are
disabled to minimize power consumption.
handbook,off
halfpage
chip
ENL,
ALLON,
BYPASS
Lock detection
Pin LOCK should be interpreted as an indication of the
presence of the reference clock on pin CREF and of the
proper functioning of the acquisition aid (frequency
window detector).
on chip
Pin LOCK is an open-collector TTL output and is to be
pulled up with a 10 kΩ resistor to a positive supply voltage.
If the VCO frequency is within a 1000 ppm window around
the desired frequency, pin LOCK will stay at a HIGH level.
If no reference clock is present, or the VCO is outside the
1000 ppm window, pin LOCK will be at a LOW level. The
logic level on pin LOCK does not indicate locking of the
PLL to the incoming data; this is indicated by the signal on
pin LOS.
36 kΩ
GND
DECODER
LOGIC
Loss of signal detection
VEE
Fig.8
The LOS function is closely related to the functionality of
the Alexander phase detector; see Fig.3 for the meaning
of A, B and T in this section.
MGT206
Input circuit of pins ENL, ALLON and
BYPASS.
The functional description states that the phase detector
does not take any action if the value at sample points
A and B are the same, as there has not been any
transition. However, if levels A and B are the same but
different from level T, this still means there has not been
any transition, but level T has got the wrong level
somehow. This is probably due to noise or bad signal
integrity, which will lead to a bit error. Hence, the
occurrence of this particular situation is an indication of bit
errors. If too many of these bit errors occur per time and
the PLL is gradually losing lock, the LOS alarm is asserted.
The LOS alarm assert level is around BER = 5 × 10−2 and
the de-assert level is around BER = 1 × 10−3.
All outputs active
All outputs (normal outputs DOUT, DOUTQ, COUT,
COUTQ and loop mode outputs DLOOP, DLOOPQ,
CLOOP and CLOOPQ) can be activated by applying a
voltage lower than −2.0 V or higher than +2.0 V to
pin ALLON. If the voltage on this pin is between
−0.8 and +0.8 V, the active outputs can be selected by
pin ENL. The input has the same structure as the
ENL input (see Fig.8).
2000 Sep 18
9
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
The LOS function will only work properly if the input signal
is larger than the input offset of the OQ2541B. Otherwise,
the signal will be masked by the input offset and
interpreted as consecutive bits of the same sign, thus
obstructing a proper LOS detection. In practice, an optical
front-end device with a noise level (RMS value) larger than
the specified offset of the OQ2541B will ensure a proper
LOS indication.
Table 2
The LOS detection is BER related, but neither dependent
on the data stream content nor protocol. Therefore, an
SDH/SONET data stream is not a prerequisite for a proper
LOS function. Since the LOS function of the OQ2541B is
derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.
The VCRO has a large tuning range. However, the
performance of the OQ2541B is optimized for
SDH/SONET, including GE bit rates.
FREQUENCY
(MHz)
DIVISION
FACTOR
LEVEL ON PIN
DREF19
38.88
64
ground
19.44
128
VEE
STM mode selection
Due to the nature of the PLL, the wide tuning range is a
necessity for proper lock behaviour over the guaranteed
temperature range, aging and batch to batch spread.
Pin LOS is an open-collector TTL compatible output.
A pull-up resistor is to be connected to a positive supply
voltage.
Though it might seem that the OQ2541B is capable of
recovering other bit rates than SDH/SONET and
GE bit rates (STM1/OC3, STM4/OC12, STM16/OC48 and
1250 Mbits/s), the behaviour cannot be guaranteed.
The LOS pin will be at a HIGH level (TTL) if the data signal
is absent on pins DIN and DINQ or if BER > 5 × 10−2.
Otherwise, pin LOS will be at a LOW level if
BER < 1 × 10−3.
The required SDH/SONET bit rate is selected by
connecting pins DOUT155, DOUT622 and DOUT1250
to ground or to the supply voltage VEE (see Table 3):
• For STM16/OC48 (2488.32 Mbits/s) operation, all three
pins have to be connected to ground
Reference frequency select
A reference clock signal of 19.44 or 38.88 MHz must be
connected to pins CREF and CREFQ. It should be noted
that the reference frequency should be either
39.0625 or 19.53125 MHz in a GE system. Pin DREF19 is
used to select the appropriate output frequency at
frequency divider 2 (see Table 2).
• For GE (1250 Mbits/s) operation, pin DOUT1250 has to
be connected to VEE
• For STM4/OC12 (622.08 Mbits/s) operation,
pins DOUT1250 and DOUT622 have to be connected
to VEE (the dividers are daisy chained)
• For STM1/OC3 (155,52 Mbits/s) operation, all three pins
have to be connected to VEE.
To minimize the adverse influence of reference clock
crosstalk, a differential signal with an amplitude from
75 to 150 mV (p-p) is advised.
The connections to VEE and ground carry a current of a
few mA and should have low resistance and inductance.
Therefore, short printed-circuit board tracks are
recommended. In some cases, a small decoupling
capacitor (approximately 100 pF) near the selection pins
might be necessary to provide a clean return path for
RF currents.
Since the reference clock is only used as an acquisition aid
for the PLL of the frequency window detector, the quality
of the reference clock (i.e. phase noise) is not important.
There is no phase noise specification imposed on the
reference clock generator and even frequency stability
may be in the order of 100 ppm. In general, most
inexpensive crystal-based oscillators are suitable.
When the OQ2541B is used in an application with a fixed
data rate, it is best to connect pins DOUT155, DOUT622
and DOUT1250 through a short track or a via to the ground
plane or pin VEE. If a selectable bit rate is required in the
application, the pins can be controlled through low-ohmic
switching FETs, e.g. BSH103 or equivalent (low RDSon).
When the OQ2541B is used in an application with a fixed
reference clock frequency, it is best to connect
pin DREF19 through a short track or a via to the ground
plane or pin VEE. If a selectable reference clock frequency
is required in the application, the pin can be controlled
through a low ohmic switching FET, e.g. BSH103 or
equivalent (low RDSon).
2000 Sep 18
Reference frequency selection
10
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
Table 3
OQ2541BHP; OQ2541BU
STM mode select
BIT RATE
(Mbits/s)
DIVISION
FACTOR
STM1/OC3
155.52
STM4/OC12
622.08
Gigabit Ethernet
STM16/OC48
MODE
LEVEL ON PIN
DOUT155
DOUT622
DOUT1250
16
VEE
VEE
VEE
4
ground
VEE
VEE
1250.00
2
ground
ground
VEE
2488.32
1
ground
ground
ground
Application with positive supply voltage
LOSS OF SIGNAL AND LOCK DETECTION
The versatile design of the OQ2541B also allows it to
operate in a positive supply voltage application, although
some pins have a different mode of operation. This section
deals with these differences and supports the user with
achieving a successful application of the OQ2541B in a
5 V environment.
In the negative supply application, pins LOS and LOCK
are open-collector outputs that require pull-up resistors to
a positive supply voltage.
In the positive supply application, the pull-up voltage
needs to be higher than the positive supply voltage and the
signals on pins LOS and LOCK would no longer be
TTL compatible. However, the internal circuit on pins LOS
and LOCK can be used in a current mirror configuration
(see Fig.9). This requires only an external PNP transistor
(e.g. BC857 or equivalent) to mirror the current. A 10 kΩ
pull-down resistor from the collector of the external
transistor to ground yields a TTL compatible signal again,
albeit inverted. Table 5 shows the meaning of the LOS and
LOCK flags, when used in the positive supply application.
APPLICATION DIAGRAM
Fig.32 shows a sample application diagram. It should be
noted that all pins GND are now connected to VCC and all
pins VEE are connected to the regulated voltage from the
power controller.
OUTPUT SELECTION
In a positive supply voltage application, the functions of
pins ENL, ALLON and BYPASS are different than in a
negative supply application, see also Table 4.
The functions can be activated by a voltage more than
2.0 V lower than 5.0 V (VCC). Preferably, they should be
connected to VEE (pin 25), which is approximately 3.3 V
below VCC. If the pins do not differ by more than 0.8 V
of VCC (5.0 V), the functions are deactivated.
handbook, halfpage
off chip
GND
If the pin is connected to GND (0 V) in the negative supply
application, it should now be connected to 5.0 V (the
voltage on pins GND). If the pin is connected to a positive
voltage >0.8 V in the negative supply application, then it
should be connected to VEE (pin 25, approximately 3.3 V
below VCC). Beware not to connect pins ENL, ALLON or
BYPASS to a voltage lower than that on pin 25, because
this causes serious damage to the OQ2541B.
+5 V
BC857
LOS,
LOCK
signal out
10 kΩ
MGL671
CAUTION
Fig.9
Do not connect pins ENL, ALLON or BYPASS to ground,
because this will destroy the IC.
2000 Sep 18
on chip
11
Signal out for LOS and LOCK indications in
a positive supply voltage application.
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
Table 4
OQ2541BHP; OQ2541BU
Output selection in a positive supply voltage application
LEVEL ON PIN
OUTPUT
MODE
ENL
ALLON
BYPASS
DLOOP,
DLOOPQ,
CLOOP AND
CLOOPQ
DOUT, DOUTQ,
COUT AND
COUTQ
DCR loop
VCC (5 V)
VCC (5 V)
VCC (5 V)
active
−
DCR all outputs
−
VEE (VCC − 3.3 V) VCC (5 V)
active
active
DCR normal
VEE (VCC − 3.3 V) VCC (5 V)
VCC (5 V)
−
active
Bypass loop
VCC (5 V)
VEE (VCC − 3.3 V)
active
−
VEE (VCC − 3.3 V) VEE (VCC − 3.3 V)
active
active
−
active
LEVEL
TTL
0 V (ground)
LOW
Bypass all outputs −
Bypass normal
Table 5
VCC (5 V)
VEE (VCC − 3.3 V) VCC (5 V)
VEE (VCC − 3.3 V)
LOS and LOCK indication in a positive supply voltage application
SIGNAL
LOS active
DESCRIPTION
loss of signal: BER > 5 ×
10−2
10−3
LOS inactive
no loss of signal: BER < 1 ×
5 V (VCC)
HIGH
LOCK active
reference clock present and VCRO
inside 1000 ppm window
0 V (ground)
LOW
LOCK inactive
no reference clock present or VCRO
outside 1000 ppm window
5 V (VCC)
HIGH
DIVIDER SETTINGS
return paths are available for all frequencies (both of
interest and not of interest). These return paths should
preferably have an enclosed area as small as possible,
both horizontally and vertically (by means of through-holes
or vias). The position of a decoupling capacitor is very
important. A decoupling capacitor at an unfavourable
position could do more damage than completely omitting
the capacitor, while at the right location it might mean the
difference between mediocre results and the ultimate
achievement.
The reference frequency dividers and the STM mode
selectors still operate the same in a positive supply voltage
application. The only difference is that pins formerly
connected to ground should now be connected to
VCC (5 V). Pins connected to VEE should still be connected
to VEE because connecting these pins to ground (0 V) will
damage the IC.
RF INPUT AND OUTPUTS
All RF inputs, outputs and internal signals of the OQ2541B
are referenced to pins GND. In the positive supply voltage
application, this means that all RF signals are referenced
to VCC. Therefore, a clean VCC rail is of utmost importance
for proper RF performance. The best performance is
obtained when the transmission line reference plane is
also decoupled to VCC. Careful design of VCC and good
decoupling schemes should be taken into account. While
designing the printed-circuit board, bear in mind that the
VCC has become what was formerly ground.
While laying out the application, the return path is the most
important issue to be considered. It is always advised to
carefully examine the current carrying loops in the design.
Care should be taken that low ohmic and low inductance
2000 Sep 18
12
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MAX.
UNIT
−6
+0.5
V
CLOOP, CLOOPQ, DLOOP, DLOOPQ, CREF, CREFQ, DIN, DINQ,
DOUT, DOUTQ, COUT and COUTQ
−1
+0.5
V
ENL, ALLON, BYPASS, LOCK and LOS
VEE − 0.5 +5.5
V
DREF19, DOUT1250, DOUT622, DOUT155, PC and AREF
VEE − 0.5 +0.5
V
CAPUPQ and CAPDOQ
VEE + 0.5 −0.5
V
ENL, ALLON and BYPASS
−
1
mA
CREF, CREFQ, DIN and DINQ
−20
+10
mA
VEE
negative supply voltage
Vn
DC voltage on pins
In
MIN.
input current on pins
Ptot
total power dissipation
−
700
mW
Tamb
ambient temperature
−10
+85
°C
Tj
junction temperature
−10
+110
°C
Tstg
storage temperature
−65
+150
°C
HANDLING INSTRUCTIONS
Precautions should be taken to avoid damage through electrostatic discharge. This is particularly important during
assembly and handling of the bare die. Additional safety can be obtained by bonding the VEE and GND pads first, the
remaining pads may then be bonded to their external connections in any order.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
Rth(j-s)
thermal resistance from junction to solder point
Rth(j-a)
thermal resistance from junction to ambient
in free air; note 1
VALUE
UNIT
46
K/W
67
K/W
Note
1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided
57 × 57 × 1.6 mm FR4 epoxy PCB with 35 µm thick copper tracks. The measurements are performed in still air.
2000 Sep 18
13
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
CHARACTERISTICS
VEE = −3.35 V; Tamb = −10 to +85 °C; typical values measured at Tamb = 25 °C; all voltages are measured with respect
to GND.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VEE
negative supply voltage
see Fig.12; note 1
−3.50
−3.35
−3.10
V
IEE
negative supply current
50 Ω loaded; see Fig.13
−
125
160
mA
Ptot
total power dissipation
−
400
560
mW
Data and clock inputs: pins DIN, DINQ, CREF and CREFQ
Vi(p-p)
input voltage
(peak-to-peak value)
50 Ω measurement system;
see Fig.10; notes 2 and 3
7
200
450
mV
Vi(sens)(p-p)
input sensitivity
(peak-to-peak value)
50 Ω measurement system;
notes 2 and 4
−
2.5
7
mV
VIO
DC input offset voltage
50 Ω measurement system
−3
0
+3
mV
VI
input voltage
50 Ω measurement system
−600
−200
+250
mV
Zi
input impedance
single-ended; see Fig.4; note 5
−
50
−
Ω
Data and clock outputs: pins DOUT, DOUTQ, DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and CLOOPQ
Vo(p-p)
output voltage swing
(peak-to-peak value)
50 Ω measurement system;
single-ended; see Fig.10
default adjustment; note 6
170
200
210
mV
50
−
400
mV
−600
−
0
mV
single-ended
−
100
−
Ω
differential; 20% to 80%
−
50
−
ps
clock output fall time
differential; 20% to 80%
−
50
−
ps
data output rise time
differential; 20% to 80%
−
120
−
ps
tf(D)
data output fall time
differential; 20% to 80%
−
120
−
ps
td(D-C)
data-to-clock delay
see Figs. 11 and 14; note 8
220
260
300
ps
floating pin
−110
−100
−90
mV
special adjustment; note 7
VO
output voltage
Zo
output impedance
tr(C)
clock output rise time
tf(C)
tr(D)
Output amplitude adjustment: pin AREF
VAREF
output amplitude reference
voltage
Power control output: pin PC
gm
transconductance
−84
−60
−42
mA/V
IO
output current
1
−
3.5
mA
Loop mode enable input: pins ENL, ALLON and BYPASS
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
−0.8
−
0.8
V
see descriptions of ENL,
ALLON and BYPASS
−3.3
−
−2.0
V
2.0
−
5.0
V
Phase lock indicator: pin LOCK
VOL
LOW-level output voltage
note 9
−0.6
−
−
V
VOH
HIGH-level output voltage
note 9
−
−
3.3
V
2000 Sep 18
14
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
SYMBOL
PARAMETER
OQ2541BHP; OQ2541BU
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Loss of signal indicator: pin LOS
VOL
LOW-level output voltage
note 9
−0.6
−
−
V
VOH
HIGH-level output voltage
note 9
−
−
3.3
V
tas
assert time
note 10
−
0.1
−
µs
tdas
de-assert time
note 10
−
10
−
BERas
assert bit error rate
note 10
−
5 × 10−2 −
BER
BERdas
de-assert bit error rate
note 10
−
1 × 10−3 −
BER
CREF = 19.44 MHz
−
100
200
µs
CREF = 38.88 MHz
−
50
200
µs
f = 6.5 kHz
1.5
>2.5
−
UI
f = 65 kHz
0.15
0.8
−
UI
f = 1 MHz
0.15
0.8
−
UI
f = 25 kHz
1.5
>2.5
−
UI
f = 250 kHz
0.15
0.7
−
UI
f = 5 MHz
0.15
0.7
−
UI
f = 100 kHz
1.5
>2.5
−
UI
f = 1 MHz
0.15
0.4
−
UI
f = 10 MHz
0.15
0.3
−
UI
STM1/OC3 mode; note 11;
see Fig.17
−
125
180
kHz
STM4/OC12 mode; note 11;
see Fig.19
−
500
700
kHz
STM16/OC48 mode; note 11;
see Fig.21
−
1.8
2.8
MHz
f = 500 Hz to 1.3 MHz
−
0.04
0.50
UI
f = 12 kHz to 1.3 MHz
−
0.025
0.10
UI
f = 65 kHz to 1.3 MHz
−
0.02
0.10
UI
f = 1 kHz to 5 MHz
−
0.050
0.50
UI
f = 12 kHz to 5 MHz
−
0.035
0.10
UI
f = 250 kHz to 5 MHz
−
0.030
0.10
UI
f = 5 kHz to 20 MHz
−
0.06
0.50
UI
f = 12 kHz to 20 MHz
−
0.05
0.10
UI
f = 1 to 20 MHz
−
0.045
0.10
UI
µs
PLL characteristics
tacq
Jtol(p-p)
acquisition time
jitter tolerance
(peak-to-peak value)
STM1/OC3 mode; note 11
STM4/OC12 mode; note 11
STM16/OC48 mode; note 11
Jtransfer
Jgen(p-p)
3 dB corner frequency for jitter
transfer
jitter generation
(peak-to-peak value)
STM1/OC3 mode; note 12
STM4/OC12 mode; note 12
STM16/OC48 mode; note 12
2000 Sep 18
15
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
SYMBOL
Jgen(rms)
PARAMETER
jitter generation (RMS value)
OQ2541BHP; OQ2541BU
CONDITIONS
MIN.
TYP.
MAX.
UNIT
STM1/OC3 mode; note 12
f = 500 Hz to 1.3 MHz
−
0.005
−
UI
f = 12 kHz to 1.3 MHz
−
0.0025
−
UI
f = 65 kHz to 1.3 MHz
−
0.002
−
UI
f = 1 kHz to 5 MHz
−
0.006
−
UI
f = 12 kHz to 5 MHz
−
0.004
−
UI
f = 250 kHz to 5 MHz
−
0.004
−
UI
f = 5 kHz to 20 MHz
−
0.008
−
UI
f = 12 kHz to 20 MHz
−
0.007
−
UI
STM4/OC12 mode; note 12
STM16/OC48 mode; note 12
f = 1 to 20 MHz
TDR
transitionless data run
note 13
−
0.0065
−
UI
−
2000
−
bits
Notes
1. Typical power supply voltage for the voltage regulator is −4.5 V (see Fig.6).
2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true
differential excitation).
3. The specified input voltage range is the guaranteed and tested range for proper operation; BER < 1 × 10−10.
4. In DCR mode, an input sensitivity of 7 mV (p-p) for BER < 1 × 10−10 is guaranteed. The typical input sensitivity for
BER < 1 × 10−10 is 2.5 mV (p-p). In bypass mode, full clipping of the output signal occurs at about 25 mV (p-p),
see Fig.15.
5. CML inputs are terminated internally using on-chip resistors of 50 Ω connected to ground.
6. Output voltage range with default reference voltage on pin AREF (floating).
7. Output voltage range with adjustment of voltage on pin AREF (see Section “Output amplitude reference”).
8. Measured with ‘1010’ data pattern, single-ended output signals and rising edges of the signals on
pins COUT to DOUT or pins CLOOP to DLOOP. It should be noted that small deviations of the specified value are
possible if measured differentially.
9. External pull-up resistor of 10 kΩ connected to supply voltage of 3.3 V.
10. LOS assert or de-assert timing and BER level are for indication only. The values are neither production tested nor
guaranteed.
11. Measured in accordance with ITU specification G.958. Measured with demoboard OM5801 for STM16/OC48,
STM4/OC12 and STM1/OC3. See for more information “Application note AN96051”.
12. Measured in accordance with ITU specification G.813 and 10 dB above the system input sensitivity power level.
Measured with demoboard OM5801 for STM16/OC48, STM4/OC12 and STM1/OC3.
13. TDR is bit rate independent.
2000 Sep 18
16
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
handbook, full pagewidth
OQ2541BHP; OQ2541BU
CML INPUT
CML OUTPUT
VI(max)
GND
GND
VO(max)
VIQH
VOQH
VOH
VIH
Vi(p-p)
VIQL
Vo(p-p)
VOQL
VOL
VIO
VIL
VOO
VO(min)
VI(min)
MGK144
Fig.10 Logic level symbol definitions for CML.
handbook, full pagewidth
GND
COUT or
CLOOP
−200 mV
td(D-C)
GND
DOUT or
DLOOP
−200 mV
MGL672
Fig.11 Data-to-clock delay for CML outputs: COUT to DOUT or CLOOP to DLOOP.
2000 Sep 18
17
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
TYPICAL PERFORMANCE CHARACTERISTICS
MGT207
−3.20
VEE
handbook, full pagewidth
(V)
−3.25
−3.30
−3.35
−3.40
−3.45
−3.50
−40
−20
0
20
40
60
80
T (°C)
100
The supply voltage is regulated by the power controller.
Fig.12 Supply voltage as a function of the temperature.
MGT208
0.15
handbook, full pagewidth
IEE
(A)
0.14
0.13
0.12
0.11
0.10
−40
−20
0
20
40
60
Fig.13 Supply current as a function of the temperature.
2000 Sep 18
18
80
T (°C)
100
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT209
300
handbook, full pagewidth
td(D-C)
(ps)
280
260
240
220
200
−40
−20
0
20
40
60
80
T (°C)
100
See Fig.11 for the definition of td(D-C).
Fig.14 Data-to-clock delay time as a function of the temperature.
MGT210
200
handbook, full pagewidth
Vo(p-p)
(mV)
160
120
80
40
0
0
5
10
15
20
25
Fig.15 Output voltage as a function of input voltage in bypass mode.
2000 Sep 18
19
Vi(p-p) (mV)
30
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT211
10
handbook, full pagewidth
J tol(p-p)
(UI)
(1)
1
(2)
10 −1
1
102
10
f (kHz)
103
(1) OQ2541B; (2) ITU STM1.
Fig.16 Jitter tolerance as a function of the jitter frequency in the STM1/OC3 mode (155.52 Mbits/s).
MGT212
5
handbook, full pagewidth
J transfer
(dB)
0
(1)
−5
(2)
−10
−15
−20
−25
1
102
10
f (kHz)
103
(1) ITU STM1; (2) OQ2541B.
Fig.17 Jitter transfer as a function of the jitter frequency in the STM1/OC3 mode (155.52 Mbits/s).
2000 Sep 18
20
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT213
10
handbook, full pagewidth
J tol(p-p)
(UI)
1
(1)
(2)
10 −1
1
102
10
103
f (kHz)
104
(1) OQ2541B; (2) ITU STM4.
Fig.18 Jitter tolerance as a function of the jitter frequency in the STM4/OC12 mode (622.08 Mbits/s).
MGT214
5
handbook, full pagewidth
J transfer
(dB)
0
−5
(1)
−10
(2)
−15
−20
−25
10
102
103
f (kHz)
104
(1) ITU STM4; (2) OQ2541B.
Fig.19 Jitter transfer as a function of the jitter frequency in the STM4/OC12 mode (622.08 Mbits/s).
2000 Sep 18
21
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT216
10
handbook, full pagewidth
J tot(p-p)
(UI)
1
(1)
(2)
10 −1
10
102
103
f (kHz)
104
(1) OQ2541B; (2) ITU STM16.
Fig.20 Jitter tolerance as a function of the jitter frequency in the STM16/OC48 mode (2488.32 Mbits/s).
MGT215
5
handbook, full pagewidth
J transfer
(dB)
0
(1)
−5
(2)
−10
−15
−20
−25
10
102
103
f (kHz)
104
(1) ITU STM16; (2) OQ2541B.
Fig.21 Jitter transfer as a function of the jitter frequency in the STM16/OC48 mode (2488.32 Mbits/s).
2000 Sep 18
22
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT217
handbook, full pagewidth
Measured single ended.
Fig.22 Data and clock output waveforms in the STM4/OC12 mode (622.08 Mbits/s).
MGT218
handbook, full pagewidth
Measured single ended.
Fig.23 Data and clock output waveforms in the STM16/OC48 mode (2488.32 Mbits/s).
2000 Sep 18
23
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT219
handbook, full pagewidth
Measured differentially.
Fig.24 Clock output waveform in the STM4/OC12 mode (622.08 Mbits/s).
MGT220
handbook, full pagewidth
Measured differentially;
differentially. PRBS 223 − 1 pattern.
Fig.25 Data output waveform in the STM4/OC12 mode (622.08 Mbits/s).
2000 Sep 18
24
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT221
handbook, full pagewidth
Measured differentially.
Fig.26 Clock output waveform in the STM16/OC48 mode (2488.32 Mbits/s).
MGT222
handbook, full pagewidth
Measured differentially; PRBS 223 − 1
Fig.27 Data output waveform in the STM16/OC48 mode (2488.32 Mbits/s).
2000 Sep 18
25
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
MGT223
handbook, full pagewidth
Measured differentially; 10101010 pattern.
Fig.28 Data output waveform in the STM16/OC48 mode (2488.32 Mbits/s).
MGT224
handbook, full pagewidth
Measured differentially; bypass mode.
Fig.29 Data output waveform in the STM16/OC48 mode (2488.32 Mbits/s).
2000 Sep 18
26
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
APPLICATION INFORMATION
ALLON
handbook, full pagewidth
ENL
CAPUPQ
180 nF
1
+3.3 V
BYPASS
24
10 kΩ
10
15
39
+3.3 V
180 nF
CAPDOQ
16
10 kΩ
12
DIN
PREAMP
42
33
DINQ
43
34
45
46
OQ2541B
6
7
CREF
19.44 MHz
system clock
LOS
21
3
22
4
CREFQ
DREF19
48
9
27
28
i.c.
5
13, 18, 19,
36, 40
30
25
31
DOUT
DOUTQ
normal
output
COUT
COUTQ
DLOOP
DLOOPQ
loop
output
CLOOP
CLOOPQ
AREF
DOUT1250
DOUT622
DOUT155
37
VEE1 VEE2
GND(1)
LOCK
PC
16
β ≈ 100
100
nF
2Ω
1
kΩ
6.8
Ω
1
kΩ
3.3
nF
1 µF
L1(2)
−4.5 V
MGT225
(1) All pins GND must be connected directly to the PCB ground plane (pins 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47).
(2) L1 = RF choke type Murata BLM21.
Fig.30 Application diagram showing the OQ2541B configured for the STM16/OC48 mode (2488.32 Mbits/s).
2000 Sep 18
27
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
handbook, full pagewidth
OQ2541BHP; OQ2541BU
ALLON
ENL
CAPUPQ
180 nF
1
+3.3 V
BYPASS
24
10 kΩ
10
15
39
+3.3 V
180 nF
CAPDOQ
16
10 kΩ
12
DIN
PREAMP
42
33
DINQ
43
34
45
46
OQ2541B
6
7
CREF
19.44 MHz
system clock
LOS
21
3
22
4
CREFQ
DREF19
48
9
27
28
i.c.
5
13, 18, 19,
36, 40
30
25
31
VEE1
GND(1)
LOCK
DOUT
DOUTQ
normal
output
COUT
COUTQ
DLOOP
DLOOPQ
loop
output
CLOOP
CLOOPQ
AREF
DOUT1250
DOUT622
DOUT155
37
VEE2
PC
16
β ≈ 100
100
nF
2Ω
1
kΩ
6.8
Ω
1
kΩ
3.3
nF
1 µF
L1(2)
−4.5 V
MGT226
(1) All pins GND must be connected directly to the PCB ground plane (pins 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47).
(2) L1 = RF choke type Murata BLM21.
Fig.31 Application diagram showing the OQ2541B configured for the STM4/OC12 mode (622.08 Mbits/s).
2000 Sep 18
28
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
handbook, full pagewidth
OQ2541BHP; OQ2541BU
ALLON
ENL
CAPUPQ
180 nF
1
VCC
BYPASS
24
10
39
LOS
15
LOS
180 nF
10 kΩ
16
CAPDOQ
12
VCC
LOCK
LOCK
10 kΩ
DIN
PREAMP
DINQ
33
42
34
43
45
OQ2541B
46
6
7
CREF
19.44 MHz
system clock
21
3
22
4
CREFQ
DREF19
48
9
27
28
i.c.
5
13, 18, 19,
36, 40
30
25
31
DOUTQ
COUT
normal
unused
=
output
output
COUTQ
DLOOP
DLOOPQ
CLOOP
main
loop
=
output(3)
output
CLOOPQ
AREF
DOUT1250
DOUT622
DOUT155
VCC
37
VEE1 VEE2
GND(1)
DOUT
PC
16
β ≈ 100
100
nF
VCC
2Ω
1
kΩ
8.2
Ω
VCC VCC
1
kΩ
3.3
nF
1 µF
L1(2)
MGT227
(1) All GND pins must be connected directly to VCC on the PCB plane of 5 V (pins 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47).
(2) L1 = RF choke type Murata BLM21.
(3) The loop mode outputs are used as main outputs.
Fig.32 Application diagram showing the OQ2541B configured for the STM16/OC48 mode (2488.32 Mbits/s) with
a positive supply voltage application (VCC = +5 V).
2000 Sep 18
29
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
BONDING PAD LOCATIONS
Table 6
COORDINATES(1)
SYMBOL
Bonding pad locations.
x
COORDINATES(1)
SYMBOL
PAD
PAD
x
y
y
GND
38
+697.5
+1017.5
LOS
39
+542.5
+1017.5
ENL
1
−1017.5
+852.5
i.c.
40
+387.5
+1017.5
GND
2
−1017.5
+697.5
GND
41
+232.5
+1017.5
CLOOP
3
−1017.5
+542.5
DOUT
42
+77.5
+1017.5
CLOOPQ
4
−1017.5
+387.5
DOUTQ
43
−77.5
+1017.5
GND
5
−1017.5
+232.5
GND
44
−232.5
+1017.5
DLOOP
6
−1017.5
+77.5
COUT
45
−387.5
+1017.5
DLOOPQ
7
−1017.5
−77.5
COUTQ
46
−542.5
+1017.5
GND
8
−1017.5
−232.5
GND
47
−697.5
+1017.5
DREF19
9
−1017.5
−387.5
AREF
48
−852.5
+1017.5
BYPASS
10
−1017.5
−542.5
GND
11
−1017.5
−697.5
LOCK
12
−1017.5
−852.5
i.c.
13
−852.5
−1017.5
GND
14
−697.5
−1017.5
CAPUPQ
15
−542.5
−1017.5
CAPDOQ
16
−387.5
−1017.5
GND
17
−232.5
−1017.5
i.c.
18
−77.5
−1017.5
i.c.
19
+77.5
−1017.5
GND
20
+232.5
−1017.5
CREF
21
+387.5
−1017.5
CREFQ
22
+542.5
−1017.5
GND
23
+697.5
−1017.5
ALLON
24
+852.5
−1017.5
VEE1
25
+1017.5
−852.5
GND
26
+1017.5
−697.5
DOUT1250
27
+1017.5
−542.5
DOUT622
28
+1017.5
−387.5
GND
29
+1017.5
−232.5
DOUT155
30
+1017.5
−77.5
VEE2
31
+1017.5
+77.5
GND
32
+1017.5
+232.5
DIN
33
+1017.5
+387.5
DINQ
34
+1017.5
+542.5
GND
35
+1017.5
+697.5
i.c.
36
+1017.5
+852.5
PC
37
+852.5
+1017.5
2000 Sep 18
Note
1. All x and y coordinates represent the position of the
centre of the pad in µm with respect to the centre of the
die (see Fig.33).
30
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
GND
COUTQ
COUT
GND
DOUTQ
DOUT
GND
i.c.
LOS
GND
PC
48
47
46
45
44
43
42
41
40
39
38
37
ENL
1
36
i.c.
GND
2
35
GND
CLOOP
3
34
DINQ
CLOOPQ
4
33
DIN
GND
5
32
GND
DLOOP
6
31
VEE2
DLOOPQ
7
0
30
DOUT155
GND
8
y
29
GND
DREF19
9
28
DOUT622
BYPASS
10
27
DOUT1250
GND
11
26
GND
LOCK
12
25
VEE1
x
0
GND
20
21
22
23
24
ALLON
CAPDOQ
19
GND
CAPUPQ
18
CREFQ
17
CREF
16
GND
15
i.c.
14
i.c.
13
GND
OQ2541BU
i.c.
2.360
mm
AREF
handbook, full pagewidth
OQ2541BHP; OQ2541BU
2.360 mm
MGT228
Fig.33 Bonding pad locations of OQ2541BU.
2000 Sep 18
31
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
Table 7
OQ2541BHP; OQ2541BU
Physical characteristics of bare die
NAME
DESCRIPTION
Glass passivation
0.8 µm silicon nitride on top of 0.9 µm PSG (PhosphoSilicate Glass)
Bonding pad dimension
minimum dimension of exposed metallization is 90 × 90 µm (pad size = 100 × 100 µm)
Metallization
1.8 µm AlCu (1% Cu)
Thickness
380 µm nominal
Size
2.360 × 2.360 mm (5.5696 mm2)
Backing
silicon; electrically connected to VEE potential through substrate contacts
Attach temperature
<440 °C; recommended die attach is glue
Attach time
<15 s
Thermal considerations
To improve heat transfer away from the product, a large area fill is recommended as a die pad. The die should be
mounted on this with a heat conductive glue. All supply and ground pads must be bonded to ensure good electrical
performance; this also improves heat transfer to the die pad or other copper area fills. The more copper leading away
from the die, the better the heat transport. In turn, this copper should be able to lose its heat to the environment through
radiation, natural convection (unforced airflow over the printed-circuit board) or forced cooling.
2000 Sep 18
32
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
pin 1 index
θ
bp
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
2000 Sep 18
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
33
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
SOLDERING
OQ2541BHP; OQ2541BU
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2000 Sep 18
34
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable(2)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The
package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Sep 18
35
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
OQ2541BHP; OQ2541BU
DATA SHEET STATUS
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS (1)
Objective specification
Development
This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification
Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
DEFINITIONS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
BARE DIE DISCLAIMER
All die are tested and are guaranteed to comply with all
data sheet limits up to the point of wafer sawing for a
period of ninety (90) days from the date of Philips' delivery.
If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post
packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in
the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability
for device functionality or performance of the die or
systems after third party sawing, handling, packing or
assembly of the die. It is the responsibility of the customer
to test and qualify their application in which the die is used.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
2000 Sep 18
36
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
NOTES
2000 Sep 18
37
OQ2541BHP; OQ2541BU
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
NOTES
2000 Sep 18
38
OQ2541BHP; OQ2541BU
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE
NOTES
2000 Sep 18
39
OQ2541BHP; OQ2541BU
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Internet: http://www.semiconductors.philips.com
SCA 70
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Printed in The Netherlands
403510/300/01/pp40
Date of release: 2000
Sep 18
Document order number:
9397 750 06952