MPEG-4 Video Decoder LSI TC35274 Preliminary TOSHIBA MPEG-4 Video Decoder LSI TC35274 Tentative Technical Data Sheet MPEG-4 Video Decoder LSI Features U A single-chip MPEG-4 video decoder LSI performs 15frames/sec of MPEG-4 video decoding with QCIF (176x144 pixels) at 30MHz clock frequency. U A 4-Mbit embedded DRAM is integrated to reduce power consumption without performance degradation. U An MPEG-4 video core consists of a 16-bit RISC processor and dedicated hardware accelerators so as to bring programmability, high performance, and P-FBGAxxxx low power consumption. U Firmware program for the RISC is downloaded into the embedded DRAM before starting operation. Other applications, such as H.263, are performed by using appropriate firmware. U General host interface is adopted in order to support various host CPU. • TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. • The products described in this document are subject to foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. • The circuit contained herein is presented only as a guide for the applications, and it is not guaranteed. TOSHIBA Confidential 1/13 Version 0.90 2000-4-27 Preliminary TOSHIBA Confidential 2/13 Version 0.90 MPEG-4 Video Decoder LSI TC35274 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary 1. Functional Specifications 1.1 MPEG-4 Video Decoder ISO MPEG-4 IS SP@L1 decoding is executed with QCIF (176x144 pixels) at 15 frames/sec. YCbCr 4:2:2 8bit digital image data output to a LCD via an external LCD controller. Size conversion and de-blocking filter operatation. 16-bit parallel host interface. 1.2 System Configurations Fig. 1 illustrates a block diagram of TC35274. Before starting operation, an external host CPU downloads a firmware into an embedded DRAM via a host interface. Encoded video bitstream are transferred from a host CPU via a host interface, and stored into the embedded DRAM. Then, an MPEG-4 video core decodes the bitstream. The decoded pictures output to an external LCD controller via an LCD I/F. Host CPU LCDC MPEG-4 Video Host I/F RISC HW HW LCD I/F DMAController Arbiter + DRAM Controller 4Mb Embedded DRAM Fig. 1 Block diagram of TC35274 * In order to run this LSI as an MEPG-4 video decoder LSI, Specified firmware programs have to be obtained in advance. TOSHIBA Confidential 3/13 Version 0.90 2000-4-27 Preliminary MPEG-4 Video Decoder LSI TC35274 2. Terminals 2.1 Pin Assignment TBD 2.2 Pin Allocation TBD 2.3 I/O Pins /RESET TGCLK /STANDBY TSMODE TDBISTEN TDTMB PLLFN PLL Pins PLLDIV TREOUT PLLBP TC35274 PLLAVS MPEG-4 Video Decoder LSI /HCS /HWR Interface TDTCLK 2 PLLAVD Host Test Pins /HRD HADDR 7 HDAT 16 TEST0-3 DISPCLK DISPHSYNC DISPYSYNC DISPBLK Display Interface DISPPIXEL /HWAIT HINT Fig. 2 Pin Map TOSHIBA Confidential 4/13 Version 0.90 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary Table 1. System Control Signals Signal Name /RESET In/Out In Bit Width 1 STANDBY In 1 Description System Reset Input (Low Active). When the LSI is reset, this terminal has to be low for more than 16 clock cycles. When power on, the LSI has to be reset after PLL locked. It takes approximately 100us until the PLL locked. System Standby Input (High Active). Stop clock distribution to the LSI. After standby, system reset is required. “0” : Active. “1” : Standby. Table 2. PLL Control Signals Signal Name PLLFN In/Out In Bit Width 1 PLLDIV[2:0] In 3 PLLAVD PLLAVS In In 1 1 Description Reference Clock Input. It has to be 13.00MHz to 20MHz with +/- 10% duty. System clock frequency select. System Clock = PLLFN * N. “00” : N=1.0. “01” : N=1.5. “10” : N=2.0 “11” : N=2.5. Analog PLL Power(VDD). Analog PLL Ground(VSS). Table 3. Host Interface Signal Name /HCS In/Out In Bit Width 1 /HWR In 1 /HRD In 1 HADDR[6:0] HDAT[15:0] HWAIT In In/Out Out 7 16 1 HINT Out 1 Description Chip enable input ( low active). “0” : Chip select. “1” : Non operation. Write strobe (low active). “0” : Write operation. “1” : Non operation. Read Strobe (low active). “0” : Read operation. “1” : Non operation. Address signal. Data signal. Bus wait signal (low active). “0” : Wait. “1” : Non wait. Interrupt signal (high active). “0” : Non operation. “1” : Interrupt Operation. Table 4 Video Display Interface Signal Name DISPCLK /DISPHSYNC /DISPVSYNC /DISPBLK DISPPIXEL In/Out In In In Out Out Bit Width 1 1 1 1 8 TOSHIBA Confidential 5/13 Version 0.90 Description Clock signal from display. HSYNC signal from display. VSYNC signal form display. Blanking signal to display. Luminance (Y) and chrominance (Cb,Cr) signal output. 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary Table 5 Test Control Signal Signal Name TGCLK TSMODE TDBISTEN TREOUT TDTMB TDTCLK TEST[2:0] In/Out In In In Out In In In Bit Width 1 1 1 1 1 1 3 Description Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Test terminal. Please connect to open. Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Test terminal. Please connect to Vss. Table 6 Power Supply and GND Signal Name Vss Vdds Vdd2 In/Out Bit Width TOSHIBA Confidential 6/13 Version 0.90 Description GND 3.3V Vdd 2.5V Vdd 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary 3. Interface Specifications 3.1 Host Interface An external host CPU can access to TC35274 via a host interface. The access timing of a read, a write, and an interrupt operation are explained below. The host interface has two access modes; handshake access mode and synchronized access mode. 3.1.1 Handshake access mode In this mode, the host CPU has to finish an access operation after a waiting signal (/HWAIT) becomes high. Fig.3 shows the timing diagram of a read operation. A read access starts by asserting both a chip select signal (/HCS) and a read signal (/RD) (timing (a)). At this timing, /HWAIT becomes low. When the read data are ready, /HWAIT becomes high (timing (b)). The host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD (timing (c)). Fig.4 shows the timing diagram of a write operation. A write access starts by asserting both /HCS and a write signal (/WR) (timing (a)). At this timing, /HWAIT becomes low. When TC35274 gets the write data, /HWAIT becomes high (timing (b)). After that, the host CPU finishes the write operation by negating both /HCS and /HWR (timing (c)). (a) (b) (c) TCSS TCSH /HCS TADH TADS HADDR TRR /HRD TWTAD TRDH /HWAIT TWTID TDTVD TDTRS TDTID HDAT TDTOD Fig. 3 Read Operation in handshake mode TOSHIBA Confidential 7/13 Version 0.90 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary (a) (b) (c) TCSS TCSH /HCS TADH TADS HADDR TRR /HWR TWTAD TRDH /HWAIT TWTID TDTID HDAT TDTWS Fig. 4 Write Operation in handshake mode 3.1.2 Synchronized access mode In this mode, a host CPU accomplishs an access to TC35274 in the specified period without a handshake. However, if the host CPU accesses to the embedded DRAM in TC35274, it has to check whether the next access is available or not by checking a status register at every 8 accesses. Fig.5 shows the timing diagram of a read operation. A read access starts by asserting both a chip select signal (/HCS) and a read signal (/RD) (timing (a)). After the specified cycles indicated as Tacs, the host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD (timing (b)). Fig.6 shows the timing diagram of a write operation. A write access starts by asserting both /HCS and a write signal (/WR) (timing (a)). After the specified cycles, the host CPU finishes the write operation by negating both /HCS and /HWR (timing (b)). TOSHIBA Confidential 8/13 Version 0.90 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary (a) (b) TCSS TCSH /HCS TADH TADS HADDR TRR TACS /HRD TWTAD TDTVD TRDH TDTRS TDTID HDAT TDTOD Fig.5 Read Operation in Synchronization mode (a) (c) TCSS TCSH /HCS TADH TADS HADDR TACS TRR /HWR TWTAD TDTID HDAT TDTWS Fig.6 Write Operation in Synchronization Mode TOSHIBA Confidential 9/13 Version 0.90 2000-4-27 Preliminary 3.1.3 MPEG-4 Video Decoder LSI TC35274 Interrupt An interrupt to the external host CPU is performed as follows. (a) HINT Active When an interrupt is requested by TC35274, HINT becomes high (timing (a)). (b) Clear HINT The host CPU detects the interrupt request by HINT. The CPU also detects the interrupt causes by reading an interrupt status register in the host interface of TC35274. When the CPU reads the register at the timing (b), The CPU detects the interrupt causes occurring during the timing (a) and (b). HINT is cleared when the CPU reads the interrupt status register. (c) Multiple Interrupt Even if another interrupt is requested during the timing (b) and (c), The assertion of HINT is suspended to the timing (c). (a) (b) (c) T RRD HINT /HCS HADDR /HRD T ACS /HW AIT HDAT Fig. 7 Interrupt Operation TOSHIBA Confidential 10/13 Version 0.90 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary Table 7 Host Interface Timing Parameters TCSS TCSH TADS TADH TWTAD TWTID TACS TACID TDTOD TDTVD TDTRS TDTwS tDTID TRDH TRR * TSYSCLK Description Setup time of HCS. Hold time of HCS. Setup time of Address. Hold time of Address. Delay time of /HWAIT for /HRD or /HWR. Access time in handshake access mode.* Access time in synchronized access mode. Delay time of HACK Delay time of Data. Data hold time. Read data setup time. Write data setup time. Data hold time. Hold time of /HRD. Recovery time of /HRD or /HWR Min 0.0 0.0 0.0 0.0 Max TSYSCLK*3 TSYSCLK*100 15.0 TSYSCLK*3 TSYSCLK*2 15.0 15.0 TSYSCLK*99 TSYSCLK*1 0.0 15.0 0.0 TSYSCLK*3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns means the cycle time of TC35274 internal system clock. * Access to internal DRAM requires Tsysclk*100 (ns) in a worst case. As for the others accesses, it takes 3 cycles of the internal system clock. TOSHIBA Confidential 11/13 Version 0.90 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary 3.4 Video Display Interface The video display interface outputs image data with YCbCr 4:2:2 8-bit digital format. An external LCD controller is required to connect LCD. /DISPVSYN 1 2 3 1 2 3 /DISPHSYN /DISPBLNK Internal Signal L2VBUSY Vblank=3 VSize=4 VBlank=3 VSize=4 /DISPHSYN DISPCLK Hblank=4 /DISPBLNK Hblank=4 HSize=2 Cb0 Y0 Cr0 Y1 DISPPIXEL[7:0] Cb0 Y0 Cr0Y1 Fig. 8 Timing Diagram of Display Interface. TCYCLE DSPCLK TSETUP THOLD DSPHSYN DSPVSYN TDELAY DSPBLK Cb0 DSPPXL Y0 Cr0 Y1 Y n-1 Fig. 9 Detail Timing Diagram of Display Interface. TOSHIBA Confidential 12/13 Version 0.90 2000-4-27 MPEG-4 Video Decoder LSI TC35274 Preliminary Table 8 Display Interface Timing Parameter TCYCLE TSETUP THOLD TDELAY * Description Cycle time of DISPCLK Setup time of DISPHSYN and DISPVSYN Hold time DISPHSYN and DISPVSYN Delay time of DISPBLK and DISPPXL Min Max Unit (TSYSCLK*3)+15 ns ns ns ns 100 2 2 When system clock is 40MHz, DSPCLK has to be less than 10MHz. 4. Electric Specifications 4.1 TBD. TOSHIBA Confidential 13/13 Version 0.90 2000-4-27