INTEGRATED CIRCUITS DATA SHEET TDA9875 Digital TV Sound Processor (DTVSP) Preliminary specification Supersedes data of 1997 Mar 20 File under Integrated Circuits, IC02 1998 Feb 13 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) CONTENTS 1 FEATURES 1.1 1.2 1.3 Demodulator and decoder section DSP section Analog audio section 2 GENERAL DESCRIPTION 2.1 Supported standards 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.2 6.3 Description of the demodulator and decoder section Description of the DSP Description of the analog audio section 7 LIMITING VALUES 8 THERMAL CHARACTERISTICS 9 CHARACTERISTICS 10 I2C-BUS CONTROL 10.1 10.2 10.3 10.4 10.5 Introduction Power-up state Slave receiver mode Slave transmitter mode Expert mode 11 I2S-BUS DESCRIPTION 12 EXTERNAL COMPONENTS 13 PACKAGE OUTLINE 14 SOLDERING 14.1 14.2 14.3 Introduction Soldering by dipping or by wave Repairing soldered joints 15 DEFINITIONS 16 LIFE SUPPORT APPLICATIONS 17 PURCHASE OF PHILIPS I2C COMPONENTS 1998 Feb 13 2 TDA9875 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 1 1.1 TDA9875 FEATURES Demodulator and decoder section • Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources • SIF AGC with 21 dB control range • SIF 8-bit Analog-to-Digital Converter (ADC) • Standby mode with functionality for SCART copies • DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation • Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth 15 kHz • NICAM decoding (B/G, I and L standard) • Dual audio ADC from analog inputs to DSP • Two-carrier multistandard FM demodulation (B/G, D/K and M standard) • Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound • Two dual audio Digital-to-Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension. • Optional AM demodulation for system L, simultaneously with NICAM 2 • Programmable identification (B/G, D/K and M standard) and different identification times. 1.2 The TDA9875 is a single-chip Digital TV Sound Processor (DTVSP) for analog and digital multi-channel sound systems in TV sets and satellite receivers. DSP section 2.1 • Digital crossbar switch for all digital signal sources and destinations • Plop-free volume control • Automatic Volume Level (AVL) control • Adaptive de-emphasis for satellite • Programmable beeper M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. • Monitor selection for FM/AM DC values and signals, with peak detection option • I2S-bus interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and mute. The AM sound of L/L’ standard is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the mono audio input of the TDA9875. A second possibility is to use the internal AM demodulator stage, however this gives limited performance. Analog audio section • Analog crossbar switch with inputs for mono and stereo (also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output Korea has a stereo sound system similar to Europe and is supported by the TDA9875. Differences include deviation, modulation contents and identification. It is based on M standard. • User defined full-level/−3 dB scaling for SCART outputs • Output selection of mono, stereo, dual A/B, dual A or dual B An overview of the supported standards and sound systems and their key parameters is given in Table 1. • 20 kHz bandwidth for SCART-to-SCART copies 1998 Feb 13 Supported standards The multistandard/multi-stereo capability of the TDA9875 is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. • Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft-mute 1.3 GENERAL DESCRIPTION 3 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 2.1.1 TDA9875 ANALOG 2-CARRIER SYSTEMS Table 1 Frequency modulation STANDARD SOUND SYSTEM CARRIER FREQUENCY (MHz) FM DEVIATION (kHz) NOM./MAX./OVER mono 4.5 15/25/50 M MODULATION SC1 mono M A2+ 4.5/4.724 15/25/50 1⁄ B/G A2 5.5/5.742 27/50/80 1⁄ I mono 6.0 27/50/80 D/K A2 6.5/6.742 27/50/80 1⁄ D/K A2* 6.5/6.26 27/50/80 1⁄ Table 2 + R) 1⁄ SC2 BANDWIDTH/ DE-EMPHASIS (kHz/µs) − 15/75 2(L − R) 2(L 2(L + R) R 15/75 (Korea) 15/50 mono − 15/50 2(L + R) R 15/50 2(L + R) R 15/50 Identification for A2 systems PARAMETER A2/A2* A2+ (KOREA) Pilot frequency 54.6875 kHz = 3.5 × line frequency 55.0699 kHz = 3.5 × line frequency Stereo identification frequency pilot frequency 117.5 Hz = --------------------------------------133 pilot frequency 149.9 Hz = --------------------------------------105 Dual identification frequency pilot frequency 274.1 Hz = --------------------------------------57 pilot frequency 276.0 Hz = --------------------------------------57 AM modulation depth 50% 50% 2.1.2 2-CARRIER SYSTEMS WITH NICAM Table 3 NICAM SC1 MODULATION STANDARD FREQUENCY TYPE (MHz) SC2 ROLL-OFF NICAM (MHz) DE-EMPHASIS (%) CODING DEVIATION NICAM INDEX (%) (kHz) NOM/MAX. NOM./MAX. B/G 5.5 FM − 27/50 5.85 J17 40 note 1 I 6.0 FM − 27/50 6.552 J17 100 note 1 D/K 6.5 FM − 27/50 5.85 J17 40 not yet defined L 6.5 AM 54/100 − 5.85 J17 40 note 1 Note 1. See “EBU specification” or equivalent specification. 1998 Feb 13 4 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 2.1.3 TDA9875 SATELLITE SYSTEMS An important specification for satellite TV reception is the “Astra specification”. The TDA9875 is suited for the reception of Astra and other satellite signals. Table 4 FM satellite sound CARRIER TYPE CARRIER FREQUENCY (MHz) MODULATION INDEX MAXIMUM FM DEVIATION (kHz) MODULATION BANDWIDTH/ DE-EMPHASIS (kHz/µs) Main 6.50(1) 0.26 85 mono 15/50(1) Sub 7.02/7.20 0.15 50 m/st/d(2) 15/adaptive(3) 15/adaptive(3) Sub 7.38/7.56 0.15 50 m/st/d(2) Sub 7.74/7.92 0.15 50 m/st/d(2) 15/adaptive(3) Sub 8.10/8.28 0.15 50 m/st/d(2) 15/adaptive(3) Notes 1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasis of 60 µs, or in accordance with J17, is available. 2. m/st/d = mono or stereo or dual language sound. 3. Adaptive de-emphasis = compatible to transmitter specification. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9875 1998 Feb 13 SDIP64 DESCRIPTION plastic shrink dual in-line package; 64 leads (750 mil) 5 VERSION SOT274-1 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 4 TDA9875 BLOCK DIAGRAM SIF2 handbook, full pagewidth SIF1 10 P1 P2 ADDR1 ADDR2 SCL SDA 12 9 7 20 3 13 SUPPLY SOUND IF (SIF) INPUT SWITCH AGC, ADC I2C-BUS INTERFACE 4 6 11 8 5 IDENTIFICATION FM (AM) DEMODULATION NICAM DEMODULATION TIMING DETECTION DAC 19 2 1 33 XTALI XTALO SYSCLK 34 18 17 CLOCK 36 NICAM DECODER DEMATRIX 21 37 31 32 ANALOG CROSSBAR SWITCH 29 47 48 PEAK DETECTION 51 LEVEL ADJUST LEVEL ADJUST 52 63 62 SDI1 SDI2 SDO1 SDO2 SCK WS VDDD1 26 25 24 22 42 41 I2C-BUS AUDIO INTERFACE ADC(2) 45 44 23 14 VSSD2 49 DIGITAL SUPPLY DAC(2) 54 55 16 38 43 35 TDA9875 SUPPLY DAC AUDIO PROCESSING 46 39 40 28 30 59 TEST DAC(2) DAC(2) SUPPLY DAC REFERENCE SUPPLY OPERATIONAL AMPLIFIERS 61 60 58 56 53 50 57 MGK107 MOL MOR AUXOL AUXOR Fig.1 Block diagram. 1998 Feb 13 Iref Vtune NICAM PCLK SCIR1 SCIL1 SCIR2 SCIL2 EXTIR EXTIL MONOIN SCOR1 SCOL1 SCOR2 SCOL2 LOR LOL CAPL2 CAPL1 CAPR1 CAPR2 15 64 TEST2 Vref1 DIGITAL SELECT VSSD1 TEST1 VSSA1 27 VDDD2 CRESET VDDA1 6 PCAPR PCAPL VDDA2 VSSA2 VSSG Vref2 Vref(p) Vref(n) VDDA3 VSSA3 Vref3 VSSA4 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 5 TDA9875 PINNING SYMBOL PIN I/O DESCRIPTION PCLK 1 O NICAM clock output at 728 kHz NICAM 2 O serial NICAM data output at 728 kHz ADDR1 3 I first I2C-bus slave address modifier SCL 4 I I2C-bus clock SDA 5 I/O I2C-bus data VSSA1 6 supply supply ground 1; analog front-end circuitry VDDA1 7 supply analog supply voltage 1; analog front-end circuitry Iref 8 − P1 9 I/O SIF2 10 I sound IF input 2 resistor for reference current generator; analog front-end circuitry first general purpose I/O pin Vref1 11 − reference voltage; analog front-end circuitry SIF1 12 I sound IF input 1 ADDR2 13 I second I2C-bus slave address modifier VSSD1 14 supply supply ground 1; digital circuitry VDDD1 15 supply digital supply voltage 1; digital circuitry CRESET 16 − capacitor for power-on reset XTALO 17 O crystal oscillator output XTALI 18 I crystal oscillator input Vtune 19 O tuning voltage output for crystal oscillator P2 20 I/O second general purpose I/O pin SYSCLK 21 O system clock output SCK 22 I/O I2S-bus clock WS 23 I/O I2S-bus word select SDO2 24 O I2S-bus data output 2 SDO1 25 O I2S-bus data output 1 SDI2 26 I I2S-bus data input 2 SDI1 27 I I2S-bus data input 1 TEST1 28 I first test pin; connected to VSSD1 for normal operation MONOIN 29 I audio mono input TEST2 30 I second test pin; connected to VSSD1 for normal operation EXTIR 31 I external audio input right channel EXTIL 32 I external audio input left channel SCIR1 33 I SCART 1 input right channel SCIL1 34 I SCART 1 input left channel VSSG 35 − ground guards; audio analog-to-digital converter circuitry SCIR2 36 I SCART 2 input right channel SCIL2 37 I SCART 2 input left channel VDDA2 38 supply Vref(p) 39 − positive reference voltage; audio analog-to-digital converter circuitry Vref(n) 40 − reference voltage ground; audio analog-to-digital converter circuitry 1998 Feb 13 analog supply voltage 2; audio analog-to-digital converter circuitry 7 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) SYMBOL CAPL1 PIN I/O 41 − TDA9875 DESCRIPTION filter capacitor pin 1; audio analog-to-digital converter, left channel CAPL2 42 − VSSA2 43 supply CAPR2 44 − filter capacitor pin 2; audio analog-to-digital converter, right channel CAPR1 45 − filter capacitor pin 1; audio analog-to-digital converter, right channel Vref2 46 − reference voltage; audio analog-to-digital converter circuitry SCOR1 47 O SCART 1 output right channel SCOL1 48 O SCART 1 output left channel VSSD2 49 supply supply ground 2; digital circuitry VSSA4 50 supply supply ground 4; audio operational amplifier circuitry SCOR2 51 O SCART 2 output right channel SCOL2 52 O SCART 2 output left channel Vref3 53 − reference voltage; audio digital-to-analog converter and operational amplifier circuitry PCAPR 54 − post-filter capacitor pin right channel, audio digital-to-analog converter PCAPL 55 − post-filter capacitor pin left channel, audio digital-to-analog converter VSSA3 56 supply AUXOR 57 O headphone (Auxiliary) output right channel AUXOL 58 O headphone (Auxiliary) output left channel VDDA3 59 supply MOR 60 O filter capacitor pin 2; audio analog-to-digital converter, left channel supply ground 2; audio analog-to-digital converter circuitry supply ground 3; audio digital-to-analog converter circuitry analog supply voltage 3; audio digital-to-analog converter loudspeaker (Main) output right channel MOL 61 O loudspeaker (Main) output left channel LOL 62 O line output left channel LOR 63 O line output right channel VDDD2 64 supply 1998 Feb 13 digital supply voltage 2; digital circuitry 8 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 handbook, halfpage PCLK 1 64 VDDD2 NICAM 2 63 LOR ADDR1 3 62 LOL SCL 4 61 MOL SDA 5 60 MOR VSSA1 6 59 VDDA3 VDDA1 7 58 AUXOL Iref 8 57 AUXOR P1 9 56 VSSA3 SIF2 10 55 PCAPL Vref1 11 54 PCAPR SIF1 12 53 Vref3 ADDR2 13 52 SCOL2 VSSD1 14 51 SCOR2 VDDD1 15 50 VSSA4 CRESET 16 XTALO 17 49 VSSD2 TDA9875 48 SCOL1 XTALI 18 47 SCOR1 Vtune 19 46 Vref2 P2 20 45 CAPR1 SYSCLK 21 44 CAPR2 SCK 22 43 VSSA2 WS 23 42 CAPL2 SDO2 24 41 CAPL1 SDO1 25 40 Vref(n) SDI2 26 39 Vref(p) SDI1 27 38 VDDA2 TEST1 28 37 SCIL2 MONOIN 29 36 SCIR2 TEST2 30 35 VSSG EXTIR 31 34 SCIL1 EXTIL 32 33 SCIR1 MGK106 Fig.2 Pin configuration. 1998 Feb 13 9 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 6 6.1.5 FUNCTIONAL DESCRIPTION 6.1 6.1.1 SIF INPUT 6.1.6 AGC A timing loop controls the frequency of the crystal oscillator to lock the sampling rate to the symbol timing of the NICAM data. The polarity of the control signal is selectable to support applications in which external circuitry is used to boost the tuning voltage of the oscillator. 6.1.7 The AGC can be controlled via the I2C-bus. Details can be found in the I2C-bus register definitions (see Chapter 10). MIXER The status of the NICAM decoder can be read out from the NICAM status register by the user (see the I2C-bus register description in Section 10.4.2). The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to the sound conveyed by the NICAM channel. The error byte contains the number of sound sample errors, resulting from parity checking, that occurred in the past 128 ms period. The Bit Error Rate (BER) can be calculated using the following equation; –5 bit errors BER = ----------------------- ≈ error byte × 1.74 × 10 total bits FM AND AM DEMODULATION An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported. 1998 Feb 13 NICAM DECODER The device performs all decoding functions in accordance with the “EBU NICAM 728 specification”. After locking to the frame alignment word, the data is descrambled by applying the defined pseudo-random binary sequence; the device will then synchronize to the periodic frame flag bit C0. The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus. When receiving NICAM programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency loop. 6.1.4 NICAM DEMODULATION The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock signal onto the NICAM decoder and, for evaluation purposes, to PCLK (pin 1) and NICAM (pin 2). The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen from Table 12 (subaddress 0). 6.1.3 FM IDENTIFICATION The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. Description of the demodulator and decoder section Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. 6.1.2 TDA9875 10 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 6.1.8 When the AM sound in NICAM L systems is demodulated in the 1st sound IF and the audio signal connected to the mono input of the TDA9875, the controlling microcontroller must implement the switching from NICAM reception to mono input, if auto-muting is desired. NICAM AUTO-MUTE This function is enabled by setting bit AMUTE LOW subaddress 14 (see Section 10.3.11). Upper and lower error limits may be defined by writing appropriate values to two registers in the I2C-bus section (subaddresses 16 and 17; see Sections 10.3.13 and 10.3.14). When the number of errors in a 128 ms period exceeds the upper error limit the auto-mute function will switch the output sound from NICAM to whatever sound is on the first sound carrier (FM or AM). When the error count is smaller than the lower error limit the NICAM sound is restored. 6.1.9 CRYSTAL OSCILLATOR A circuit diagram of the external components of the voltage-controlled crystal oscillator is illustrated in Fig.8 (see Chapter 12). 6.1.10 The auto-mute function can be disabled by setting bit AMUTE HIGH. In this condition clicks become audible when the error count increases; the user will hear a signal of degrading quality. TEST PINS Both test pins are active HIGH, in normal operation of the device they are wired to VSSD1. Test functions are for manufacturing tests only and are not available to customers. Without external circuitry these pads are pulled down to LOW level with internal resistors. A decision to enable/disable the auto-muting is taken by the microcontroller based on an interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any additional strategy implemented by the set maker in the microcontroller software. 1998 Feb 13 TDA9875 11 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... DC FILTER 2 2 2 MATRIX AUTOMATIC VOLUME LEVEL MATRIX VOLUME SOFT-MUTE BASS/TREBLE BEEPER 4 LEVEL ADJUST I2S1 2 2 LEVEL ADJUST I2S2 2 12 2 ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS LEVEL ADJUST AND MUTE 2 LEVEL ADJUST DC FILTER MATRIX 2 2 2 LS HP I2S1 8 FIXED DE-EMPHASIS FM 2 LEVEL ADJUST AND MUTE 2 LEVEL ADJUST NICAM 6 DIGITAL CROSSBAR SELECT SPATIAL PSEUDO VOLUME BASS/TREBLE BASS BOOST CONTOUR SOFT-MUTE BEEPER MATRIX 2 Philips Semiconductors 2 2 Digital TV Sound Processor (DTVSP) from ADC Description of the DSP LEVEL ADJUST 2 6.2 dbook, full pagewidth 1998 Feb 13 2 I2S2 10 LEVEL ADJUST 2 MATRIX MATRIX 2 DAC 12 2 4 16 1 I2C-bus MGK108 Preliminary specification TDA9875 Fig.3 DSP data flow diagram. MONITOR SELECT PEAK DETECTION Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 6.2.1 6.2.6 LEVEL SCALING All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range of ±15 dB. It is recommended to scale all input channels to be 15 dB below full-scale (−15 dB full-scale) under nominal conditions. 6.2.2 There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. The Automatic Volume Level (AVL) function provides a constant output level of −23 dB full-scale for input levels between 0 dBFS and −29 dB full-scale. There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 seconds. NICAM PATH FM (AM) PATH Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. A high-pass filter suppresses DC offsets from the FM demodulator due to carrier frequency offsets and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. Volume is controlled individually for each channel ranging from +24 dB to −83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). The de-emphasis function offers fixed settings for the supported standards (50 µs, 60 µs, 75 µs and J17). An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of 1⁄2(L + R) and R to L and R signals, of 1⁄2(L + R) and 1⁄2(L − R) to L and R signals or of channel 1 and channel 2 to L and R signals. 6.2.4 Balance can be realized by independent control of the left and right channel volume settings. NICAM AUTO-MUTE Contour is adjustable between 0 dB and +18 dB with 1 dB resolution. If NICAM is received and the signal quality becomes poor, the digital crossbar switch switches automatically to FM and switches the matrix to channel 1. The automatic switching between NICAM and channel 1 (FM or AM) reception depends on the NICAM bit error rate. The auto-mute function can be disabled via the I2C-bus. 6.2.5 Bass is adjustable between +15 dB and −12 dB with 1 dB resolution and treble is adjustable between ±12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dBs (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). MONITOR This function provides data words from a number of locations of the signal processing paths to the I2C-bus interface (2 data bytes). Signal sources include the FM demodulator outputs, most inputs to the digital crossbar switch and the inputs to the loudspeaker channel of the ADC. Source selection and data read-out is performed via the I2C-bus. Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full-scale between 0 dB and −93 dB with a 3 dB step resolution. The beeper is not effected by mute. Optionally, the peak value can be measured instead of simply taking samples. The internally stored peak value is reset to zero when the data is read via the I2C-bus. The monitor function may be used, for example, for signal level measurements or carrier detection. 1998 Feb 13 LOUDSPEAKER (MAIN) CHANNEL The matrix provides the following functions; forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. The NICAM path has a switchable J17 de-emphasis. 6.2.3 TDA9875 13 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) One example of how the feature interface can be used in a TV set is to connect an external Dolby Surround Pro Logic DSP, such as the SAA7710, to the I2S-bus ports. Outputs must be enabled and a suitable master clock signal for the DSP can be taken from pin SYSCLK. A stereo signal from any source will be output on one of the I2S-bus serial data outputs and the four processed signal channels will be entered at both I2S-bus serial data inputs. Left and right could then be output to the power amplifiers via the Main channel, centre and surround via the Auxiliary channel. Soft-mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine masking. 6.2.7 TDA9875 HEADPHONE (AUXILIARY) CHANNEL The matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to −83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). 6.2.9 CHANNEL FROM THE AUDIO ANALOG-TO-DIGITAL CONVERTER The signal level at the output of the ADC can be adjusted in a range of ±15 dB with a 1 dB step resolution. The audio ADC itself is scaled to a gain of −6 dB. Balance can be realized by independent control of the left and right channel volume settings. 6.2.10 CHANNEL TO THE ANALOG CROSSBAR PATH Bass is adjustable between +15 dB and −12 dB with 1 dB resolution and treble is adjustable between ±12 dB with 1 dB resolution. Level adjust with control positions 0 dB, +3 dB, +6 dB and +9 dB. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). 6.2.11 Input channels to the crossbar switch are from the audio ADC, I2S1, I2S2, FM path, NICAM path and from the loudspeaker channel path after matrix and AVL. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full-scale between 0 dB and −93 dB with a 3 dB step resolution. The beeper is not effected by mute. The I2S1 and I2S2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals. Output channels comprise loudspeaker, headphone, I2S1, I2S2 and the audio DACs for line output and SCART. 6.2.12 FEATURE INTERFACE The feature interface comprises two I2S-bus input/output ports and a system clock output. Each I2S-bus port is equipped with level adjust facilities that can change the signal level in a ±15 dB range in 1 dB steps. Outputs can be disabled to improve EMC performance. Sending illegal data patterns via the I2C-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions. The I2S-bus output matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2. 1998 Feb 13 GENERAL There are a number of functions that can provide signal gain, e.g. volume, bass and treble control. Great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full-scale (−15 dB full-scale). This means that a volume setting of, say, +15 dB would just produce a full-scale output signal and not cause clipping, if the signal level is nominal. Soft-mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine masking. 6.2.8 DIGITAL CROSSBAR SWITCH (SEE Fig.6) 14 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 6.2.13 TDA9875 EXPERT MODE The TDA9875 provides a special expert mode that gives direct write access to the internal Coefficient RAM (CRAM) of the DSP. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. However, this mode must be used with great care. More information on the functions of this device, such as filter structures, the number of coefficients per function, their default values, memory addresses, etc., can be made available on request. 6.2.14 DSP CHARACTERISTICS Table 5 DSP characteristics FUNCTION Bass control for loudspeaker and headphone output Treble control for loudspeaker and headphone output EXPERT MODE yes yes Contour for loudspeaker output yes Bass boost for loudspeaker output yes control range −12 to +15 dB step resolution 1 dB step resolution at frequency 40 Hz control range −12 to +12 dB step resolution 1 dB step resolution at frequency 14 kHz control range 0 to +18 dB step resolution 1 dB step resolution at frequency 40 Hz control range 0 to +20 dB step resolution 2 dB step resolution at frequency 20 Hz corner frequency 350 Hz −83 to +24 dB 1 dB mute position at step 10101100 processing time 32 ms yes anti-phase crosstalk positions 30, 40 and 52 % yes 90 degree phase shift at frequency 150, 200 and 300 Hz Soft-mute for loudspeaker and headphone output no Spatial effects Pseudo stereo yes AVL no 1998 Feb 13 UNIT control range no General VALUE step resolution Volume control for each separate channel in loudspeaker and headphone output Beeper additional to the signal in the loudspeaker and headphone channel PARAMETER no beep frequencies see Section 10.3.38 control range 0 to −93 dB step resolution 3 dB mute position at step 00100000 step width quasi continuously AVL output level for an input level −23 between 0 dB and −29 dB (full-scale) dB attack time 10 ms decay time constant 2, 4 and 8 s −3 dB lower corner frequency of DSP 10 Hz −1 dB bandwidth of DSP kHz 15 14.5 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) EXPERT MODE FUNCTION Level adjust I2S1 and I2S2 inputs yes Level adjust I2S1 and I2S2 outputs yes Level adjust analog crossbar path no Level adjust audio ADC outputs yes Level adjust NICAM path yes Level adjust FM path 6.3 yes TDA9875 PARAMETER VALUE UNIT −15 to +15 control range dB step resolution 1 dB control range −15 to +15 dB step resolution 1 dB mute position at step 00010000 control positions 0, 3, 6 and 9 dB control range +15 to −15 dB step resolution 1 dB control range +15 to −15 dB step resolution 1 dB control range +15 to −15 dB step resolution 1 dB Description of the analog audio section handbook, full pagewidth SCART 1 2 −3 dB 2 2 2 SCART 2 external 2 −3 dB 2 2 ANALOG CROSSBAR SWITCH 2 ANALOG MATRIX 2 ANALOG MATRIX 2 ANALOG MATRIX 2 2 D 2 FM 3 dB 2 0 dB 3 dB 2 0 dB SCART 1 SCART 2 Line output 2 A D A NICAM 2 0 dB mono 2 3 dB 2 2 I2S1 2 I2S2 2 I2S1 2 I2S2 2 DSP AND DIGITAL CROSSBAR SWITCH 2 2 D A 2 2 D A Main Auxiliary MGK109 Fig.4 Block diagram for the audio section. 1998 Feb 13 16 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 6.3.1 ANALOG CROSSBAR SWITCH AND ANALOG MATRIX (see also Fig.6) 6.3.2 The input attenuator is realized by an external series resistor in combination with the input impedance, both of which form a voltage divider. With this voltage divider the maximum SCART signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. If it is known for certain applications that the input signal level is always below 1.4 V (RMS), the SCART inputs can be used without external resistors. The basic signal routing philosophy of the TDA9875 is that each switch handles two signal channels at the same time, e.g. left and right, language A and B, directly at the source. Each source selector switch is followed by an analog matrix to perform further selection tasks, such as putting a signal from one input channel, say language A, to both output channels or for swapping left and right channels. The analog matrix provides the functions given in Table 6 (see also Fig.5). 6.3.3 MATRIX OUTPUT MODE RIGHT OUTPUT 1 left input right input 2 right input left input 3 left input left input 4 right input right input handbook, halfpage left input right input ANALOG MATRIX EXTERNAL AND MONO INPUTS The 3 dB input attenuators are not required for the external and mono inputs, because those signal levels are under control of the TV designer. The maximum allowed input level is 1.4 V (RMS). By adding external series resistors, the external inputs can be used as an additional SCART input. Analog matrix functions LEFT OUTPUT SCART INPUTS The SCART specification allows for a signal level of up to 2 V (RMS). Because of signal handling limitations, due to the 5 V supply voltage of the TDA9875, it is necessary to have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a −3 dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4 V input), there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. There are a number of analog input and output ports with the TDA9875. Analog source selector switches are employed to provide the desired analog signal routing capability. The analog signal routing is performed by the analog crossbar switch section. A dual audio ADC provides the connection to the DSP section and a dual audio DAC provides the connection from the DSP section to the analog crossbar switch. The digital signal routing is performed by a digital crossbar switch. Table 6 TDA9875 6.3.4 SCART OUTPUTS The SCART outputs employ amplifiers with two gain settings. The gain can be set to +3 dB or to 0 dB via the I2C-bus. The +3 dB position is needed to compensate for the 3 dB attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be preferred [under the condition of 1.4 V (RMS) maximum input level]. The 0 dB position is needed, for example, for an external-to-SCART copy with 0 dB gain. left output right output MGK110 6.3.5 Fig.5 Analog matrix. The line output can provide an unprocessed copy of the audio signal in the loudspeaker channels. This can be either an external signal that comes from the dual audio ADC, or a signal from an internal digital audio source that comes from the dual audio DAC. The line output employs amplifiers with two gain settings. The +3 dB position is needed to compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for example, for non-attenuated external or internal digital signals (see Section 6.3.4). All switches and matrices are controlled via the I2C-bus. There is one restriction for switching signals at inputs and outputs for SCART 1 and SCART 2. At these ports, an input signal cannot be copied to its own output, i.e. it is not possible to make a copy from SCART 1 input to SCART 1 output. 1998 Feb 13 LINE OUTPUT 17 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 6.3.6 LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS 6.3.9 DUAL AUDIO DAC Unused internal registers may lose their information in standby mode. Therefore, the device needs to be initialized on returning to normal operation. This can be accomplished in the same way as after a power-on reset. The TDA9875 contains three dual audio DACs, one for the connection from the DSP to the analog crossbar switch section and two for the loudspeaker and headphone outputs. Each of the three dual low-noise high-dynamic range DACs consists of two 15-bit DACs with current outputs, followed by a buffer operational amplifier. The audio DACs operate with four-fold oversampling and noise shaping. 6.3.8 DUAL AUDIO ADC There is one dual audio ADC in the TDA9875 for the connection of the analog crossbar switch section to the DSP. The dual audio ADC consists of two bitstream 3rd-order sigma-delta audio ADCs and a high-order decimation filter. 1998 Feb 13 STANDBY MODE The standby mode (subaddress 1, bit 5) disables most functions and reduces power dissipation. The analog crossbar switch and the SCART section remains operational and can be controlled by the I2C-bus to support copying of analog signals from SCART 1 to SCART 2 and vice versa. Signals from any audio source can be applied to the loudspeaker and to the headphone output channels via the digital crossbar switch and the DSP. 6.3.7 TDA9875 18 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SW5 DIGITAL MATRIX SCART 2 SW4 ADC AUTOMATIC VOLUME LEVEL SW6 DIGITAL MATRIX SW7 DIGITAL MATRIX mono 19 part part HEADPHONE CHANNEL PROCESSING DAC Main Auxiliary I2S1 LEVEL ADJUST I2S2 FM/AM DEMODULATOR ADAPTIVE DE-EMPHASIS FIXED DE-EMPHASIS STEREO DECODER LEVEL ADJUST SW8 NICAM DAC LEVEL ADJUST external FM/AM LOUDSPEAKER CHANNEL PROCESSING NICAM DECODER DE-EMPHASIS DIGITAL MATRIX LEVEL ADJUST SW3 LEVEL ADJUST SW9 DIGITAL MATRIX LEVEL ADJUST ANALOG MATRIX BUFFER 0/+3 dB ANALOG MATRIX BUFFER 0/+3 dB Line MGK111 TDA9875 Fig.6 Audio signal flow diagram. SCART 2 Preliminary specification LEVEL ADJUST SCART 1 DAC SW2 I2S2 BUFFER 0/+3 dB LEVEL ADJUST SW1 I2S1 ANALOG MATRIX Philips Semiconductors Digital TV Sound Processor (DTVSP) andbook, full pagewidth 1998 Feb 13 SCART 1 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD DC supply voltage −0.5 +6.5 V ∆VDD voltage differences between two VDD pins − 550 mV IIK DC input clamping diode current VI < −0.5 V or VI > VDD + 0.5 V − ±10 mA IOK DC output clamping diode current (output type 4 mA) VO < −0.5 V or VO > VDD + 0.5 V − ±20 mA IO DC output source or sink current (output type 4 mA) −0.5 V < VO < VDD + 0.5 V − ±20 mA IDDD, ISSD DC VDD or VSS current per digital supply pin − ±100 mA IDDA, ISSA DC VDD or VSS current per analog supply pin − ±50 mA Ilu(prot) latch-up protection 100 − mA P/out power dissipation per output − 100 mW Ptot total power dissipation − 1.3 W Tstg storage temperature −55 +125 °C Tamb operating ambient temperature −20 +70 °C Ves electrostatic handling note 1 2000 − V note 2 200 − V Notes 1. Human body model: C = 100 pF; R = 1.5 kΩ. 2. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω. 8 THERMAL CHARACTERISTICS SYMBOL Rth j-a 1998 Feb 13 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 20 VALUE UNIT 31 K/W Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 9 CHARACTERISTICS VDD = 5 V; Tamb = 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz; fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with “EBU specification”; 1 kΩ measurement source resistance for AF inputs; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital supplies VDDD1 digital supply voltage 1 4.75 5.0 5.5 V VSSD1 digital supply ground 1 − 0.0 − V IDDD1 digital supply current 1 65 80 95 mA 55 70 85 mA VDDD2 digital supply voltage 2 4.75 5.0 5.5 V VSSD2 digital supply ground 2 − 0.0 − V IDDD2 digital supply current 2 VDDD2 = 5.5 V 50 65 80 mA VDDD2 = 5.0 V 45 55 65 mA VDDD1 = 5.5 V VDDD1 = 5.0 V Demodulator supplies and references VDDA1 analog supply voltage for demodulator part 4.75 5.0 5.5 V VSSA1 analog ground for demodulator part − 0.0 − V IDDA1 analog supply current for demodulator part VDDA = 5.5 V 20 26 31 mA VDDA = 5.0 V 19 24 28 mA Vref1 analog reference voltage for demodulator part referenced to VDDA1/VSSA1 35 50 65 % Iref1(sink) Vref1 sink current 170 220 260 µA Audio supplies and references VDDA2 analog supply voltage for audio ADC part 4.75 5.0 5.5 V VSSA2 analog ground for audio ADC part − 0.0 − V IDDA2 analog supply current for audio ADC part VDDA = 5.5 V 11 14 17 mA VDDA = 5.0 V 10 13 16 mA VDDA3 analog supply voltage for audio DAC part 4.75 5.0 5.5 V VSSA3 analog ground for audio DAC part − 0.0 − V IDDA3 analog supply current for audio DAC part VDDA = 5.5 V; digital silence 9 12 14 mA VDDA = 5.0 V; digital silence 8 11 13 mA VSSA4 analog ground for operational amplifier − 0.0 − V VSSG ground, guard rings for analog-to-digital circuitry − 0.0 − V Vref2 reference voltage for audio ADCs − 50 − % 1998 Feb 13 referenced to VDDA2/VSSA2 21 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875 CONDITIONS MIN. TYP. MAX. UNIT − 20 − kΩ − 20 − kΩ − 50 − % impedance Vref3 to VDDA3 − 20 − kΩ impedance Vref3 to VSSA3 − 20 − kΩ − − 1.6 V ZVref2-VDDA2 impedance Vref2 to VDDA2 ZVref2-VSSA2 impedance Vref2 to VSSA2 Vref3 reference voltage for audio DAC and operational amplifier ZVref3-VDDA3 ZVref3-VSSA3 referenced to VDDA3/VSSA3 Digital inputs and outputs INPUTS CMOS level input, high drive, pull-down (pins TEST1 and TEST2) VIL LOW level input voltage VIH HIGH level input voltage 3.0 − − V Ci input capacitance − − 10 pF Zi input impedance − 50 − kΩ CMOS level input, hysteresis, high drive, pull-up (pin CRESET) VIL LOW level input voltage − − 1.6 V VIH HIGH level input voltage 3.0 − − V Vhys hysteresis voltage − 0.33VDDD − V Ci input capacitance − − 10 pF Zi input impedance − 50 − kΩ INPUTS/OUTPUTS I2C-bus level input with Schmitt trigger, open-drain output stage (pins SCL and SDA) VIL LOW level input voltage − − 1.6 V VIH HIGH level input voltage 3.0 − − V VHYS hysteresis voltage − 0.33VDDD − V ILI input leakage current − − ±10 µA Ci input capacitance − − 10 pF VOL LOW level output voltage − − 0.5 V CL load capacitance active pull-up − − 400 pF passive pull-up − − 200 pF TTL/CMOS level, high drive, 4 mA 3-state output stage, pull-up (pins PCLK, NICAM, ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1 and SDI2) VIL LOW level input voltage − − 0.8 V VIH HIGH level input voltage 2.0 − − V Ci input capacitance − − 10 pF VOL LOW level output voltage IOL = 3 mA − − 0.5 V VOH HIGH level output voltage IOH = −3 mA 2.9 − − V CL load capacitance active pull-up − − 50 pF Zi input impedance − 50 − kΩ 1998 Feb 13 22 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875 CONDITIONS MIN. TYP. MAX. UNIT OUTPUTS 4 mA 3-state output stage (pin SYSCLK) VOL LOW level output voltage IOL = 2 mA IOH = −2 mA VOH HIGH level output voltage CL load capacitance ILIZ 3-state leakage current Vi = 0 to VDDD − − 0.5 V 2.9 − − V − − 50 pF − − ±10 µA SIF1 and SIF2 analog inputs VSIFmax(rms) maximum composite SIF input voltage (RMS value) − 250 − mV VSIFmin(rms) minimum composite SIF input voltage (RMS value) − 21 − mV AGC AGC range − 21 − dB fi input frequency 4 − 9.2 MHz Ri input resistance 10 13 16 kΩ Ci input capacitance − 7.5 11 pF ∆fFM FM deviation B/G standard; THD < 1% 100 − − kHz ∆fFM(FS) FM deviation full-scale level terrestrial FM; level adjust 0 dB 150 − − kHz C/NFM FM carrier C/Nc ratio NFM bandwidth = 6 MHz; white noise for S/N = 40 dB; “CCIR468”; quasi peak − 77 − C/NN NICAM carrier C/Nc ratio Nc bandwidth = 6 MHz; bit error rate = 10−3; white noise − 66 − αct crosstalk attenuation input channel fi = 4 to 9.2 MHz 50 − − dB from FM source to any output; Vo = 1 V (RMS) − 0.3 0.5 % from NICAM source to any output; Vo = 1 V (RMS) − 0.1 0.3 % SC1 from FM source to any 61 output; Vo = 1 V (RMS), TIMPOL bit HIGH 65 − dB SC2 from FM source to any 57 output; Vo = 1 V (RMS), TIMPOL bit HIGH 60 − dB dB FM -------------Hz dB N ---------Hz Demodulator performance THD + N S/N total harmonic distortion plus noise signal-to-noise ratio NICAM source; Vo = 1 V (RMS) 1998 Feb 13 23 NICAM in accordance with “EBU specification”; note 2 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) SYMBOL B−3 PARAMETER −3 dB bandwidth αct crosstalk attenuation αcs(stereo) stereo channel separation αAM AM suppression for FM DEPD de-emphasis S/NAM AM demodulation TDA9875 CONDITIONS MIN. TYP. MAX. UNIT from FM source to any output 14.5 15 − kHz from NICAM source to any output 14.5 15 − kHz from SIF1 or SIF2 to any output 65 70 − dB 40 45 − dB − − dB AM: 1 kHz, 50 30% modulation; reference: 1 kHz, 50 kHz deviation 50 µs, 60 µs, 75 µs, J17, adaptive de-emphasis SIF level 100 mV (RMS); 54% AM; 1 kHz AF; “CCIR468”; quasi peak − 36 − dB IDENTIFICATION FOR FM SYSTEMS modp pilot modulation for identification 25 50 75 % C/Np pilot sideband C/N for identification start − 32 − dB ------Hz hystun hysteresis − − 2 dB fident identification window slow mode 116.85 − 118.12 Hz medium mode 116.11 − 118.89 Hz fast mode 114.65 − 120.46 Hz slow mode 273.44 − 274.81 Hz medium mode 272.07 − 276.20 Hz B/G stereo B/G dual 270.73 − 277.60 Hz slow mode − − 2 s medium mode − − 1 s fast mode − − 0.5 s slow mode − − 2 s medium mode − − 1 s fast mode − − 0.5 s fast mode tident(on) tident(off) total identification time ON total identification time OFF Analog audio inputs MONO INPUT Vi(nom)(rms) nominal level input voltage (RMS value) note 3 − 500 − mV Vi(clip)(rms) clipping level input voltage (RMS value) THD < 3%; note 4 1250 1400 − mV Ri input resistance note 4 28 35 42 kΩ 1998 Feb 13 24 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875 CONDITIONS MIN. TYP. MAX. UNIT SCART AND EXTERNAL INPUTS Vi(nom)(rms) nominal level input voltage at input pin (RMS value) −3 dB divider with external 15 kΩ resistor; notes 3 and 5 − 350 − mV Vi(clip)(rms) clipping level input voltage at input pin (RMS value) −3 dB divider with external 15 kΩ resistor; THD < 3%; notes 4 and 5 1250 1400 − mV Ri input resistance note 4 28 35 42 kΩ 1400 − − mV Analog audio outputs LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS Vo(clip)(rms) clipping level output voltage (RMS value) Ro output resistance 150 250 375 Ω RL(AC) AC load resistance 10 − − kΩ RL(DC) DC load resistance 10 − − kΩ CL output load capacitance − 10 12 nF Voffset(DC) static DC offset voltage − 30 70 mV αmute mute suppression nominal input signal from any source; fi = 1 kHz; note 3 80 − − dB Gro(main,aux) roll-off gain at 14.5 kHz for Main and Auxiliary channels from any source −3 −2 − dB fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 µF; signal from I2S-bus 40 45 − dB PSRRmain,aux power supply ripple rejection for Main and Auxiliary channels THD < 3% SCART OUTPUTS AND LINE OUTPUT Vo(nom)(rms) nominal level output voltage (RMS value) +3 dB amplification; note 3 − 500 − mV Vo(clip)(rms) clipping level output voltage (RMS value) THD < 3% − 1400 − mV Ro output resistance 150 250 375 Ω RL(AC) AC load resistance 10 − − kΩ RL(DC) DC load resistance 10 − − kΩ CL output load capacitance − − 2.5 nF Voffset(DC) static DC offset voltage output amplifiers at +3 dB position − 30 50 mV αmute mute suppression nominal input signal from any source; fi = 1 kHz; note 3 80 − − dB 1998 Feb 13 25 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) SYMBOL Bline PSRRline PARAMETER line bandwidth power supply ripple rejection TDA9875 CONDITIONS MIN. TYP. MAX. UNIT from SCART, external, Auxiliary and mono sources; −3 dB bandwidth 20 − − kHz from DSP sources; −3 dB bandwidth 14.5 − − kHz fripple = 70 Hz; Vripple = 100 mV (peak); CVref = 47 µF; signal from I2S-bus 40 45 − dB from any analog audio input to I2S-bus − 0.1 0.3 % from I2S-bus to any analog audio output − 0.1 0.3 % SCART-to-SCART copy − 0.1 0.3 % SCART-to-Main copy − 0.2 0.5 % from any analog audio input to I2S-bus 73 77 − dB from I2S-bus to any analog audio output 78 90 − dB SCART-to-SCART copy 78 90 − dB SCART-to-Main copy 73 77 − dB between any analog input pairs; fi = 1 kHz 70 − − dB between any analog output pairs; fi = 10 kHz 65 − − dB between left and right of any input pair 65 − − dB between left and right of any output pair 60 − − dB output amplifier in +3 dB position; Rext = 15 kΩ ±10% −1.5 0 +1.1 dB output amplifier in 0 dB position; Rext = 15 kΩ ±10% −4.5 −3.0 −1.9 dB Rext = 15 kΩ ±10%; note 1 −1.5 0 +1.5 dB Audio performance THD + N S/N αct αcs GA total harmonic distortion plus noise signal-to-noise ratio crosstalk attenuation channel separation from SCART-to-SCART with −3 dB input voltage divider from external input to loudspeaker 1998 Feb 13 Vi = Vo = 1 V (RMS); fi = 1 kHz; bandwidth 20 Hz to 15 kHz; note 1 reference voltage Vo = 1.4 V (RMS); fi = 1 kHz; “CCIR468”; quasi peak; note 1 26 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) SYMBOL PARAMETER TDA9875 CONDITIONS MIN. TYP. MAX. UNIT VCXO and clock generation VCXO Crystal input Ci input capacitance Vbias(DC) DC bias voltage Ri = 100 kΩ − − 10 pF 3.5 3.63 3.7 V Crystal output Vosc(p-p) oscillation amplitude (peak-to-peak value) − 1.4 − V Vbias(DC) DC bias voltage 2.0 2.4 2.8 V Gm mutual conductance at 24.576 MHz 16.6 17.6 18.8 Co output capacitance − − 10 pF mA --------V CRYSTAL SPECIFICATION (FUNDAMENTAL MODE) fxtal crystal frequency − 24.576 − MHz CL load capacitance − 20 − pF C1 series capacitance − 20 − fF C0 parallel capacitance − − 7 pF Φpull pulling sensitivity CL changed from 18 to 16 pF − 25 − RR equivalent series resistance at nominal frequency − − 30 Ω RN equivalent series resistance of unwanted mode 2RR − − Ω ∆T temperature range −20 +25 +70 °C XJ adjustment tolerance − − ±30 10−6 XD drift − − ±30 10−6 XA ageing − − ±5 1998 Feb 13 across temperature range 27 –6 10 ----------pF –6 10 ----------year Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Notes to the characteristics 1. ADC level adjust = +6 dB, all other level adjusts = 0 dB, if external −3 dB divider is used set output buffer gain to +3 dB, tone control to 0 dB, AVL off and volume control to 0 dB. 2. Due to companding, the quantization noise of the NICAM system limits signal-to-noise ratio to 62 dB (unweighted; RMS value). 3. Definition of nominal levels: The full-scale level for analog audio signals is VFS = 1.4 V (RMS). The nominal level at the digital crossbar switch is defined at −15 dB (full-scale). a) Audio input nominal levels: SCART: 350 mV (at pin); −12 dB (full-scale) external, mono: 500 mV; −9 dB (full-scale) b) FM/AM path nominal (maximum) levels: system M: 15 kHz deviation; −23.7 dB (full-scale) system B/G, D/K, I: 27 kHz deviation; −18.6 dB (full-scale) SAT stereo (maximum): 50 kHz deviation; −13.3 dB (full-scale) SAT mono (maximum): 85 kHz deviation; −8.7 dB (full-scale) AM: 54% modulation; full-scale SIF ADC; −20 dB (full-scale) c) NICAM path nominal (maximum) levels: system B/G: −18.2 dB (full-scale) system I: −22.8 dB (full-scale) maximum level: 0.0 dB (full-scale). 4. If the supply voltage for the TDA9875 is switched off, because of the ESD protection circuitry, all audio input pins are short-circuited. To avoid a short-circuit at the SCART inputs a 15 kΩ resistor (−3 dB divider) has to be used. 5. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the 5 V supply voltage for the TDA9875, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve SCART-to-SCART copies with 0 dB gain, there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line output. The attenuator is realized by an internal resistor that works together with an external series resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled down to 1.4 V (RMS) at the input pin. To avoid clipping, the +3 dB gain must not be used if the SCART input signal is larger than 1.4 V (RMS). 1998 Feb 13 28 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10 I2C-BUS CONTROL 10.2 10.1 At power-up the device is in the following state: Introduction • All outputs muted The TDA9875 is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers. Status information can be read from an array of registers to enable the controlling microcontroller determine whether any action is required. • No sound carrier frequency loaded • General-purpose I/O pins ready for input (HIGH) • Input SIF1 selected with: – AGC on The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, with a maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar or complementary functions, there are four possible slave addresses available which can be selected by pins ADDR1 and ADDR2 (see Table 7). Table 7 – Small hysteresis. • Demodulators for both sound carriers set to FM with: – Identification for B/G, D/K, response time 1 s – Level adjust set to 0 dB – De-emphasis 50 µs – Matrix set to mono. • Main channel set to FM input with: – Spatial off Possible slave addresses ADDR2 ADDR1 SLAVE ADDRESS A6 TO A0 0 0 1011000 0 1 1011001 1 0 1011010 1 1 1011011 Power-up state – Pseudo off – AVL off – Volume mute – Bass flat – Treble flat – Contour off – Bass boost flat. The I2C-bus interface remains operational in the standby mode of the TDA9875 to allow control of the analog source selectors with regard to SCART-to-SCART copying. • Auxiliary channel set to FM input with: – Volume mute – Bass flat The device will not respond to a ‘general call’ on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master. – Treble flat. • Feature interface all outputs off The data transmission between the microcontroller and the other I2C-bus controlled ICs is not disturbed when the supply voltage of the TDA9875 is not connected. • Beeper off • Monitoring of carrier 1 FM demodulator DC output. After power-up a device initialization has to be performed via the I2C-bus to put the TDA9875 into the proper mode of operation, in accordance with the desired TV standard, audio control settings, etc. 1998 Feb 13 29 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.3 TDA9875 Slave receiver mode As a slave receiver, the TDA9875 provides 46 registers for storing commands and data. These registers are accessed via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location. Table 8 I2C-bus; slave address, subaddress and data format S Table 9 SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA ACK P Explanation of Table 8 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge SUBADDRESS address of register to write to DATA data byte to be written into register P STOP condition It is allowed to send more than one data byte per transmission to the TDA9875. In this event, the subaddress is automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with ACK (acknowledge). There is no ‘wrap-around’ of subaddresses. Commands and data are processed as soon as they have been completely received. Functions requiring more than one byte will, thus, be executed only after all bytes for that function have been received. Should the transmission is terminated (STOP condition) before all bytes have been received, the incomplete data for that function are ignored. Table 10 Format for a transmission employing auto-increment of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA BYTE A(1) DATA ACK P Note 1. n data bytes with auto-increment of subaddresses. Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the functions of volume, bass, treble control, bass boost and level adjust. Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will not then be executed. 1998 Feb 13 30 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 11 Overview of the slave receiver registers (note 1) DATA SUBADDRESS (DECIMAL) MSB 0 X FUNCTION LSB X X g g g g g AGC gain selection (ignored, if AGC off) 1 c c c c c c c c general configuration 2 p X X m m s s s monitor select, peak detector on/off 3 f f f f f f f f carrier 1 frequency; MS part 4 f f f f f f f f carrier 1 frequency 5 f f f f f f f f carrier 1 frequency; LS part 6 f f f f f f f f carrier 2 frequency; MS part 7 f f f f f f f f carrier 2 frequency 8 f f f f f f f f carrier 2 frequency; LS part 9 c c c X c c c c demodulator configuration 10 d d d d d d d d FM de-emphasis 11 X X X X X m m m FM matrix 12 X X X l l l l l channel 1 output level adjust 13 X X X l l l l l channel 2 output level adjust 14 X X c c X X c c NICAM configuration 15 X X X l l l l l NICAM output level adjust 16 l l l l l l l l NICAM lower error limit 17 u u u u u u u u NICAM upper error limit 18 m m m m m m m m audio mute control 19 g m m m g s s s DAC output select 20 X g m m X s s s SCART 1 output select 21 X g m m X s s s SCART 2 output select 22 X g m m X X X s line output select 23 s s s l l l l l ADC output select 24 X m m m X s s s Main channel select 25 X X s s p p a a audio effects (AVL, pseudo, spatial) 26 v v v v v v v v volume control, Main left 27 v v v v v v v v volume control, Main right 28 X X X c c c c c contour control, Main 29 X X X b b b b b bass control, Main 30 X X X t t t t t treble control, Main 31 X m m m X s s s Auxiliary channel select 32 v v v v v v v v volume control, Auxiliary left 33 v v v v v v v v volume control, Auxiliary right 34 X X X b b b b b bass control, Auxiliary 35 X X X t t t t t treble control, Auxiliary 36 X X X c c c c c feature interface configuration 37 X m m m X s s s I2S1 output select 1998 Feb 13 31 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 DATA SUBADDRESS (DECIMAL) MSB FUNCTION LSB 38 X X X i i i i i I2S1 input level adjust 39 X X X o o o o o I2S1 output level adjust 40 X m m m X s s s I2S2 output select 41 X X X i i i i i I2S2 input level adjust 42 X X X o o o o o I2S2 output level adjust 43 X X X X X f f f beeper frequency 44 X X v v v v v v beeper volume, Main and Auxiliary 45 b b b b b b b b bass boost, Main left and right Note 1. X indicates bits that have not yet been assigned to a function. Their meaning is ‘don’t care’. They should be written as a zero. The following sub-sections provide a detailed description of the slave receiver registers: 10.3.1 10.3.1.1 AGC GAIN REGISTER Description If the automatic gain control function is switched off in the General Configuration Register, the contents of this register will define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF ADC. If automatic gain control is on, the contents of this register is ignored. It should be noted that the input voltages should be considered as approximate target values. 1998 Feb 13 32 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.3.1.2 TDA9875 Definition Table 12 Subaddress 0 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 SIF INPUT VOLTAGE [mV (RMS)] X X X 1 1 1 1 1 240 X X X 1 1 1 1 0 214 X X X 1 1 1 0 1 195 X X X 1 1 1 0 0 176 X X X 1 1 0 1 1 159 X X X 1 1 0 1 0 145 X X X 1 1 0 0 1 131 X X X 1 1 0 0 0 119 X X X 1 0 1 1 1 107 X X X 1 0 1 1 0 99 X X X 1 0 1 0 1 90 X X X 1 0 1 0 0 82 X X X 1 0 0 1 1 76 X X X 1 0 0 1 0 70 X X X 1 0 0 0 1 65 X X X 1 0 0 0 0 60 X X X 0 1 1 1 1 55 X X X 0 1 1 1 0 51 X X X 0 1 1 0 1 48 X X X 0 1 1 0 0 45 X X X 0 1 0 1 1 42 X X X 0 1 0 1 0 39 X X X 0 1 0 0 1 36 X X X 0 1 0 0 0 34 X X X 0 0 1 1 1 32 X X X 0 0 1 1 0 30 X X X 0 0 1 0 1 29 X X X 0 0 1 0 0 27 X X X 0 0 0 1 1 25 X X X 0 0 0 1 0 24 X X X 0 0 0 0 1 23 X X X 0 0 0 0 0 22 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 33 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.3.2 TDA9875 GENERAL CONFIGURATION REGISTER 10.3.2.1 Description Table 13 Description of Table 14 NAME HIGH/LOW SIFSEL HIGH Selects pin SIF2 for input (recommended for satellite tuner). LOW Pin SIF1 (terrestrial TV) is selected. HIGH Forces the AGC block to a fixed gain as defined in the AGC gain register. LOW The automatic gain control function is enabled and the contents of the AGC gain register is ignored. HIGH A longer decay time and larger hysteresis are selected for input signals with strong video modulation (intercarrier). This bit only has an effect when bit AGCOFF = 0. LOW Selects normal attack and decay times for the AGC and a small hysteresis. HIGH Causes initialization of TDA9875 to its default settings. This has the same effect as a power-on reset. If there is a conflict between the default settings and any bit set HIGH in this register, the bits of this register have priority over the corresponding default setting. LOW This bit is automatically reset to LOW after initialization. When set LOW, the TDA9875 is in its normal mode of operation. HIGH Puts the TDA9875 into the standby mode. Most functions are disabled and power dissipation is somewhat reduced, but the analog selectors/matrices remain operational to support analog copying from SCART 1 to SCART 2 and vice versa. LOW The TDA9875 is in its normal mode of operation. On return from standby mode, the device is in its power-on reset mode and needs to be re-initialized. − These bits control the general purpose input/output pins. The contents of these bits is written directly to the corresponding pins. If input is desired, the bits must be set HIGH to allow the pins to be pulled LOW externally. Input from the pins is reflected in the device status register (see Section 10.4, subaddress 0). P1OUT is recommended to be used for switching an SIF trap for the adjacent picture carrier in designs that employ such a trap. AGCOFF AGCSLOW INIT STDBY P1OUT, P2OUT 10.3.2.2 FUNCTION Definition Table 14 Subaddress 1 (note 1) BIT NAME DESCRIPTION 7 (MSB) P2OUT general purpose I/O pin 2 6 P1OUT general purpose I/O pin 1 5 STDBY stand-by mode on/off 4 INIT 3 X 2 initialize to defaults (as reset) don’t care AGCSLOW AGC decay time 1 AGCOFF 0 (LSB) SIFSEL AGC on/off SIF input select Note 1. The default setting at power-up is 11000000. 1998 Feb 13 34 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.3.3 TDA9875 MONITOR SELECT REGISTER 10.3.3.1 Description This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be monitored. Peak level refers to the magnitude of the maximum excursion of a signal. Data can be read-out in the I2C-bus slave transmitter mode (see Section 10.4, subaddresses 5 and 6). Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in FM mode, while magnitude is supplied in AM mode. Table 15 Description of bit PEAKMON NAME HIGH/LOW PEAKMON 10.3.3.2 FUNCTION HIGH selects the peak level of a source to be monitored LOW the last sample will be supplied Definition Table 16 Subaddress 2 (notes 1, 2 and 3) MSB LSB B7 B6 B5 PEAKMON X X B4 B3 B2 see Table 18 B1 B0 see Table 17 Notes 1. X = don’t care. 2. PEAKMON is described in Section 10.3.3.1. 3. The default setting at power-up is 00000000. Table 17 Signal source (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 DC output of FM demodulator 0 0 1 audio magnitude/phase, FM demodulator output 0 1 0 crossbar input from FM/AM channel 0 1 1 crossbar input from NICAM channel 1 0 0 crossbar input from I2S1 channel 1 0 1 crossbar input from I2S2 channel 1 1 0 crossbar input from audio ADC channel 1 1 1 input to Main channel DAC (without beeper) Note 1. The term ‘crossbar’ refers to the digital selector, where level-adjusted signals from various sources are available. 1998 Feb 13 35 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 19 Subaddresses 3 to 5 Table 18 Monitor output B4 B3 MONITOR OUTPUT 0 0 L input + R input ------------------------------------------2 0 1 L input (channel 1, respectively) 5 1 0 R input (channel 2, respectively) 4 BIT SUBADDRESSES 7 (MSB) 6 3 10.3.3.3 Note 2 By reading out Level Read-out Registers (subaddresses 5 and 6, see Section 10.4), the current peak level will be reset. 10.3.4 10.3.4.1 3 1 0 7 6 CARRIER 1 FREQUENCY REGISTER 5 Description 4 The three bytes together constitute a 24-bit frequency control word to represent the sound carrier (i.e. mixer) frequency in accordance with the following formula: f mix 24 data = --------- × 2 f clk 3 4 2 1 0 7 Where: 6 Data = 24-bit frequency control word 5 fmix = desired sound carrier frequency 4 fclk = 12.288 MHz (clock frequency of mixer) 3 224 = 16777216 (number of steps in a 24-bit word size). 2 5 1 Example: A 5.5 MHz sound carrier frequency will be generated by sending the following sequence of data bytes to the TDA9875 (data = 7509333 in decimal notation or 729555 in hex): 01110010 10010101 01010101. 0 (LSB) 10.3.5 As three bytes are required to define a carrier frequency, execution of this command starts only after all bytes have been received. If an error occurs, e.g. a premature STOP condition, partial data for this function is ignored. 10.3.5.1 CARRIER 2 FREQUENCY REGISTER Description Same as for sound carrier 1. The default setting at power-up is 00000000 for all three bytes. If the carrier 2 frequency register is used, it will be for either the second FM sound carrier of a terrestrial or satellite FM program or the NICAM sound carrier. 10.3.4.2 10.3.5.2 Definition Definition Subaddresses 6 to 8. Most significant part at subaddress 3. Same as for sound carrier 1, except for subaddresses used. 1998 Feb 13 36 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.3.6 TDA9875 DEMODULATOR CONFIGURATION REGISTER 10.3.6.1 Definition Table 20 Subaddress 9 (note 1; see Table 23) BIT NAME 7 (MSB) IDMOD1 6 IDMOD0 5 IDAREA 4 X 3 CH2MOD1 2 CH2MOD0 DESCRIPTION response time for FM sound mode identification application area for FM identification don’t care channel 2 receive mode 1 CH1WIDE channel 1 bandwidth 0 (LSB) CH1MODE channel 1 receive mode Note 1. The default setting at power-up is 00000000. Table 21 Channel 2 receive mode (see Table 20) B3 B2 CHANNEL 2 0 0 FM 0 1 AM 1 0 NICAM B7 B6 IDENT MODE 0 0 slow 0 1 medium 1 0 fast 1 1 off/reset Table 22 Identification mode (see Table 20) 1998 Feb 13 37 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.3.6.2 TDA9875 Description Table 23 Description of subaddress 9 (notes 1 and 2) NAME HIGH/LOW CH1MODE HIGH Selects the hardware for the first sound carrier to operate in AM mode. LOW FM mode is assumed. This applies to both terrestrial and satellite FM reception. CH1WIDE HIGH Switches the decimation filters for the first sound carrier to a wide bandwidth, so that the main sound carrier of a satellite channel with its larger deviation can be handled without additional distortion. LOW The bandwidth is narrow to cope with the intermodulation requirements of FM stereo. − These bits control the hardware for the second sound carrier in accordance with the truth Table 21. The NICAM mode employs a wider bandwidth of the decimation filters than the FM mode. HIGH Selects FM identification frequencies in accordance with the specification for Korea. LOW Frequencies for Europe are selected (B/G and D/K standard). CH2MOD0, CH2MOD1 IDAREA − IDMOD0, IDMOD1 FUNCTION These bits define the response time after which a sound mode identification result may be expected. The longer the time, the more reliable the identification. Notes 1. It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial 2-carrier sound. 2. Switching the identification off will reset the associated hardware to a defined state. 10.3.7 FM DE-EMPHASIS REGISTER 10.3.7.1 Description This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2. In the event of FM stereo reception, both groups must be set to the same characteristics. 10.3.7.2 Definition Table 24 Subaddress 10 (note 1) BIT NAME 7 (MSB) ADEEM2 6 DESCRIPTION adaptive de-emphasis on/off time constant selection for FM de-emphasis 5 4 3 2 ADEEM1 adaptive de-emphasis on/off time constant selection for FM de-emphasis 1 0 (LSB) Note 1. The default setting at power-up is 00000000. 1998 Feb 13 38 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 25 De-emphasis B6 and B2 B5 and B1 B4 and B0 DE-EMPHASIS 0 0 0 50 µs (Europe) 0 0 1 60 µs 0 1 0 75 µs (M standard) 0 1 1 J17 1 0 0 off Table 26 Description of bits ADEEM1 and ADEEM2 (note 1) NAME HIGH/LOW ADEEM1, ADEEM2 FUNCTION HIGH Activates the adaptive de-emphasis function, which is required for certain satellite FM channels. The standard FM de-emphasis must then be set to 75 µs. LOW The adaptive de-emphasis is off. Note 1. The FM de-emphasis gain is 0 dB at 40 Hz. 10.3.8 FM MATRIX REGISTER 10.3.8.1 Description This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received carrier and the related sound mode identification. For the dematrixing, it is assumed that the output from sound carrier 1 is on channel L input. 10.3.8.2 Definition Table 27 Subaddress 11 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 X X X X X B2 B1 B0 see Table 28 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. Table 28 Description of Subaddress 11 (bits B2 to B0) B2 B1 B0 L OUTPUT R OUTPUT MODE 0 0 0 L input L input mono 1 0 0 1 R input R input mono 2 0 1 0 L input R input dual 0 1 1 R input L input dual swapped 1 0 0 2L input − R input R input stereo Europe 1 0 1 L input + R input ------------------------------------------2 L input – R input ------------------------------------------2 stereo Korea 1998 Feb 13 39 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.3.9 10.3.9.1 TDA9875 CHANNEL 1 OUTPUT LEVEL ADJUST REGISTER Description This register is used to correct for standard and station-dependent differences of signal levels. Table 29 applies to sound carrier 1. 10.3.9.2 Definition Table 29 Subaddress 12 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 40 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.10 CHANNEL 2 OUTPUT LEVEL ADJUST REGISTER 10.3.10.1 Description This register is used to correct for standard and station-dependent differences of signal levels. Table 30 applies to sound carrier 2 in its FM and AM modes. In the event of FM stereo or FM dual language reception, channels 1 and 2 should be adjusted to the same level. 10.3.10.2 Definition Table 30 Subaddress 13 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X 0 1 1 1 1 +15 X X X 0 1 1 1 0 +14 X X X 0 1 1 0 1 +13 X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 X X X 1 0 0 1 1 −13 1998 Feb 13 41 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 MSB B7 LSB B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X 1 0 0 1 0 −14 X X X 1 0 0 0 1 −15 X X X 1 0 0 0 0 mute Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 10.3.11 NICAM CONFIGURATION REGISTER 10.3.11.1 Definition Table 31 Subaddress 14 (note 1) BIT NAME DESCRIPTION 7 (MSB) X don’t care 6 X don’t care 5 TIMPOL timing loop polarity 4 DOUTEN data output enable 3 X don’t care 2 X don’t care 1 NDEEM de-emphasis on/off 0 (LSB) AMUTE auto-muting on/off Note 1. The default setting at power-up is 00000000. 1998 Feb 13 42 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.11.2 Description Table 32 Description of Table 31 (notes 1, 2 and 3) NAME HIGH/LOW AMUTE HIGH Automatic muting is disabled. This bit has only an effect when the second sound carrier is set to NICAM. LOW enables the automatic switching between NICAM and the program on the first sound carrier (i.e. FM mono or AM), dependent on the NICAM bit error rate HIGH switches the NICAM J17 de-emphasis off LOW switches the NICAM J17 de-emphasis on HIGH enables the output of the NICAM serial data stream from the DQPSK demodulator and of the associated clock, PCLK LOW both outputs will be 3-stated HIGH Inverts the polarity. This feature can be used to compensate for the phase shift that is introduced by an external inverting amplifier at the pin Vtune. Such an amplifier could be used to provide a larger tuning voltage swing for the VCXO. LOW sets the NICAM timing loop to normal polarity NDEEM DOUTEN TIMPOL FUNCTION Notes 1. The decision of whether auto-muting is permitted shall be taken by the controlling microcontroller based on information contained in the TDA9875’s status registers. Thus, it depends on the strategy implemented in the software whether the auto-mute function is in accordance with “NICAM 728 ETS Revised for Data Applications” or any other preference. 2. The NICAM de-emphasis gain is 0 dB at 40 Hz. 3. In FM mode of sound carrier 2, the TIMPOL bit can be used to switch pin Vtune HIGH or LOW. 10.3.12 NICAM OUTPUT LEVEL ADJUST REGISTER 10.3.12.1 Description This register is used to correct for standard and station-dependent differences of signal levels. Table 33 applies to both NICAM sound outputs. 10.3.12.2 Definition Table 33 Subaddress 15 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X 0 1 1 1 1 +15 X X X 0 1 1 1 0 +14 X X X 0 1 1 0 1 +13 X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 1998 Feb 13 43 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 X X X 1 0 0 1 1 −13 X X X 1 0 0 1 0 −14 X X X 1 0 0 0 1 −15 X X X 1 0 0 0 0 mute Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 10.3.13 NICAM LOWER ERROR LIMIT REGISTER 10.3.13.1 Description When the auto-mute function is enabled (bit AMUTE in the NICAM configuration register) and the NICAM bit error count is lower than the value contained in this register, the NICAM signal is reselected for reproduction, see Section 10.3.14. 10.3.13.2 Definition Table 34 Subaddress 16 (notes 1 and 2) MSB B7 LSB B6 B5 B4 B3 Notes 1. The default setting at power-up is 00010100. 2. The lower bit error rate limit ≅ subaddress 16 × 1.74 × 10−5. 1998 Feb 13 44 B2 B1 B0 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.14 NICAM UPPER ERROR LIMIT REGISTER 10.3.14.1 Description When the auto-mute function is enabled (bit AMUTE in the NICAM configuration register) and the NICAM bit error count is higher than the value contained in this register, the signal of the first sound carrier (i.e. FM mono or AM sound) is selected for reproduction. The difference between upper and lower error limit constitutes a hysteresis to avoid frequent switching between NICAM and the program on the first sound carrier. 10.3.14.2 Definition Table 35 Subaddress 17 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 Notes 1. The default setting at power-up is 01010000. 2. The lower bit error rate limit ≅ subaddress 16 × 1.74 × 10−5. 10.3.15 AUDIO MUTE CONTROL REGISTER 10.3.15.1 Description When any of these bits are set HIGH, the corresponding pair of output channels will be muted. A LOW bit allows normal signal output. There is a soft-mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the volume control. This is switched on/off by bits MUTMAIN and MUTAUX. 10.3.15.2 Definition Table 36 Subaddress 18 (note 1) BIT NAME DESCRIPTION 7 (MSB) MUTI2S2 mute I2S2 outputs 6 MUTI2S1 mute I2S1 outputs 5 MUTDAC mute internal DAC 4 MUTLINE mute line outputs 3 MUTSC2 mute SCART 2 outputs 2 MUTSC1 mute SCART 1 outputs 1 MUTAUX mute Auxiliary outputs 0 (LSB) MUTMAIN mute Main channels Note 1. The default setting at power-up is 11111111. 1998 Feb 13 45 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.16 DAC OUTPUT SELECT REGISTER 10.3.16.1 Description This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for signal selection. The DAC is used for signal output from digital sources at analog outputs. The two combinations of FM and NICAM apply to the (rare) condition that three different languages are being broadcast in an FM + NICAM system. They allow for a two-out-of-three selection for external use, such as recording. 10.3.16.2 Definition Table 37 Subaddress 19 (note 1) MSB B7 LSB B6 DACGAIN2(2) B5 B4 B3 B2 DACGAIN1(2) see Table 39 B1 see Table 38 Notes 1. The default setting at power-up is 00000000. 2. See Table 40. Table 38 Signal source left and right SIGNAL SOURCE B2 B1 B0 LEFT RIGHT 0 0 0 FM left FM right 0 0 1 NICAM left NICAM right 0 1 0 I2S1 left I2S1 right 0 1 1 I2S2 left I2S2 right 1 0 0 ADC left ADC right 1 0 1 AVL left AVL right 1 1 0 FM mono NICAM M1 1 1 1 FM mono NICAM M2 Table 39 Bits B6 to B4 (note 1) B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 X X L+R -------------2 L+R -------------2 Note 1. X = don’t care. 1998 Feb 13 46 B0 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 40 Description of bits DACGAIN1 and DACGAIN2 NAME HIGH/LOW DACGAIN1, DACGAIN2 FUNCTION HIGH These bits can introduce some extra gain at the input to the DAC. DACGAIN1 adds 3 dB and DACGAIN2 adds 6 dB of gain, respectively. LOW Sets a gain of 0 dB. 10.3.17 SCART 1 OUTPUT SELECT REGISTER 10.3.17.1 Description This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode. 10.3.17.2 Definition Table 41 Subaddress 20 (notes 1 and 2) MSB LSB B7 B6 X SC1GAIN(3) B5 B4 B3 see Table 43 B2 X B1 see Table 42 Notes 1. X = don’t care. 2. The default setting at power-up is 00000001. 3. See Table 44. Table 42 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input 1 0 0 DAC input Table 43 Bits B5 and B4 B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input 1998 Feb 13 47 B0 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 44 Description of bit SC1GAIN (note 1) NAME HIGH/LOW FUNCTION HIGH Activates the 3 dB gain stage at the SCART 1 output port. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to SCART 1 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. LOW The audio signal will be output unchanged (0 dB gain). SC1GAIN Note 1. A possibility to copy from SCART 1 input to SCART 1 output is not implemented. 10.3.18 SCART 2 OUTPUT SELECT REGISTER 10.3.18.1 Description This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode. 10.3.18.2 Definition Table 45 Subaddress 21 (notes 1 and 2) MSB LSB B7 B6 X SC2GAIN(3) B5 B4 B3 see Table 47 B2 X B1 see Table 46 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 3. See Table 48. Table 46 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 0 SCART 1 input 0 1 0 external input 0 1 1 mono input 1 0 0 DAC input Table 47 Bits B5 and B4 B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input 1998 Feb 13 48 B0 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 48 Description of bit SC2GAIN (note 1) NAME HIGH/LOW FUNCTION SC2GAIN HIGH Activates the 3 dB gain stage at the SCART 2 output port. As any SCART input passes a 3 dB attenuator, this gain stage can be used to compensate that attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to SCART 2 output. However, that gain must be used with great care, as it will cause signal clipping at high input levels. LOW The audio signal will be output unchanged (0 dB gain). Note 1. A possibility to copy from SCART 2 input to SCART 2 output is not implemented. 10.3.19 LINE OUTPUT SELECT REGISTER 10.3.19.1 Description By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form. This register is used to characterize the signal to be output at the line output and define the output channel selector mode. 10.3.19.2 Definition Table 49 Subaddress 22 (note 1) BIT NAME DESCRIPTION 7 (MSB) X don’t care 6 LINGAIN line output gain on/off; see Table 51 5 see Table 50 4 3 X don’t care 2 X don’t care 1 X don’t care 0 (LSB) LINSEL select source for line output; see Table 51 Note 1. The default setting at power-up is 00000000. Table 50 Bits B5 and B4 B5 B4 L OUTPUT R OUTPUT 0 0 L input R input 0 1 L input L input 1 0 R input R input 1 1 R input L input 1998 Feb 13 49 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 51 Description of bits LINSEL and LINGAIN NAME HIGH/LOW LINSEL HIGH Specifies that a signal from an analog source is being processed in the Main channel. Analog signal sources comprise SCART 1 input, SCART 2 input, external input and mono input, i.e. any input to the ADC. LOW Specifies that a signal from a digital source is being processed in the Main channel. Digital signal sources comprise FM, NICAM, I2S1 input and I2S2 input. HIGH Activates the 3 dB gain stage at the line output port. LOW The audio signal will be output unchanged (0 dB gain). LINGAIN FUNCTION 10.3.20 ADC OUTPUT SELECT REGISTER 10.3.20.1 Description This register is used to define the signal source for the ADC. There is no output channel selector, because all digital signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided. 10.3.20.2 Definition Table 52 Subaddress 23 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 see Table 53 B1 B0 see Table 54 Note 1. The default setting at power-up is 00000000. Table 53 Signal source B7 B6 B5 SIGNAL SOURCE 0 0 0 SCART 1 input 0 0 1 SCART 2 input 0 1 0 external input 0 1 1 mono input Table 54 Gain setting (notes 1 and 2) B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 1 1 1 1 1 1 1 0 +15 +14 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 +13 +12 +11 0 0 1 1 0 0 1 0 0 1 +10 +9 0 0 1 0 0 1 0 1 0 1 +8 +7 1998 Feb 13 50 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 B4 B3 B2 B1 B0 GAIN SETTING (dB) 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 +6 +5 +4 +3 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 +2 +1 0 −1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 −2 −3 −4 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 −5 −6 −7 −8 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 −9 −10 −11 −12 −13 −14 −15 mute Notes 1. An input of the DAC output to the ADC is meaningless and, therefore, not implemented. 2. A full-scale input signal to the ADC results in an output level of −6 dB (full-scale). This occurs prior to any gain setting. 10.3.21 MAIN CHANNEL SELECT REGISTER 10.3.21.1 Description This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode of the digital matrix for signal selection. 10.3.21.2 Definition Table 55 Subaddress 24 (notes 1 and 2) MSB B7 X LSB B6 B5 B4 B3 see Table 57 X Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 51 B2 B1 see Table 56 B0 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 56 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 0 FM input 0 0 1 NICAM input 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC input B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 X X L+R -------------2 L+R -------------2 Table 57 Bits B6 to B4 (note 1) Note 1. X = don’t care. 10.3.22 AUDIO EFFECTS REGISTER 10.3.22.1 Definition Table 58 Subaddress 25 (notes 1 and 2; see Table 62) MSB LSB B7 B6 B5 X X SPATIAL1(3) B4 B3 B2 SPATIAL0(3) PSEUDO1(4) PSEUDO0(4) B1 B0 AVL1(5) AVL0(5) Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 3. See Table 61. 4. See Table 60. 5. See Table 59. Table 59 AVL control mode 1998 Feb 13 B1 B0 AVL MODE 0 0 off/reset 0 1 short decay 1 0 medium decay 1 1 long decay 52 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 60 Pseudo control setting B3 B2 PSEUDO SETTING (Hz) 0 0 off 0 1 300 1 0 200 1 1 150 B5 B4 SPATIAL SETTING (%) 0 0 off 0 1 30 1 0 40 1 1 52 Table 61 Spatial control setting Table 62 Description of Table 58 (notes 1, 2 and 3) NAME FUNCTION AVL0, AVL1 These bits set the mode of operation of the automatic volume level control function at the entrance to the Main (loudspeaker) channel. PSEUDO0, PSEUDO1 These bits set the amount of the effect function (pseudo stereo) for mono signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification. SPATIAL0, SPATIAL1 These bits set the amount of the effect function (stereo base width expansion) for stereo signals in the Main channel. This function should be activated only in accordance with the result of the sound mode identification. Notes 1. Switching the AVL off will reset the associated hardware to a defined state. 2. When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to avoid excessive settling times. This can be achieved by switching the AVL off and on again. 3. The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in Table 60. There is a gain of 3 dB in the audio channel containing the filter. 10.3.23 VOLUME CONTROL REGISTERS (MAIN) 10.3.23.1 Description These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies to the left channel signal, while the register at subaddress 27 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings. 1998 Feb 13 53 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.23.2 Definition Table 63 Subaddresses 26 and 27 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 0 0 0 1 1 0 0 0 +24 0 0 0 1 0 1 1 1 +23 0 0 0 1 0 1 1 0 +22 0 0 0 1 0 1 0 1 +21 0 0 0 1 0 1 0 0 +20 0 0 0 1 0 0 1 1 +19 0 0 0 1 0 0 1 0 +18 0 0 0 1 0 0 0 1 +17 0 0 0 1 0 0 0 0 +16 0 0 0 0 1 1 1 1 +15 0 0 0 0 1 1 1 0 +14 0 0 0 0 1 1 0 1 +13 0 0 0 0 1 1 0 0 +12 0 0 0 0 1 0 1 1 +11 0 0 0 0 1 0 1 0 +10 0 0 0 0 1 0 0 1 +9 0 0 0 0 1 0 0 0 +8 0 0 0 0 0 1 1 1 +7 0 0 0 0 0 1 1 0 +6 0 0 0 0 0 1 0 1 +5 0 0 0 0 0 1 0 0 +4 0 0 0 0 0 0 1 1 +3 0 0 0 0 0 0 1 0 +2 0 0 0 0 0 0 0 1 +1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 −1 1 1 1 1 1 1 1 0 −2 1 1 1 1 1 1 0 1 −3 1 1 1 1 1 1 0 0 −4 1 1 1 1 1 0 1 1 −5 1 1 1 1 1 0 1 0 −6 1 1 1 1 1 0 0 1 −7 1 1 1 1 1 0 0 0 −8 1 1 1 1 0 1 1 1 −9 1 1 1 1 0 1 1 0 −10 1 1 1 1 0 1 0 1 −11 1 1 1 1 0 1 0 0 −12 1998 Feb 13 54 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 MSB B7 LSB B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 1 1 1 1 0 0 1 1 −13 1 1 1 1 0 0 1 0 −14 1 1 1 1 0 0 0 1 −15 1 1 1 1 0 0 0 0 −16 1 1 1 0 1 1 1 1 −17 1 1 1 0 1 1 1 0 −18 1 1 1 0 1 1 0 1 −19 1 1 1 0 1 1 0 0 −20 1 1 1 0 1 0 1 1 −21 1 1 1 0 1 0 1 0 −22 1 1 1 0 1 0 0 1 −23 1 1 1 0 1 0 0 0 −24 1 1 1 0 0 1 1 1 −25 1 1 1 0 0 1 1 0 −26 1 1 1 0 0 1 0 1 −27 1 1 1 0 0 1 0 0 −28 1 1 1 0 0 0 1 1 −29 1 1 1 0 0 0 1 0 −30 1 1 1 0 0 0 0 1 −31 1 1 1 0 0 0 0 0 −32 1 1 0 1 1 1 1 1 −33 1 1 0 1 1 1 1 0 −34 1 1 0 1 1 1 0 1 −35 1 1 0 1 1 1 0 0 −36 1 1 0 1 1 0 1 1 −37 1 1 0 1 1 0 1 0 −38 1 1 0 1 1 0 0 1 −39 1 1 0 1 1 0 0 0 −40 1 1 0 1 0 1 1 1 −41 1 1 0 1 0 1 1 0 −42 1 1 0 1 0 1 0 1 −43 1 1 0 1 0 1 0 0 −44 1 1 0 1 0 0 1 1 −45 1 1 0 1 0 0 1 0 −46 1 1 0 1 0 0 0 1 −47 1 1 0 1 0 0 0 0 −48 1 1 0 0 1 1 1 1 −49 1 1 0 0 1 1 1 0 −50 1 1 0 0 1 1 0 1 −51 1998 Feb 13 55 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 MSB B7 LSB B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 1 1 0 0 1 1 0 0 −52 1 1 0 0 1 0 1 1 −53 1 1 0 0 1 0 1 0 −54 1 1 0 0 1 0 0 1 −55 1 1 0 0 1 0 0 0 −56 1 1 0 0 0 1 1 1 −57 1 1 0 0 0 1 1 0 −58 1 1 0 0 0 1 0 1 −59 1 1 0 0 0 1 0 0 −60 1 1 0 0 0 0 1 1 −61 1 1 0 0 0 0 1 0 −62 1 1 0 0 0 0 0 1 −63 1 1 0 0 0 0 0 0 −64 1 0 1 1 1 1 1 1 −65 1 0 1 1 1 1 1 0 −66 1 0 1 1 1 1 0 1 −67 1 0 1 1 1 1 0 0 −68 1 0 1 1 1 0 1 1 −69 1 0 1 1 1 0 1 0 −70 1 0 1 1 1 0 0 1 −71 1 0 1 1 1 0 0 0 −72 1 0 1 1 0 1 1 1 −73 1 0 1 1 0 1 1 0 −74 1 0 1 1 0 1 0 1 −75 1 0 1 1 0 1 0 0 −76 1 0 1 1 0 0 1 1 −77 1 0 1 1 0 0 1 0 −78 1 0 1 1 0 0 0 1 −79 1 0 1 1 0 0 0 0 −80 1 0 1 0 1 1 1 1 −81 1 0 1 0 1 1 1 0 −82 1 0 1 0 1 1 0 1 −83 1 0 1 0 1 1 0 0 mute (note 1) Note 1. The default setting at power-up is 10101100. 1998 Feb 13 56 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.24 CONTOUR CONTROL REGISTER 10.3.24.1 Description This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so, of decrease of the volume setting. The 0 dB contour setting is equal to contour off. 10.3.24.2 Definition Table 64 Subaddress 28 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 CONTOUR GAIN (dB) X X X 1 0 0 1 0 18 X X X 1 0 0 0 1 17 X X X 1 0 0 0 0 16 X X X 0 1 1 1 1 15 X X X 0 1 1 1 0 14 X X X 0 1 1 0 1 13 X X X 0 1 1 0 0 12 X X X 0 1 0 1 1 11 X X X 0 1 0 1 0 10 X X X 0 1 0 0 1 9 X X X 0 1 0 0 0 8 X X X 0 0 1 1 1 7 X X X 0 0 1 1 0 6 X X X 0 0 1 0 1 5 X X X 0 0 1 0 0 4 X X X 0 0 0 1 1 3 X X X 0 0 0 1 0 2 X X X 0 0 0 0 1 1 X X X 0 0 0 0 0 0 (note 2) Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 10.3.25 BASS CONTROL REGISTER (MAIN) 10.3.25.1 Description This register is used to apply bass control to the left and right signal channels of the Main channel. 1998 Feb 13 57 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.25.2 Definition Table 65 Subaddress 29 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 BASS SETTING (dB) X X X 0 1 1 1 1 +15 X X X 0 1 1 1 0 +14 X X X 0 1 1 0 1 +13 X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 (note 2) X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 58 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.26 TREBLE CONTROL REGISTER (MAIN) 10.3.26.1 Description This register is used to apply treble control to the left and right signal channels of the Main channel. 10.3.26.2 Definition Table 66 Subaddress 30 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 TREBLE SETTING (dB) X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 (note 2) X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 59 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.27 AUXILIARY CHANNEL SELECT REGISTER 10.3.27.1 Description This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode of the digital matrix for signal selection. 10.3.27.2 Definition Table 67 Subaddress 31 (notes 1 and 2) MSB LSB B7 B6 X B5 B4 B3 see Table 69 B2 B1 X B0 see Table 68 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. Table 68 Signal source B2 B1 B0 SIGNAL SOURCE 0 0 0 FM input 0 0 1 NICAM input 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC input 1 0 1 AVL input B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 X X L+R -------------2 L+R -------------2 Table 69 Bits B6 to B4 (note 1) Note 1. X = don’t care. 1998 Feb 13 60 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY) 10.3.28.1 Description These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32 applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal. Balance control is exercised by offsetting the left and right channel volume settings. 10.3.28.2 Definition Table 70 Subaddresses 32 and 33 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 0 1 0 +8 +7 +6 +5 +4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 +3 +2 +1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 −1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 −2 −3 −4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 1 0 1 −5 −6 −7 1998 Feb 13 61 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 −8 −9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 −10 −11 −12 −13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 −14 −15 −16 −17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 −18 −19 −20 −21 −22 −23 −24 −25 −26 −27 −28 −29 −30 −31 −32 −33 −34 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 −35 −36 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 1 0 1 −37 −38 −39 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 1 0 −40 −41 −42 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 0 −43 −44 −45 −46 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 −47 −48 1998 Feb 13 62 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 VOLUME SETTING (dB) 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 −49 −50 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 0 −51 −52 −53 −54 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 −55 −56 −57 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 −58 −59 −60 −61 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 −62 −63 −64 −65 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 −66 −67 −68 −69 −70 −71 −72 −73 −74 −75 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 −76 −77 −78 −79 −80 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 0 1 −81 −82 −83 1 0 1 0 1 1 0 0 mute (note 1) Note 1. The default setting at power-up is 10101100. 1998 Feb 13 63 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.29 BASS CONTROL REGISTER (AUXILIARY) 10.3.29.1 Description This register is used to apply bass control to the left and right signal channels of the Auxiliary channel. 10.3.29.2 Definition Table 71 Subaddress 34 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 BASS SETTING (dB) X X X 0 1 1 1 1 +15 X X X 0 1 1 1 0 +14 X X X 0 1 1 0 1 +13 X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 (note 2) X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 64 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.30 TREBLE CONTROL REGISTER (AUXILIARY) 10.3.30.1 Description This register is used to apply treble control to the left and right signal channels of the Auxiliary channel. 10.3.30.2 Definition Table 72 Subaddress 35 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 TREBLE SETTING (dB) X X X 0 1 1 0 0 +12 X X X 0 1 0 1 1 +11 X X X 0 1 0 1 0 +10 X X X 0 1 0 0 1 +9 X X X 0 1 0 0 0 +8 X X X 0 0 1 1 1 +7 X X X 0 0 1 1 0 +6 X X X 0 0 1 0 1 +5 X X X 0 0 1 0 0 +4 X X X 0 0 0 1 1 +3 X X X 0 0 0 1 0 +2 X X X 0 0 0 0 1 +1 X X X 0 0 0 0 0 0 (note 2) X X X 1 1 1 1 1 −1 X X X 1 1 1 1 0 −2 X X X 1 1 1 0 1 −3 X X X 1 1 1 0 0 −4 X X X 1 1 0 1 1 −5 X X X 1 1 0 1 0 −6 X X X 1 1 0 0 1 −7 X X X 1 1 0 0 0 −8 X X X 1 0 1 1 1 −9 X X X 1 0 1 1 0 −10 X X X 1 0 1 0 1 −11 X X X 1 0 1 0 0 −12 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 65 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER 10.3.31.1 Definition Table 73 Subaddress 36 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 X X X SYSCL1(3) SYSCL0(3) SYSOUT(4) I2SFORM(5) I2SOUT(6) Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 3. System clock frequency select; see Table 74. 4. System clock output on/off; see Table 75. 5. Serial output format; see Table 75. 6. I2S-bus outputs on/off; see Table 75. Table 74 System clock frequency select B4 B3 SYSCLK OUTPUT FREQUENCY (MHz) 0 0 256fs 8.192 0 1 384fs 12.288 1 0 512fs 16.384 1 1 768fs 24.576 Table 75 Description of Table 73 NAME HIGH/LOW FUNCTION I2SOUT HIGH Enables the output of serial audio data (2 pins) plus serial bit clock and word select in a format determined by the I2SFORM bit. The TDA9875 is then an I2S-bus master. LOW the outputs mentioned will be 3-stated, thereby improving the EMC performance HIGH an MSB-aligned, MSB-first output format is selected, i.e. a level change at the word select pin indicates the beginning of a new audio sample LOW the standard I2S-bus output format is selected HIGH enables the output of a system (or master) clock signal at pin SYSCLK LOW the output will be off, thereby improving the EMC performance I2SFORM SYSOUT 1998 Feb 13 66 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.32 I2S1 OUTPUT SELECT REGISTER 10.3.32.1 Description This register is used to define both the signal source to be output at I2S1 and the mode of the digital matrix for signal selection. 10.3.32.2 Definition Table 76 Subaddress 37 (notes 1 and 2) MSB LSB B7 B6 X B5 B4 B3 see Table 78 B2 B1 X B0 see Table 77 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. Table 77 Signal source (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 FM output 0 0 1 NICAM output 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC output 1 0 1 AVL output 1 1 0 Auxiliary output 1 1 1 Main output Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 78 Bits B6 to B4 (note 1) B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 X X L+R -------------2 L+R -------------2 Note 1. X = don’t care. 1998 Feb 13 67 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.33 I2S1 INPUT LEVEL ADJUST REGISTER 10.3.33.1 Description This register is used to adjust the input level at the I2S1 interface. Left and right signal channel are treated identically. 10.3.33.2 Definition Table 79 Subaddress 38 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 68 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.34 I2S1 OUTPUT LEVEL ADJUST REGISTER 10.3.34.1 Description This register is used to adjust the output level at the I2S1 interface. Left and right signal channel are treated identically. 10.3.34.2 Definition Table 80 Subaddress 39 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 69 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.35 I2S2 OUTPUT SELECT REGISTER 10.3.35.1 Description This register is used to define both the signal source to be output at I2S2 and the mode of the digital matrix for signal selection. 10.3.35.2 Definition Table 81 Subaddress 40 (notes 1 and 2) MSB LSB B7 B6 X B5 B4 B3 see Table 83 B2 B1 X B0 see Table 82 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. Table 82 Signal source (note 1) B2 B1 B0 SIGNAL SOURCE 0 0 0 FM output 0 0 1 NICAM output 0 1 0 I2S1 input 0 1 1 I2S2 input 1 0 0 ADC output 1 0 1 AVL output 1 1 0 Auxiliary output 1 1 1 Main output Note 1. The Main and Auxiliary channel outputs will not contain the beeper signal. Table 83 Bits B6 to B4 (note 1) B6 B5 B4 L OUTPUT R OUTPUT 0 0 0 L input R input 0 0 1 L input L input 0 1 0 R input R input 0 1 1 R input L input 1 X X L+R -------------2 L+R -------------2 Note 1. X = don’t care. 1998 Feb 13 70 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.36 I2S2 INPUT LEVEL ADJUST REGISTER 10.3.36.1 Description This register is used to adjust the input level at the I2S2 interface. Left and right signal channel are treated identically. 10.3.36.2 Definition Table 84 Subaddress 41 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 71 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.37 I2S2 OUTPUT LEVEL ADJUST REGISTER 10.3.37.1 Description This register is used to adjust the output level at the I2S2 interface. Left and right signal channel are treated identically. 10.3.37.2 Definition Table 85 Subaddress 42 (note 1) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GAIN SETTING (dB) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 (note 2) −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 mute Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 1998 Feb 13 72 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.38 BEEPER FREQUENCY CONTROL REGISTER 10.3.38.1 Description This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main and Auxiliary channel output DAC. Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than the 390 Hz beep. 10.3.38.2 Definition Table 86 Subaddress 43 (notes 1 and 2) MSB LSB B7 B6 B5 B4 B3 B2 B1 B0 GENERATED FREQUENCY (Hz) X X X X X 1 1 1 25000 X X X X X 1 1 0 7040 X X X X X 1 0 1 3580 X X X X X 1 0 0 1770 X X X X X 0 1 1 1270 X X X X X 0 1 0 900 X X X X X 0 0 1 640 X X X X X 0 0 0 390 Notes 1. X = don’t care. 2. The default setting at power-up is 00000000. 10.3.39 BEEPER VOLUME CONTROL REGISTER 10.3.39.1 Description This register is used to set the beeper volume. The gain setting is relative to digital full-scale at the input to the Main and Auxiliary channel output DACs. The beeper volume is independent of any other volume setting. The beeper signal is added to the Main and Auxiliary channel output signals in the 2 × fs domain. The beeper volume should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to avoid output signal distortion due to overload. 1998 Feb 13 73 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.39.2 Definition Table 87 Subaddress 44 (note 1) MSB LSB GAIN SETTING (dB) B7 B6 B5 B4 B3 B2 B1 B0 X X 0 0 0 0 0 0 0 X X 1 1 1 1 1 1 −3 X X 1 1 1 1 1 0 −6 X X 1 1 1 1 0 1 −9 X X 1 1 1 1 0 0 −12 X X 1 1 1 0 1 1 −15 X X 1 1 1 0 1 0 −18 X X 1 1 1 0 0 1 −21 X X 1 1 1 0 0 0 −24 X X 1 1 0 1 1 1 −27 X X 1 1 0 1 1 0 −30 X X 1 1 0 1 0 1 −33 X X 1 1 0 1 0 0 −36 X X 1 1 0 0 1 1 −39 X X 1 1 0 0 1 0 −42 X X 1 1 0 0 0 1 −45 X X 1 1 0 0 0 0 −48 X X 1 0 1 1 1 1 −51 X X 1 0 1 1 1 0 −54 X X 1 0 1 1 0 1 −57 X X 1 0 1 1 0 0 −60 X X 1 0 1 0 1 1 −63 X X 1 0 1 0 1 0 −66 X X 1 0 1 0 0 1 −69 X X 1 0 1 0 0 0 −72 X X 1 0 0 1 1 1 −75 X X 1 0 0 1 1 0 −78 X X 1 0 0 1 0 1 −81 X X 1 0 0 1 0 0 −84 X X 1 0 0 0 1 1 −87 X X 1 0 0 0 1 0 −90 X X 1 0 0 0 0 1 −93 X X 1 0 0 0 0 0 mute (note 2) Notes 1. X = don’t care. 2. The default setting at power-up is 00100000. 1998 Feb 13 74 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 10.3.40 BASS BOOST CONTROL REGISTER 10.3.40.1 Description This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function must be used with care in order to avoid clipping distortion at high volume settings. More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then has full control over this 2nd-order filter and can, within limits, realize bass equalizers with arbitrary centre frequencies, Q factors and boost/cut settings. 10.3.40.2 Definition Table 88 Subaddress 45 (note 1; see Table 89) MSB B7 LSB B6 B5 B4 B3 B2 B1 B0 Note 1. The default setting at power-up is 00000000. Table 89 Gain setting B7, B3 B6, B2 B5, B1 B4, B0 GAIN SETTING (dB) CORNER FREQUENCY (Hz) 1 0 1 0 20 350 1 0 0 1 18 350 1 0 0 0 16 350 0 1 1 1 14 350 0 1 1 0 12 350 0 1 0 1 10 350 0 1 0 0 8 350 0 0 1 1 6 350 0 0 1 0 4 350 0 0 0 1 2 350 0 0 0 0 0 350 1998 Feb 13 75 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.4 TDA9875 Slave transmitter mode As a slave transmitter, the TDA9875 provides 13 registers with status information and data, a part of which is for Philips internal purposes only. These registers can be accessed by means of subaddresses. Table 90 General format for reading data from the TDA9875 S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA NAm P Table 91 Explanation of Tables 90 and 92 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge (by the slave) SUBADDRESS address of register to read from Sr repeated START condition 1 data direction bit (read from device) DATA data byte read from register NAm not acknowledge (by the master) Am acknowledge (by the master) P STOP condition Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the TDA9875. In this situation, the subaddress is automatically incremented after each data byte, which results in reading the sequence of data bytes from successive register locations, starting at SUBADDRESS. Table 92 Format of a transmission using automatic incrementing of subaddresses S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA BYTE Am(1) DATA NAm P Note 1. n data bytes with auto-increment of subaddresses. Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master). The subaddresses ‘wrap around’ from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF in hexadecimal notation. 1998 Feb 13 76 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Table 93 Overview of the slave transmitter registers (note 1) DATA SUBADDRESS (DECIMAL) MSB 0 s FUNCTION LSB s s s s s s s device status (power-on, identification, etc.) 1 s s s s s s s s NICAM status 2 e e e e e e e e NICAM error count 3 d d d d d d d d additional data (LSB) 4 c c X c c d d d additional data (MSB) 5 l l l l l l l l level read-out (MSB) 6 l l l l l l l l level read-out (LSB) 7 X X X c c c c c SIF level 251 a a a a a a a a test register 3 252 a a a a a a a a test register 2 253 a a a a a a a a test register 1 254 d d d d d d d d device identification code 255 s s s s s s s s software identification code Note 1. X indicates a bit that has not yet been assigned to a function. Its meaning is ‘don’t care’, its return value is a zero. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of registers for the identification of individual members and some key parameters in a family of devices. A detailed description of the slave transmitter registers is given in below: 10.4.1 DEVICE STATUS REGISTER 10.4.1.1 Definition Table 94 Subaddress 0 BIT NAME DESCRIPTION 7 (MSB) P2IN input from port 2 6 P1IN input from port 1 5 RSSF reserve sound switching flag 4 AMSTAT auto-mute status 3 VDSP identification of NICAM sound 2 IDDUA identification of FM dual sound 1 IDSTE identification of FM stereo 0 (LSB) X don’t care 1998 Feb 13 77 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.4.1.2 TDA9875 Description Table 95 Description of Table 94 NAME HIGH/LOW IDSTE HIGH FUNCTION this bit is HIGH if an FM stereo signal has been identified LOW IDDUA − VDSP HIGH LOW This bit is HIGH if an FM dual-language signal has been identified. When neither IDSTE nor IDDUA are set, the received signal is assumed to be FM mono. indicates that digital transmission is a sound source (NICAM) the transmission is either data or currently undefined format (NICAM) AMSTAT − if this bit is HIGH, it indicates that the auto-muting function has switched from NICAM to the program of the first sound carrier (i.e. FM mono or AM in NICAM L systems) RSSF HIGH This bit is a copy of the C4 bit in the NICAM status register. It indicates that the FM (or AM for standard L) sound matches the digital transmission and auto-muting should be enabled. LOW − P1IN, P2IN 10.4.2 auto-muting should be disabled, as analog and digital sound are different these bits reflect the status of the corresponding general purpose port pins, see Section 10.3.2 NICAM STATUS REGISTER 10.4.2.1 Definition Table 96 Subaddress 1 BIT NAME DESCRIPTION 7 (MSB) C4 NICAM application control bits 6 C3 5 C2 4 C1 3 OSB synchronization bit 2 CFC configuration change 1 S/MB identification of NICAM stereo 0 (LSB) D/SB identification of NICAM dual mono 1998 Feb 13 78 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.4.2.2 TDA9875 Description Table 97 Description of Table 96 NAME HIGH/LOW D/SB HIGH S/MB HIGH FUNCTION if this bit is HIGH it indicates dual mono mode LOW if this bit is HIGH it indicates stereo mode LOW CFC HIGH OSB C1, C2, C3, C4 LOW if this bit is HIGH, it indicates a configuration change at the 16 frame (C0) boundary HIGH indicates that the device has both frame and C0 (16 frame) synchronization LOW the audio output from the NICAM part should be digital silence HIGH these bits correspond to the control bits C1 to C4 in the NICAM transmission LOW 10.4.2.3 Notes The TDA9875 does not support the Extended Control Modes. Therefore, the program of the first sound carrier (i.e. FM mono or AM) is selected for reproduction in case bit C3 is set HIGH, independent of bit AMUTE in the NICAM configuration register being set or not. When a NICAM transmitter is switched off, the device will lose synchronization. In this situation the program of the first sound carrier is selected for reproduction, independent of bit AMUTE being set or not. 10.4.3 NICAM ERROR COUNT REGISTER 10.4.3.1 Description Bits B7 to B0 contain the number of errors occurring in the previous 128 ms period. The register is updated every 128 ms. 10.4.3.2 Definition Table 98 Subaddress 2 MSB B7 1998 Feb 13 LSB B6 B5 B4 B3 79 B2 B1 B0 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.4.4 TDA9875 ADDITIONAL DATA REGISTERS 10.4.4.1 Description These two bytes provide information on the additional data bits. ADBYTE0 is stored at subaddress 3. 10.4.4.2 Definition Table 99 Subaddress 3 BIT NAME 7 (MSB) AD7 6 AD6 5 AD5 4 AD4 3 AD3 2 AD2 1 AD1 0 (LSB) AD0 BIT NAME 7 (MSB) OVW Table 100 Subaddress 4 6 SAD 5 X (don’t care) 4 CI1 3 CI2 2 AD10 1 AD9 0 (LSB) AD8 Table 101 Description of Tables 99 and 100 NAME HIGH/LOW AD10 to AD0 − comprise the additional data word CI1, CI2 − these are CI bits decoded by majority logic from the parity checks of the last ten samples in a frame SAD HIGH new additional data is written into the IC LOW reset, when the additional data bits are read OVW 1998 Feb 13 − FUNCTION if this bit is HIGH, new additional data bits are written to the IC without the previous bits being read 80 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.4.5 10.4.5.1 TDA9875 When the SIF AGC is off, this register returns the contents of the AGC gain register. LEVEL READ-OUT REGISTERS Description These two bytes constitute a word that provides data from a location that has been specified with the monitor select register. The most significant byte of the data is stored at subaddress 5. 10.4.6.2 If peak-level monitoring has been selected, the peak-level monitoring register is cleared and monitoring resumes after its contents has been transferred to these two bytes. B7 Definition Table 104 Subaddress 7 (note 1) MSB LSB B6 B5 B4 B3 B2 B1 B0 Note 1. Bits B5, B6 and B7 are don’t care. 10.4.5.2 Definition 10.4.7 Table 102 Subaddress 5 10.4.7.1 BIT TEST REGISTER 3 Description This register contains, as a binary number, the highest memory address used for the Coefficient RAM (CRAM, expert mode). 7 (most significant bit or sign bit) 6 5 The first version will have the identification 01111111. 4 3 10.4.7.2 2 Table 105 Subaddress 251 1 Definition MSB 0 B7 LSB B6 B5 B4 B3 B2 B1 B0 Table 103 Subaddress 6 10.4.8 TEST REGISTER 2 BIT 10.4.8.1 7 Description This register contains, as a binary number, the highest subaddress used for slave receiver registers. 6 5 The first version will have the identification 00101101. 4 3 10.4.8.2 Definition 2 Table 106 Subaddress 252 1 MSB 0 (least significant bit) B7 10.4.6 10.4.6.1 LSB B6 B5 B4 B3 B2 B1 B0 SIF LEVEL REGISTER 10.4.9 Description 10.4.9.1 When the SIF AGC is on, bits B4 to B0 of this register contain a number that gives an indication of the SIF input level. That number can be interpreted in the same way as the AGC gain register setting (see Section 10.3, subaddress 0), i.e., if the SIF AGC were set to a fixed gain and the same number loaded into the AGC gain register, the current SIF input signal level would generate an SIF ADC output close to full-scale. 1998 Feb 13 TEST REGISTER 1 Description This register contains, as a binary number, the highest subaddress used for slave transmitter (status) registers. The first version will have the identification 00000111. 81 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) 10.4.9.2 Definition 10.4.11.2 Definition Table 107 Subaddress 253 Table 109 Subaddress 255 MSB B7 B6 B5 TDA9875 B4 B3 B2 B1 LSB MSB B0 B7 LSB B6 B5 B4 B3 B2 B1 B0 10.4.10 DEVICE IDENTIFICATION CODE 10.5 10.4.10.1 Description In addition to the slave receiver and slave transmitter modes previously described, there is a special ‘expert’ mode that gives direct write access to the internal CRAM of the DSP. There will be several devices in the digital TV sound processor family, with TDA9875 being the first member. This byte is used to identify the individual family members purely for Philips internal use. In this mode, transferred data contain 12-bit-wide coefficients. As those coefficients bypass on-chip coefficient look-up tables for many functions, they directly influence the processing of signals within the DSP. The first version will have the identification 00000000. 10.4.10.2 Definition This mode must be used with great care. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses. Table 108 Subaddress 254 MSB B7 LSB B6 B5 B4 B3 B2 B1 Expert mode B0 10.4.11 SOFTWARE IDENTIFICATION CODE 10.4.11.1 Description It is likely that during the life time of this family of devices several versions of the DSP software will be made, e.g., to accommodate new application concepts, respond to customer wishes, etc. This byte is used to identify the different releases purely for Philips internal use. The first version will have the identification 00000000. Table 110 General format for entering the expert mode and writing coefficients into the TDA9875 S SLAVE ADDRESS 0 ACK 10000000 ACK CRAM ADDRESS ACK Table 111 Explanation of Table 110 BIT FUNCTION S START condition SLAVE ADDRESS 7-bit device address 0 data direction bit (write to device) ACK acknowledge 10000000 pattern to enter the expert mode CRAM ADDRESS start address of coefficient RAM to write to DATA data byte containing part of a coefficient P STOP condition 1998 Feb 13 82 DATA ACK DATA ACK P Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 As the coefficients do not fit into one data byte, they have to be split and arranged (see Table 112). The most significant bit is transferred first. Table 112 General format (notes 1, 2 and 3) BYTE DATA DESCRIPTION 1. data byte a a a a a a a a 2 MST of 1st coefficient 2. data byte a a a a X X X X 1 LST of 1st coefficient Notes 1. X = don’t care. 2. MST = most significant third. 3. LST = least significant third. The general format described in Table 112 shows the minimum number of data bytes required, i.e. two bytes for the transfer of a single coefficient. Should more than one coefficient be sent, then the CRAM address will be automatically incremented after each coefficient, resulting in writing the sequence of coefficients into successive memory locations, starting at CRAM ADDRESS. A transmission can start with any valid CRAM address. If two coefficients are to be transferred, they are arranged as shown in Table 113. Table 113 Transfer of two coefficients BYTE DATA DESCRIPTION 1 data byte a a a a a a a a 2 MST of 1st coefficient 2 data byte a a a a b b b b 1 LST of 1st coefficient + 1 MST of 2nd coefficient 3 data byte b b b b b b b b 2 LST of 2nd coefficient With any odd number of coefficients to be transferred, the least significant nibble of the last byte is regarded as containing don’t care data. To make efficient and correct use of the expert mode, it is recommended to transfer all coefficients for any one function in a single transmission. As the transfer of coefficients cannot be accomplished within one audio sample period, it is necessary that received coefficients be buffered and made active all at the same time to avoid audio signal transients. The receive buffer is designed to store up to 8 coefficients in addition to the CRAM address. Each byte that fits into the buffer is acknowledged with ACK (acknowledge). If an attempt is made to write more coefficients than the buffer can store, the device acknowledges with NACK (not acknowledge) and any further coefficients are ignored. Coefficients that are already in the receive buffer remain intact. There is no checking of memory addresses and the automatic incrementing of addresses does not stop at the highest used CRAM address. The user of this expert mode must be fully acquainted with the relevant procedures. An expert mode transfers ends when the I2C-bus STOP condition or a repeated START condition has been detected. Only those coefficients that have been received during the last transmission will then be copied from the buffer to the CRAM. The feature interface of the TDA9875 contains two serial audio inputs and outputs and associated clock signals. It can be used to supply, for example, audio signals from received TV programs to a digital audio output device (AES/EBU format), or import serial audio signals from other sources for reproduction through the TV set’s 1998 Feb 13 More information concerning the functions of this device, such as filter structures, the number of coefficients per function, their default values, memory addresses, etc., can be supplied on request at a later date. 11 I2S-BUS DESCRIPTION 83 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 Apart from just feeding a digital audio device, such as a DAC or an AES/EBU transmitter, the serial data outputs can be connected directly to the serial inputs (loop-back connection) or first to an external device, e.g. a feature DSP such as the SAA7710 and then back to the serial inputs. In all of these configurations, the SCK and WS clocks will be generated by the TDA9875, which then is the I2S-bus master. loudspeaker and/or headphone channels. Apart from such simple data input or output, it is also possible to run audio signals through an external DSP, which performs some additional functions, such as room simulation, Dolby Surround Pro Logic etc. and feed those signals back into the loudspeaker and/or headphone channels of the TDA9875. Two serial audio formats are supported at the feature interface, i.e. the I2S-bus format and a very similar MSB-aligned format. The difference is illustrated in Fig.7. The serial data inputs, SDI1 and SDI2, are active at all times, independent of the serial data outputs being on or off. When the serial data outputs are off (either after power-up or via the appropriate I2C-bus command) serial data and clocks WS and SCK from a separate digital audio source can be fed into the TDA9875, be processed and output in accordance with internal selector positions, provided that the following criteria are met: In both formats the left audio channel of a stereo sample pair is output first and is placed on the serial data line (SDI for input, SDO for output) when the word select line (WS) is LOW. Data is written at the trailing edge of SCK and read at the leading edge of SCK. The most significant bit is sent first. At power-up, the outputs of the feature interface are 3-stated to reduce EMC and allow for combinations with other ICs. If output is desired, it has to be activated by means of an I2C-bus command. • 32 kHz audio sample frequency When the output is enabled, the serial audio data can be taken from pins SDO1 and SDO2. Depending on the signal source, switch and matrix positions, the output can be either mono, stereo or dual language sound on either output. In such cases, the external source is the I2S-bus master and the TDA9875 is the I2S-bus slave. • 32 clock bits per sample • External timing and data synchronized to TDA9875. To support synchronization of external devices or as a master clock for them, a symmetrical system clock output, SYSCLK, is available from the TDA9875. At power-up it is off. It can be enabled and the output frequency set via an I2C-bus command. Available output frequencies are 8.192, 12.288, 16.384 and 24.576 MHz. The word select output is clocked with the audio sample frequency at 32 kHz. The serial clock output (SCK) is clocked at a frequency of 2.048 MHz. This means, that there are 64 clock pulses per pair of stereo output samples, or 32 clock pulses per sample. Depending again on the signal source, the number of significant bits on the serial data outputs, SDO1 and SDO2, is between 14 and 18. 1998 Feb 13 84 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 handbook, full pagewidth SCK WS SD LSB MSB LSB MSB MGK112 one sample a. I2S-bus format. handbook, full pagewidth SCK WS SD LSB MSB LSB MSB MGK113 one sample b. MSB-aligned format. Fig.7 Serial audio interface formats. 1998 Feb 13 85 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 12 EXTERNAL COMPONENTS handbook, full pagewidth PCLK PCLK NICAM NICAM data ADDR1 ADDR1 SCL SCL SDA SDA VSSA1 R1 +5 V 10 Ω VDDA1 C1 4.7 µF R2 Iref 1 64 2 63 P1 C2 SIF2 SIFSAT C3 47 pF Vref1 100 nF C4 SIF1 SIFTV 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 47 pF ADDR2 ADDR2 VSSD1 +5 V 1.5 Ω D1 L1 3.3 µH VDDD1 R3 C5 47 µF C6 1 µF C7 R4 39 kΩ XTALO 24.576 MHz Vtune R5 10 kΩ P2 P2 C10 33 nF C9 330 nF SYSCLK SYSCLK R15 20 kΩ 13 52 14 51 15 50 16 49 LOL SCK SCK WS WS SDO2 SDO2 SDO1 SDO1 SDI2 SDI2 SDI1 SDI1 TEST1 MONOIN MONOIN 470 nF TEST2 C12 EXTIR EXTR 470 nF C13 EXTL VDDA3 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 10 nF C20 10 nF 2.2 µF C21 47 µF C23 10 nF 2.2 µF AUXOR 38 28 37 EXTIL 36 29 30 35 31 34 33 32 10 nF C27 C28 10 nF 47 µF C29 C30 2.2 µF Vref3 AUXL C24 AUXR SC2OL SCOR2 VSSA4 +5 V 10 Ω C22 2.2 µF PCAPR SCOL2 MAINR R6 C26 PCAPL SC2OR 2.2 µF VSSD2 C31 SCOL1 C32 2.2 µF 2.2 µF C33 SCOR1 Vref2 SC1OL SC1OR 47 µF CAPR1 C34 220 pF CAPR2 VSSA2 CAPL2 C35 220 pF CAPL1 Vref(n) R8 C36 47 µF R9 R10 C37 10 Ω 47 µF +5 V C38 SCIL2 R11 SC2IL SCIR2 R12 330 nF C39 SC2IR 15 kΩ VSSG R13 SCIL1 330 nF C40 SC1IL SCIR1 R14 15 kΩ 330 nF C41 15 kΩ Fig.8 Schematic for measurements. 270 Ω 270 Ω VDDA2 MGK114 86 C19 2.2 µF 10 nF C25 VSSA3 Vref(p) 27 MAINL C18 AUXOL 470 nF 1998 Feb 13 LINEL C17 MOR 15 kΩ C11 LINER 2.2 µF MOL +5 V C16 TDA9875 C8 33 pF XTALI 33 pF BB135 CRESET C15 LOR 47 µF 1.5 Ω C14 2.2 µF 10 kΩ P1 R7 VDDD2 SC1IR 330 nF Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) TDA9875 13 PACKAGE OUTLINE seating plane SDIP64: plastic shrink dual in-line package; 64 leads (750 mil) SOT274-1 ME D A2 A L A1 c e Z b1 (e 1) w M MH b 33 64 pin 1 index E 1 32 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 5.84 0.51 4.57 1.3 0.8 0.53 0.40 0.32 0.23 58.67 57.70 17.2 16.9 1.778 19.05 3.2 2.8 19.61 19.05 20.96 19.71 0.18 1.73 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-10-13 95-02-04 SOT274-1 1998 Feb 13 EUROPEAN PROJECTION 87 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 14 SOLDERING 14.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.3 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 14.2 TDA9875 Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Feb 13 88 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) NOTES 1998 Feb 13 89 TDA9875 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) NOTES 1998 Feb 13 90 TDA9875 Philips Semiconductors Preliminary specification Digital TV Sound Processor (DTVSP) NOTES 1998 Feb 13 91 TDA9875 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/1200/02/pp92 Date of release: 1998 Feb 13 Document order number: 9397 750 03003