3-Channel, Isolated, Sigma-Delta ADC with SPI ADE7912/ADE7913 Data Sheet FEATURES TYPICAL APPLICATIONS CIRCUIT NEUTRAL PHASE PHASE PHASE A C B 3.3V V1P VM IM PHASE A IP ADE7912/ ADE7913 V2P GNDISO_A GNDMCU 3.3V VM 3.3V IM PHASE B ADE7912/ ADE7913 IP V2P GNDISO_B GNDMCU 3.3V V1P VM IM PHASE C IP ADE7912/ ADE7913 SYSTEM MICROCONTROLLER V1P GNDMCU V2P GNDMCU GNDISO_C 3.3V V1P VM NEUTRAL LINE IM ADE7912/ ADE7913 IP LOAD (OPTIONAL) V2P GNDISO_N EARTH GNDMCU 11115-001 APPLICATIONS Shunt-based polyphase meters Power quality monitoring Solar inverters Process monitoring Protective devices Isolated sensor interfaces Industrial PLCs ISOLATION BARRIER SPI INTERFACE Two (ADE7912) or three (ADE7913) 24-bit isolated, Σ-Δ analog-to-digital converters (simultaneously sampling ADCs) Integrated isoPower, isolated dc-to-dc converter On-chip temperature sensor 4-wire SPI serial interface Up to 4 ADE7912/ADE7913 devices clocked from a single crystal or an external clock Synchronization of multiple ADE7912/ADE7913 devices ±31.25 mV peak input range for current channel ±500 mV peak input range for voltage channels Reference drift: 10 ppm/°C typical Single 3.3 V supply 20-lead, wide-body SOIC package with 8.3 mm creepage Operating temperature: −40°C to +85°C Safety and regulatory approvals (pending) UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A IEC 61010-1: 400 V rms VDE certificate of conformity DIN VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 846 V peak Figure 1. GENERAL DESCRIPTION The ADE7912/ADE79131 are isolated, 3-channel Σ-Δ ADCs for polyphase energy metering applications using shunt current sensors. Data and power isolation are based on the Analog Devices, Inc., iCoupler® technology. The ADE7912 features two 24-bit ADCs, and the ADE7913 features three ADCs. The current ADC provides a 67 dB signal-to-noise ratio over a 3 kHz signal bandwidth, whereas the voltage ADCs provide a SNR of 72 dB over the same bandwidth. One channel is dedicated to measuring the voltage across a shunt when the shunt is used for current sensing. Up to two additional channels are dedicated to measuring voltages, which are usually sensed using resistor dividers. One voltage channel can be used to measure the temperature of the die via an internal sensor. The ADE7913 includes three channels: one current and two voltage channels. The ADE7912 has one voltage channel but is otherwise identical to the ADE7913. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; 7,558,080. Other patents are pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADE7912/ADE7913 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Temperature Sensor ................................................................... 20 Applications ....................................................................................... 1 Protecting the Integrity of Configuration Registers .............. 21 Typical Applications Circuit............................................................ 1 CRC of Configuration Registers............................................... 21 General Description ......................................................................... 1 ADE7912/ADE7913 Status ....................................................... 21 Revision History ............................................................................... 2 Insulation Lifetime ..................................................................... 22 Functional Block Diagrams ............................................................. 4 Applications Information .............................................................. 23 Specifications..................................................................................... 5 ADE7912/ADE7913 in Polyphase Energy Meters ................. 23 Regulatory Approvals (Pending) ................................................ 7 ADE7912/ADE7913 Clock ....................................................... 25 Insulation and Safety Related Specifications ............................ 7 SPI-Compatible Interface .......................................................... 26 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 7 Synchronizing Multiple ADE7912/ADE7913 Devices .......... 27 Power Management ........................................................................ 31 Timing Characteristics ................................................................ 8 DC-to-DC Converter................................................................. 31 Absolute Maximum Ratings.......................................................... 10 Magnetic Field Immunity ......................................................... 32 Thermal Resistance .................................................................... 10 Power-Up and Initialization Procedures ................................. 33 ESD Caution ................................................................................ 10 Hardware Reset ........................................................................... 36 Pin Configuration and Function Descriptions ........................... 11 Software Reset ............................................................................. 36 Typical Performance Characteristics ........................................... 13 Power-Down Mode .................................................................... 36 Test Circuit ...................................................................................... 15 Layout Guidelines ........................................................................... 37 Terminology .................................................................................... 16 ADE7913 Evaluation Board ...................................................... 39 Theory of Operation ...................................................................... 18 ADE7912/ADE7913 Version .................................................... 39 Analog Inputs .............................................................................. 18 Register List ..................................................................................... 41 Analog-to-Digital Conversion .................................................. 18 Outline Dimensions ....................................................................... 44 Reference Circuit ........................................................................ 20 Ordering Guide .......................................................................... 44 CRC of ADC Output Values ..................................................... 20 REVISION HISTORY 11/13—Revision 0: Initial Version Rev. 0 | Page 2 of 44 Data Sheet ADE7912/ADE7913 The ADE7912/ADE7913 include isoPower®, an integrated, isolated dc-to-dc converter. Based on the Analog Devices iCoupler technology, the dc-to-dc converter provides the regulated power required by the first stage of the ADCs at a 3.3 V input supply. isoPower eliminates the need for an external dc-to-dc isolation block. The iCoupler chip scale transformer technology is also used to isolate the logic signals between the first and second stages of the ADC. The result is a small form factor, total isolation solution. The ADE7912/ADE7913 configuration and status registers are accessed via a bidirectional SPI serial port for easy interfacing with microcontrollers. The ADE7912/ADE7913 can be clocked from a crystal or an external clock signal. To minimize the system bill of materials, the master ADE7912/ADE7913 can drive the clocks of up to three additional ADE7912/ADE7913 devices. Multiple ADE7912/ADE7913 devices can be synchronized to sample at the same moment and provide coherent outputs. The ADE7912/ADE7913 are available in a 20-lead, Pb-free, wide-body SOIC package with 8.3 mm creepage. Rev. 0 | Page 3 of 44 ADE7912/ADE7913 Data Sheet FUNCTIONAL BLOCK DIAGRAMS ISOLATION BARRIER 2 8 LDO 3 V2P 20 POWER ISOLATION V1P 18 DATA 7 IP ADC 9 REF ADC 17 DATA DATA ISOLATION 6 IM GND LDO 5 4 VDD TEMP SENSOR ADC VM 19 CLOCK CLOCK DIGITAL BLOCK AND SPI PORT 16 15 14 13 CS SCLK MOSI MISO XTAL2 XTAL1 12 CLKOUT/ DREADY 11 GND VREF 10 11115-003 GNDISO GNDISO ADE7912 1 VDDISO Figure 2. ADE7912 Functional Block Diagram ISOLATION BARRIER GNDISO LDO V2P VM V1P IM IP REF GNDISO ADE7913 1 2 8 3 5 4 20 POWER ISOLATION 9 VDD GND LDO TEMP SENSOR 18 ADC DATA ADC ADC CLOCK 17 DATA DATA ISOLATION 6 7 19 CLOCK DIGITAL BLOCK AND SPI PORT 16 15 14 13 CS SCLK MOSI MISO XTAL2 XTAL1 12 CLKOUT/ DREADY 11 GND VREF 10 Figure 3. ADE7913 Functional Block Diagram Rev. 0 | Page 4 of 44 11115-002 VDDISO Data Sheet ADE7912/ADE7913 SPECIFICATIONS VDD = 3.3 V ± 10%, GND = 0 V, on-chip reference, XTAL1 = 4.096 MHz, TMIN to TMAX = −40°C to +85°C, TA = 25°C (typical). Table 1. Parameter ANALOG INPUTS 1 Pseudo Differential Signal Voltage Range Between IP and IM Pins Pseudo Differential Signal Voltage Range Between V1P and VM Pins and Between V2P and VM Pins Maximum VM and IM Voltage Crosstalk Input Impedance to GNDISO (DC) IP, IM, V1P, and V2P Pins VM Pin Current Channel ADC Offset Error Voltage Channels ADC Offset Error ADC Offset Drift over Temperature Gain Error Gain Drift over Temperature Min Typ Max Unit Test Conditions/Comments −31.25 +31.25 mV peak IM pin connected to GNDISO −500 +500 mV peak Pseudo differential inputs between V1P and VM pins and between V2P and VM pins; VM pin connected to GNDISO +25 −90 mV dB −105 dB −25 AC Power Supply Rejection, PSR −90 kΩ kΩ mV mV ppm/°C % ppm/°C ppm/°C dB DC Power Supply Rejection, PSR −80 dB ±5 °C 67 68 72 74 66 68 72 73 −79 −78 −82 −82 83 83 85 85 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz 72 74 77 79 dBFS dBFS dBFS dBFS ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz TEMPERATURE SENSOR Accuracy WAVEFORM SAMPLING—CURRENT CHANNEL1 Signal-to-Noise Ratio, SNR Signal-to-Noise-and-Distortion Ratio, SINAD Total Harmonic Distortion, THD Spurious-Free Dynamic Range, SFDR VOLTAGE CHANNELS1 Signal-to-Noise Ratio, SNR 480 240 IP and IM inputs set to 0 V (GNDISO) when V1P and V2P inputs at full scale V2P and VM inputs set to 0 V (GNDISO) when IP and V1P inputs at full scale; V1P and VM inputs set to 0 V (GNDISO) when IP and V2P inputs at full scale −2 −35 −500 −4 −135 −65 +500 +4 +135 +65 Rev. 0 | Page 5 of 44 V2 channel applies to the ADE7913 only V1 channel only Current channel V1 and V2 channels VDD = 3.3 V + 120 mV rms (50 Hz/100 Hz), IP = V1P = V2P = GNDISO VDD = 3.3 V ± 330 mV dc, IP = 6.25 mV rms, V1P = V2P = 100 mV rms ADE7912/ADE7913 Parameter Signal-to-Noise-and-Distortion Ratio, SINAD Data Sheet Min Typ 72 74 77 78 −83 −83 −85 −85 86 86 87 87 Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 3.6 45 4.096 50 4.21 55 MHz % Total Harmonic Distortion, THD Spurious-Free Dynamic Range, SFDR CLKIN2 Input Clock Frequency, CLKIN CLKIN Duty Cycle XTAL1 Logic Inputs Input High Voltage, VINH Input Low Voltage, VINL XTAL1 Total Capacitance3 XTAL2 Total Capacitance3 CLKOUT Delay from XTAL14 LOGIC INPUTS—MOSI, SCLK, CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS—CLKOUT/DREADY AND MISO Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY VDD Pin IDD 2.4 100 V V pF pF ns 0.8 15 10 V V nA pF 0.4 V V 0.8 40 40 2.4 2.5 2.97 12.5 2.7 50 3.63 19 3 V mA mA μA 1 Test Conditions/Comments ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz ADC_FREQ = 8 kHz, BW = 3300 Hz ADC_FREQ = 8 kHz, BW = 2000 Hz ADC_FREQ = 2 kHz, BW = 825 Hz ADC_FREQ = 2 kHz, BW = 500 Hz All specifications for CLKIN = 4.096 MHz ISOURCE = 800 μA ISINK = 2 mA For specified performance Minimum = 3.3 V − 10%; maximum = 3.3 V + 10% Bit 2 (PWRDWN_EN) in CONFIG register cleared to 0 Bit 2 (PWRDWN_EN) in CONFIG register set to 1 Bit 2 (PWRDWN_EN) in CONFIG register set to 1 and no CLKIN signal at XTAL1 pin See the Terminology section for a definition of the parameters. CLKIN is the internal clock of the ADE7912/ADE7913. It is the frequency at which the part is clocked at the XTAL1 pin. 3 XTAL1/XTAL2 total capacitances refer to the net capacitances on each pin. Each capacitance is the sum of the parasitic capacitance at the pin and the capacitance of the ceramic capacitor connected between the pin and GND. See the ADE7912/ADE7913 Clock section for more details. 4 CLKOUT delay from XTAL1 is the delay that occurs from a high to low transition at the XTAL1 pin to a synchronous high to low transition at the CLKOUT/DREADY pin when CLKOUT functionality is enabled. 2 Rev. 0 | Page 6 of 44 Data Sheet ADE7912/ADE7913 REGULATORY APPROVALS (PENDING) The ADE7912/ADE7913 are pending approval by the organizations listed in Table 2. Refer to Table 8 and the Insulation Lifetime section for more information about the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 2. Regulatory Approvals UL Recognized Under UL 1577 Component Recognition Program 1 Single Protection, 5000 V rms Isolation Voltage 1 2 CSA Approved under CSA Component Acceptance Notice 5A Basic insulation per IEC 61010-1, 400 V rms (564 V peak) maximum working voltage VDE Certified according to DIN VDE V 0884-10 2 (VDE V 0884-10):2006-12 Reinforced insulation, 846 V peak In accordance with UL 1577, each ADE7912/ADE7913 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 µA). In accordance with DIN V VDE V 0884-10, each ADE7912/ADE7913 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN VDE V 0884-10 (VDE V 0884-10):2006-12 approval. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 3. Critical Safety Related Dimensions and Material Properties Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(l01) Value 5000 8.3 Unit V rms mm Minimum External Tracking (Creepage) L(l02) 8.3 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >600 II mm V Test Conditions/Comments 1-minute duration Distance measured from input terminals to output terminals, shortest distance through air along the PCB mounting plane, as an aid to PCB layout Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation IEC 60112 Material group (DIN VDE 0110, 1/89, Table 1) DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS The ADE7912/ADE7913 are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. Table 4. VDE Characteristics Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Tests Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Maximum Junction Temperature Total Power Dissipation at 25°C Insulation Resistance at TS Test Conditions/Comments VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Symbol Characteristic Unit VIORM Vpd(m) I to IV I to IV I to III 40/105/21 2 846 1592 V peak V peak 1273 V peak 1018 V peak VIOTM VIOSM 6000 6000 V peak V peak TS PS RS 150 2.78 >109 °C W Ω Vpd(m) VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 4) VIO = 500 V Rev. 0 | Page 7 of 44 ADE7912/ADE7913 Data Sheet 3.0 SAFE LIMITING POWER (W) 2.5 2.0 1.5 1.0 0 0 50 100 150 AMBIENT TEMPERATURE (ºC) 200 11115-004 0.5 Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10 TIMING CHARACTERISTICS VDD = 3.3 V ± 10%, GND = 0 V, on-chip reference, CLKIN = 4.096 MHz, TMIN to TMAX = −40°C to +85°C. Table 5. SPI Interface Timing Parameters Parameter CS to SCLK Positive Edge SCLK Frequency 1 SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After SCLK Edge Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK Edge Data Output Fall Time Data Output Rise Time SCLK Rise Time SCLK Fall Time MISO Disable After CS Rising Edge CS High After SCLK Edge 1 Symbol tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDIS tSFS Minimum and maximum specifications are guaranteed by design. Rev. 0 | Page 8 of 44 Min 50 250 80 80 Max 5600 80 70 20 5 0 20 20 20 20 40 Unit ns kHz ns ns ns ns ns ns ns ns ns ns ns Data Sheet ADE7912/ADE7913 CS tSS tSFS SCLK tSL tSH tDAV tSR tSF tDIS MSB MISO INTERMEDIATE BITS LSB tDF tDR INTERMEDIATE BITS MSB IN MOSI LSB IN 11115-005 tDSU tDHD Figure 5. SPI Interface Timing 2mA 1.6V CL 50pF 800µA IOH 11115-006 TO OUTPUT PIN IOL Figure 6. Load Circuit for Timing Specifications Rev. 0 | Page 9 of 44 ADE7912/ADE7913 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Parameter VDD to GND Analog Input Voltage to GNDISO, IP, IM, V1P, V2P, VM Reference Input Voltage to GNDISO Digital Input Voltage to GND Digital Output Voltage to GND Common-Mode Transients1 Operating Temperature Industrial Range Storage Temperature Range Lead Temperature (Soldering, 10 sec)2 Rating −0.3 V to +3.7 V −2 V to +2 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V -100 kV/µs to +100 kV/µs THERMAL RESISTANCE θJA and θJC are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance −40°C to +85°C −65°C to +150°C 260°C Package Type 20-Lead SOIC_IC Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latchup or permanent damage. 2 Analog Devices recommends that reflow profiles used in soldering RoHS compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for the latest revision of this standard. 1 θJA 48.0 ESD CAUTION Table 8. Maximum Continuous Working Voltage Supporting a 50-Year Minimum Lifetime 1 Parameter AC Voltage, Bipolar Waveform DC Voltage, Basic Insulation 1 Max 564 600 Unit V peak V peak Applicable Certification All certifications, 50-year operation Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Rev. 0 | Page 10 of 44 θJC 6.2 Unit °C/W Data Sheet ADE7912/ADE7913 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDDISO 1 20 GNDISO 2 19 VDD V2P 3 18 CS VM 5 IM 6 ADE7912/ ADE7913 TOP VIEW (Not to Scale) 17 SCLK 16 MOSI 15 MISO IP 7 14 XTAL2 LDO 8 13 XTAL1 REF 9 12 CLKOUT/DREADY GNDISO 10 11 GND 11115-007 V1P 4 GND Figure 7. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 Mnemonic VDDISO 2, 10 GNDISO 3, 4, 5 V2P, V1P, VM 6, 7 IM, IP 8 LDO 9 REF 11, 20 12 GND CLKOUT/DREADY 13 XTAL1 14 XTAL2 15 MISO 16 17 MOSI SCLK Description Isolated Secondary Side Power Supply. This pin provides access to the 3.3 V on-chip isolated power supply. Do not connect external load circuitry to this pin. Decouple this pin with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor using Pin 2, GNDISO. Ground Reference of the Isolated Secondary Side. These pins provide the ground reference for the analog circuitry. Use these quiet ground references for all analog circuitry. These two pins are connected together internally. Analog Inputs for the Voltage Channels. The voltage channels are used with the voltage transducers. V2P and V1P are pseudo differential voltage inputs with a maximum signal level of ±500 mV with respect to VM for specified operation. Use these pins with the related input circuitry, as shown in Figure 20. If V1P or V2P is not used, connect it to the VM pin. On the ADE7912, connect the V2P pin to the VM pin because the V2P voltage channel is not available. The second voltage channel is available on the ADE7913 only. Analog Inputs for the Current Channel. The current channel is used with shunts. IM and IP are pseudo differential voltage inputs with a maximum differential level of ±31.25 mV. Use these pins with the related input circuitry, as shown in Figure 20. 2.5 V Output of Analog Low Dropout (LDO) Regulator. Decouple this pin with a 4.7 µF capacitor in parallel with a ceramic 100 nF capacitor to GNDISO, Pin 10. Do not connect external load circuitry to this pin. Voltage Reference. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V. Decouple this pin to GNDISO, Pin 10, with a 4.7 µF capacitor in parallel with a ceramic 100 nF capacitor. Primary Ground Reference. Clock Output (CLKOUT). When CLKOUT functionality is selected (see the Synchronizing Multiple ADE7912/ADE7913 Devices section for details), the ADE7912/ADE7913 generate a digital signal synchronous to the master clock at the XTAL1 pin. Use CLKOUT to provide a clock to other ADE7912/ADE7913 devices on the board. Data Ready, Active Low (DREADY). When DREADY functionality is selected (see the Synchronizing Multiple ADE7912/ADE7913 Devices section for details), the ADE7912/ADE7913 generate an active low signal synchronous to the ADC output frequency. Use this signal to start reading the ADC outputs of the ADE7912/ADE7913. Master Clock Input. An external clock can be provided at this logic input. The CLKOUT/DREADY signal of another appropriately configured ADE7912/ADE7913 (see the Synchronizing Multiple ADE7912/ADE7913 Devices section for details) can be provided at this pin. Alternatively, a crystal with a maximum drive level of 0.5 mW and an equivalent series resistance (ESR) of 20 Ω can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7912/ADE7913. The clock frequency for specified operation is 4.096 MHz, but lower frequencies down to 3.6 MHz can be used. See the ADE7912/ADE7913 Clock section for more details. Crystal, Second Input. A crystal with a maximum drive level of 0.5 mW and an ESR of 20 Ω can be connected across XTAL2 and XTAL1 to provide a clock source for the ADE7912/ADE7913. Data Output for SPI Port. Pull up this pin with a 10 kΩ resistor (see the ADE7912/ADE7913 Clock section for details). Data Input for SPI Port. Serial Clock Input for SPI Port. All serial data transfers are synchronized to this clock (see the Rev. 0 | Page 11 of 44 ADE7912/ADE7913 Pin No. Mnemonic 18 19 CS VDD Data Sheet Description ADE7912/ADE7913 Clock section). Chip Select for SPI Port. Primary Supply Voltage. This pin provides the supply voltage for the ADE7912/ADE7913. Maintain the supply voltage at 3.3 V ± 10% for specified operation. Decouple this pin to GND, Pin 20, with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. Rev. 0 | Page 12 of 44 Data Sheet ADE7912/ADE7913 TYPICAL PERFORMANCE CHARACTERISTICS 20 0 –20 SNR = 15.00dB THD = –28.08dB SINAD = 14.8dB SFDR = 33.75dB –20 –40 –40 AMPLITUDE (dB) –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 0 500 1000 1500 2000 2500 3000 3500 4000 4500 FREQUENCY (Hz) Figure 8. Current Channel FFT, ±31.25 mV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 0 –160 11115-108 –160 0 1000 1500 2000 2500 3000 3500 4000 4500 FREQUENCY (Hz) Figure 11. Voltage Channel V1 FFT, ±500 µV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 20 SNR = 6.98dB THD = –20.04dB SINAD = 6.77dB SFDR = 26.65dB –20 500 11115-111 AMPLITUDE (dB) 0 SNR = 67.06dB THD = –78.71dB SINAD = 66.78dB SFDR = 83.38dB SNR = 74.18dB THD = –80.44dB SINAD = 73.26dB SFDR = 73.26dB 0 –20 –40 AMPLITUDE (dB) AMPLITUDE (dB) –40 –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 500 1000 1500 2000 2500 3000 3500 4000 4500 FREQUENCY (Hz) Figure 9. Current Channel FFT, ±31.25 µV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 0 500 1000 1500 2000 2500 3000 –20 4000 4500 Figure 12. Voltage Channel V2 FFT, ±500 mV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz SNR = 74.4dB THD = –80.05dB SINAD = 73.36dB SFDR = 80.75dB 0 3500 FREQUENCY (Hz) 0 20 SNR = 14.68dB THD = –27.97dB SINAD = 14.48dB SFDR = 34.92dB –20 –40 –40 AMPLITUDE (dB) –60 –80 –100 –60 –80 –100 –120 –120 –140 –140 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) 3500 4000 4500 –160 11115-110 –160 Figure 10. Voltage Channel V1 FFT, ±500 mV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz 0 500 1000 1500 2000 2500 3000 FREQUENCY (Hz) 3500 4000 4500 11115-113 AMPLITUDE (dB) –180 11115-109 0 11115-112 –160 –160 Figure 13. Voltage Channel V2 FFT, ±500 µV, 50 Hz Pseudo Differential Input Signal, ADC_FREQ = 8 kHz, BW = 3300 Hz Rev. 0 | Page 13 of 44 Data Sheet 100 100 90 90 80 80 NUMBER OF OCCURRENCES 70 60 50 40 30 20 –6 2 10 18 26 34 42 50 40 30 20 TEMPERATURE COEFFICIENT (ppm/°C) 0 11115-114 –46 –38 –30 –22 –14 Figure 14. Cumulative Histogram of the Current Channel ADC Gain Temperature Coefficient for Temperatures Between −40°C and +25°C –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 100 90 90 80 80 60 50 40 30 20 4 6 8 10 Figure 17. Cumulative Histogram of the Voltage Channel V1 ADC Gain Temperature Coefficient for Temperatures Between +25°C and +85°C 100 70 2 TEMPERATURE COEFFICIENT (ppm/°C) NUMBER OF OCCURRENCES 10 70 60 50 40 30 20 10 –56 –48 –40 –32 –24 –16 –8 0 8 16 24 32 40 TEMPERATURE COEFFICIENT (ppm/°C) 0 11115-115 0 Figure 15. Cumulative Histogram of the Current Channel ADC Gain Temperature Coefficient for Temperatures Between +25°C and +85°C –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 90 80 80 NUMBER OF OCCURRENCES 100 90 60 50 40 30 20 4 6 Figure 18. Cumulative Histogram of the Voltage Channel V2 ADC Gain Temperature Coefficient for Temperatures Between −40°C and +25°C 100 70 2 TEMPERATURE COEFFICIENT (ppm/°C) 11115-118 NUMBER OF OCCURRENCES 50 10 0 NUMBER OF OCCURRENCES 60 11115-117 10 70 10 70 60 50 40 30 20 10 –26 –22 –18 –14 –10 –6 –2 TEMPERATURE COEFFICIENT (ppm/°C) 2 0 11115-116 0 Figure 16. Cumulative Histogram of the Voltage Channel V1 ADC Gain Temperature Coefficient for Temperatures Between −40°C and +25°C –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 TEMPERATURE COEFFICIENT (ppm/°C) 2 4 11115-119 NUMBER OF OCCURRENCES ADE7912/ADE7913 Figure 19. Cumulative Histogram of the Voltage Channel V2 ADC Gain Temperature Coefficient for Temperatures Between +25°C and +85°C Rev. 0 | Page 14 of 44 Data Sheet ADE7912/ADE7913 TEST CIRCUIT 1 10µF 150Ω FERRITE 100nF 1kΩ TP3 150Ω FERRITE 7 330kΩ 1kΩ 1kΩ 150Ω FERRITE TP5 IP VDD GND 6 IM CLKOUT/DREADY 1kΩ 4 CS V1P TS4148 33nF TS4148 5 33nF ADE7912C/ ADE7913C MISO MOSI VM SCLK 19 3.3V 20 100nF 10µF 12 TO MCU 18 TO MCU 15 16 17 TS4148 330kΩ 330kΩ TS4148 3 330kΩ XTAL1 V2P 8 1kΩ 33nF 4.7µF 4.7µF 100nF 100nF XTAL2 LDO 10 9 GNDISO GND 13 14 11 REF 3.3V 1 2 3 4 SAME AS IN ADE7912 C/ ADE7913 C 5 6 7 8 9 10 1 2 3 4 SAME AS IN ADE7912 C/ ADE7913 C 5 6 7 8 9 10 VDDISO CLKOUT/DREADY GNDISO CS V2P MISO V1P MOSI VM ADE7912B/ ADE7913B SCLK IM VDD IP XTAL1 LDO XTAL2 REF GND GNDISO GND VDDISO CLKOUT/DREADY CS GNDISO V2P V1P VM MISO MOSI ADE7912A/ ADE7913A SCLK IM VDD IP XTAL1 LDO XTAL2 REF GND GNDISO GND 12 18 Rev. 0 | Page 15 of 44 10kΩ TO MCU 16 TO MCU 17 TO MCU 19 SAME AS IN ADE7912 C/ ADE7913 C 13 14 11 20 12 18 TO MCU 15 16 17 SAME AS IN ADE7912 C/ ADE7913 C 19 13 14 11 20 NOTES 1. ADE7912 X/ADE7913 X = PHASE X ADE7912/ADE7913, WHERE X = A, B, OR C. Figure 20. Test Circuit TO MCU 15 4.096MHz 22pF 22pF 11115-008 TP4 33nF TP2 330kΩ GNDISO TS4148 150Ω FERRITE 330kΩ VDDISO 33nF TP1 150Ω FERRITE 2 ADE7912/ADE7913 Data Sheet TERMINOLOGY Pseudo Differential Signal Voltage Range Between IP and IM, V1P and VM, and V2P and VM Pins The range represents the peak-to-peak pseudo differential voltage that must be applied to the ADCs to generate a full-scale response when the IM and VM pins are connected to GNDISO, Pin 2. The IM and VM pins are connected to GNDISO using antialiasing filters (see Figure 20). Figure 21 illustrates the input voltage range between IP and IM; Figure 22 illustrates the input voltage range between V1P and VM and between V2P and VM. +31.25mV IP 0V –31.25mV IM 0V IP – IM Input Impedance to Ground (DC) The input impedance to ground represents the impedance measured at each ADC input pin (IP, IM, V1P, V2P, and VM) with respect to GNDISO, Pin 10. +31.25mV –31.25mV 11115-009 0V Figure 21. Pseudo Differential Input Voltage Range Between IP and IM Pins 0V ADC Offset Drift over Temperature The ADC offset drift is the change in offset over temperature. It is measured at −40°C, +25°C, and +85°C. The offset drift over temperature is computed as follows: –500mV 0V V1P – VM, V2P – VM Differential Input Impedance (DC) The differential input impedance represents the impedance measured between the ADC inputs: IP and IM, V1P and VM, and V2P and VM (ADE7913 only). ADC Offset Error ADC offset error is the difference between the average measured ADC output code with both inputs connected to GNDISO and the ideal ADC output code. The magnitude of the offset depends on the input range of each channel. +500mV V1P, V2P VM Crosstalk Crosstalk represents leakage of signals, usually via capacitance between circuits. Crosstalk is measured in the current channel by setting the IP and IM pins to GNDISO, Pin 10, supplying a full-scale alternate differential voltage between the V1P and VM pins and between the V2P and VM pins of the voltage channel, and measuring the output of the current channel. It is measured in the V1P voltage channel by setting the V1P and VM pins to GNDISO, Pin 10, supplying a full-scale alternate differential voltage at the IP and V2P pin, and measuring the output of the V1P channel. Crosstalk is measured in the V2P voltage channel by setting the V2P and VM pins to GNDISO, Pin 10, supplying a fullscale alternate differential voltage at the IP and V1P pins, and measuring the output of the V2P channel. The crosstalk is equal to the ratio between the grounded ADC output value and its ADC full-scale output value. The ADC outputs are acquired for 2 sec. Crosstalk is expressed in decibels. +500mV Drift = Offset (− 40 ) − Offset (25) Offset (85) − Offset (25) max , Offset (25) × (85 − 25) Offset (25) × (− 40 − 25) 0V Offset drift is expressed in nV/°C. 11115-010 –500mV Figure 22. Pseudo Differential Input Voltage Range Between V1P and VM Pins and Between V2P and VM Maximum VM and IM Voltage Range The range represents the maximum allowed voltage at VM and IM pins relative to GNDISO, Pin 10. Gain Error The gain error in the ADCs represents the difference between the measured ADC output code (minus the offset) and the ideal output code when the internal voltage reference is used (see the Analog-to-Digital Conversion section). The difference is expressed as a percentage of the ideal code. It represents the overall gain error of one current or voltage channel. Rev. 0 | Page 16 of 44 Data Sheet ADE7912/ADE7913 Gain Drift over Temperature This temperature coefficient includes the temperature variation of the ADC gain and of the internal voltage reference. It represents the overall temperature coefficient of one current or voltage channel. With the internal voltage reference in use, the ADC gain is measured at −40°C, +25°C, and +85°C. Then the temperature coefficient is computed as follows: Gain( − 40 ) − Gain(25) Gain(85) − Gain(25) Drift = max , Gain(25) × ( − 40 − 25) Gain(25) × (85 − 25) Gain drift is measured in ppm/°C. Power Supply Rejection (PSR) PSR quantifies the measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken when the voltage at the input pins is 0 V. A second reading is obtained with the same input signal levels when an ac signal (120 mV rms at 50 Hz or 100 Hz) is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of the reading (power supply rejection ratio, PSRR). PSR = 20 log10 (PSRR). For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken when the voltage between the IP and IM pins is 6.25 mV rms, and the voltages between the V1P and VM pins and between the V2P and VM pins are 100 mV rms. A second reading is obtained with the same input signal levels when the power supplies are varied by ±10%. Any error introduced is expressed as a percentage of the reading (PSRR). Then PSR = 20 log10 (PSRR). Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The spectral components are calculated over a 2 sec window. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The spectral components are calculated over a 2 sec window. The value for SINAD is expressed in decibels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of all harmonics (excluding the noise components) to the rms value of the fundamental. The spectral components are calculated over a 2 sec window. The value for THD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the rms value of the actual input signal to the rms value of the peak spurious component over the measurement bandwidth of the waveform samples. The spectral components are calculated over a 2 sec window. The value of SFDR is expressed in decibels relative to full scale, dBFS. Rev. 0 | Page 17 of 44 ADE7912/ADE7913 Data Sheet THEORY OF OPERATION The ADE7913 has three analog inputs: one current channel and two voltage channels. The ADE7912 does not include the second voltage channel. The current channel has two fully differential voltage input pins, IP and IM, that accept a maximum differential signal of ±31.25 mV. The maximum VIP signal level is also ±31.25 mV. The maximum VIM signal level allowed at the IM input is ±25 mV. Figure 23 shows a schematic of the input for the current channel and its relation to the maximum IM pin voltage. VIP +31.25mV VIP = ±31.25mV MAX PEAK VIM = ±25mV MAX VIP IP –31.25mV VIM IM 11115-033 0V Figure 23. Maximum Input Level, Current Channel Note that the current channel is used to sense the voltage across a shunt. In this case, one pole of the shunt becomes the ground of the meter (see Figure 33) and, therefore, the current channel is used in a pseudo differential configuration, similar to the voltage channel configuration (see Figure 24). The voltage channel has two pseudo differential, single-ended voltage input pins: V1P and V2P. These single-ended voltage inputs have a maximum input voltage of ±500 mV with respect to VM. The maximum signal allowed at the VM input is ±25 mV. Figure 24 shows a schematic of the voltage channel inputs and their relation to the maximum VM voltage. V1 +500mV V1 = ±500mV MAX PEAK VM = ±25mV MAX V1 V1P OR V2P –500mV VM VM 11115-034 0V Figure 24. Maximum Input Level, Voltage Channels ANALOG-TO-DIGITAL CONVERSION The ADE7912/ADE7913 have three second-order Σ-Δ ADCs. For simplicity, the block diagram in Figure 25 shows a first-order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator and the digital low-pass filter, separated by the digital isolation block. CLKIN/16 ANALOG LOW-PASS FILTER R C INTEGRATOR + + – ISOLATION BARRIER DIGITAL LOW-PASS FILTER LATCHED COMPARATOR – DIGITAL ISOLATION 24 VREF .....10100101..... 1-BIT DAC 11115-035 ANALOG INPUTS Figure 25. First-Order Σ-Δ ADC A Σ-Δ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7912/ADE7913, the sampling clock is equal to CLKIN/4 (1.024 MHz when CLKIN = 4.096 MHz). The 1-bit DAC in the feedback loop is driven by the serial stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and, therefore, the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. A meaningful result is obtained only when a large number of samples is averaged. This averaging is completed in the second part of the ADC, the digital low-pass filter, after the data is passed through the digital isolators. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit datawords that are proportional to the input signal level. The Σ-Δ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first technique is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, when CLKIN = 4.096 MHz, the sampling rate in the ADE7912/ADE7913 is 1.024 MHz, and the bandwidth of interest is 40 Hz to 3.3 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the bandwidth of interest is lowered, as shown in Figure 26. However, oversampling alone is not sufficient to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling factor of 4 is required to increase the SNR by a mere 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. Noise shaping is the second technique used to achieve high resolution. In the Σ-Δ modulator, the noise is shaped by the integrator, which has a high-pass type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital lowpass filter. This noise shaping is shown in Figure 26. Rev. 0 | Page 18 of 44 Data Sheet ADE7912/ADE7913 Antialiasing Filter SIGNAL SHAPED NOISE SAMPLING FREQUENCY NOISE 0 3.3 4 512 FREQUENCY (kHz) 1024 HIGH RESOLUTION OUTPUT FROM DIGITAL LPF SIGNAL 0 3.3 4 512 FREQUENCY (kHz) 1024 11115-036 NOISE Figure 26. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator The bandwidth of interest is a function of the input clock frequency, the ADC output frequency (selectable by Bits[5:4] (ADC_FREQ) in the CONFIG register; see the ADC Output Values section for details), and Bit 7 (BW) of the CONFIG register. When CLKIN is 4.096 MHz and the ADC output frequency is 8 kHz, if BW is cleared to 0 (the default value) the ADC bandwidth is 3.3 kHz. If BW is set to 1, the ADC bandwidth is 2 kHz. Table 10 shows the ADC output frequencies and the ADC bandwidth function of the input clock (CLKIN) frequency. Three cases are shown: one for CLKIN = 4.096 MHz, the typical clock input frequency value, one for CLKIN = 4.21 MHz, the maximum clock input frequency, and one for CLKIN = 3.6 MHz, the minimum clock input frequency. Figure 25 also shows an analog low-pass filter (RC) on the input to the ADC. This filter is placed outside the ADE7912/ADE7913, and its role is to prevent aliasing. Aliasing is an artifact of all sampled systems, as shown in Figure 27. Aliasing refers to the frequency components in the input signal to the ADC that are higher than half the sampling rate of the ADC and appear in the sampled signal at a frequency below half the sampling rate. Frequency components above half the sampling frequency (also known as the Nyquist frequency, that is, 512 kHz) are imaged or folded back down below 512 kHz. This happens with all ADCs, regardless of the architecture. In Figure 27, only frequencies near the sampling frequency of 1.024 MHz move into the bandwidth of interest for metering, that is, 40 Hz to 3.3 kHz or 40 Hz to 2 kHz. To attenuate the high frequency noise (near 1.024 MHz) and prevent the distortion of the bandwidth of interest, a lowpass filer (LPF) must be introduced. It is recommended that one RC filter with a corner frequency of 5 kHz be used for the attenuation to be sufficiently high at the sampling frequency of 1.024 MHz. The 20 dB per decade attenuation of this filter is usually sufficient to eliminate the effects of aliasing. ALIASING EFFECTS 0 2 4 512 FREQUENCY (kHz) IMAGE FREQUENCIES SAMPLING FREQUENCY 1024 11115-037 ANTIALIAS FILTER (RC) DIGITAL FILTER Figure 27. Aliasing Effects Table 10. ADC Output Frequency and ADC Bandwidth as a Function of CLKIN Frequency CLKIN (MHz) 4.096 4.21 3.6 Bits ADC_FREQ in CONFIG Register 00 01 10 11 00 01 10 11 00 01 10 11 ADC Output Frequency (Hz) 8000 4000 2000 1000 8222 4111 2055 1027 7031 3515 1757 878 ADC Bandwidth When Bit BW in CONFIG Register Cleared to 0 (Hz) 3300 1650 825 412 3391 1695 847 423 2900 1450 725 362 Rev. 0 | Page 19 of 44 ADC Bandwidth When Bit BW in CONFIG Register Set to 1 (Hz) 2000 1000 500 250 2055 1027 513 256 1757 878 439 219 ADE7912/ADE7913 Data Sheet V2WV REGISTER All ADCs in the ADE7912/ADE7913 produce 24-bit signed output codes. With a full-scale input signal of 31.25 mV on the current channel and 0.5 V on the voltage channels, and with an internal reference of 1.2 V, the ADC output code is nominally 5,320,000 and usually varies for each ADE7912/ADE7913 around this value. The code from the ADC can vary between 0x800000 (−8,388,608) and 0x7FFFFF (+8,388,607); this is equivalent to an input signal level of ±49.27 mV on the current channel and ±0.788 V on the voltage channels. However, for specified performance, do not exceed the nominal range of ±31.25 mV for the current channel and ±500 mV for the voltage channels; ADC performance is guaranteed only for input signals within these limits. 23 16 15 ADC Output Values The ADC output values are stored in three 24-bit signed registers, IWV, V1WV, and V2WV, at a rate defined by Bits[5:4] (ADC_FREQ) in the CONFIG register. The output frequency is 8 kHz (CLKIN/512), 4 kHz (CLKIN/1024), 2 kHz (CLKIN/2048), or 1 kHz (CLKIN/4096) based on ADC_FREQ being equal to 00, 01, 10, or 11, respectively, when CLKIN is 4.096 MHz. The microcontroller reads the ADC output registers one at a time or in burst mode. See the SPI Read Operation and the SPI Read Operation in Burst Mode sections for more information. REFERENCE CIRCUIT The nominal reference voltage at the REF pin is 1.2 V. This reference voltage is used for the ADCs in the ADE7912/ ADE7913. Because the on-chip dc-to-dc converter cannot supply external loads, the REF pin cannot be overdriven by a standalone external voltage reference. The voltage of the ADE7912/ADE7913 reference drifts slightly with temperature. Table 1 lists the gain drift over temperature specification of each ADC channel. This value includes the temperature variation of the ADC gain, together with the temperature variation of the internal voltage reference. CRC OF ADC OUTPUT VALUES Every output cycle, the ADE7912/ADE7913 compute the cyclic redundancy check (CRC) of the ADC output values stored in the IWV, V1WV, and V2WV registers. Bits[5:4] (ADC_FREQ) in the CONFIG register determine the ADC output frequency and, therefore, the update rate of the CRC. The CRC algorithm is based on the CRC-16-CCITT algorithm. The registers are introduced into a linear feedback shift register (LFSR) based generator one byte at a time, least significant byte first, as shown in Figure 28. Each byte is then used with the most significant bit first. The 16-bit result is written in the ADC_CRC register. 16 23 8 8 7 15 0 0 IWV REGISTER V1WV REGISTER 23 16 15 7 16 23 8 8 7 15 0 0 23 16 15 7 16 23 8 8 7 0 15 0 7 + a71 a48 a47 a24 a23 a0 LFSR GENERATOR 11115-038 ADC Transfer Function Figure 28. CRC Calculation of ADC Output Values g0 g1 g2 g3 g15 FB b0 b1 b2 b15 11115-039 LFSR a71, a70,....,a2, a1, a0 Figure 29. LFSR Generator Used for ADC_CRC Calculation Figure 29 shows how the LFSR works. The IWV, V1WV, and V2WV registers form the [a71, a70,…, a0] bits used by the LFSR. Bit a0 is Bit 7 of the first register to enter the LFSR; Bit a71 is Bit 16 of V2WV, the last register to enter the LFSR. The formulas that govern the LFSR are as follows: bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that form the CRC. Bit b0 is the least significant bit, and Bit b15 is the most significant bit. gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating polynomial defined by the CRC-16-CCITT algorithm as follows: G(x) = x16 + x12 + x5 + 1 (1) g0 = g5 = g12 = 1 (2) All other gi coefficients are equal to 0. FB(j) = aj − 1 XOR b15(j − 1) (3) b0(j) = FB(j) AND g0 (4) bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, …, 15 (5) Equation 3, Equation 4, and Equation 5 must be repeated for j = 1, 2, …, 72. The value written into the ADC_CRC register contains Bit bi(72), i = 0, 1, …, 15. The ADC_CRC register can be read by executing an SPI register read access or as part of the SPI burst mode read operation. See the SPI Read Operation and the SPI Read Operation in Burst Mode sections for more details. TEMPERATURE SENSOR The ADE7912/ADE7913 contain a temperature sensor that is multiplexed with the V2P input of the voltage channel. Bit 3 (TEMP_EN) of the CONFIG register selects what the third ADC of the ADE7913 measures. If the TEMP_EN bit is 0, its default value, the ADC measures the voltage between the V2P and VM pins. If the TEMP_EN bit is 1, the ADC measures the temperature sensor. In the case of the ADE7912, the ADC always measures the temperature sensor, and the state of the TEMP_EN bit has no significance. In both the ADE7912 and the ADE7913, the conversion result is stored in the V2WV register. The time it Rev. 0 | Page 20 of 44 Data Sheet ADE7912/ADE7913 takes for the temperature sensor measurement to settle after the TEMP_EN bit is set to 1 is 5 ms. The expression used to calculate the temperature in the microcontroller is: temp = 8.72101 × 10−5 × (V2WV + TEMPOS × 211) − 306.47 where: temp is the temperature value measured in degrees Celsius. The gain used to convert the bit information provided by the ADE7912/ADE7913 into degrees Celsius has a default value of 8.72101 × 10−5°C/LSB. The temperature measurement accuracy is ±5°C. TEMPOS is the 8-bit signed read-only register in which the temperature sensor offset is stored. The offset information is calculated during the manufacturing process, and it is stored with the opposite sign. For example, if the offset is 5, −5 is written into the ADE7912/ADE7913. One least significant bit (LSB) of the TEMPOS register is equivalent to 211 LSBs of the V2WV register. Instead of using the default gain value, the gain can be calibrated as part of the overall meter calibration process. Measure the temperature, TEMP, of every ADE7912/ADE7913, read the V2WV register containing the temperature sensor reading of every ADE7912/ADE7913, and compute the gains as follows: Temperature gain = TEMP V 2WV + TEMPOS × 211 (6) PROTECTING THE INTEGRITY OF CONFIGURATION REGISTERS The configuration registers of the ADE7912/ADE7913 are either user accessible registers (CONFIG, EMI_CTRL, SYNC_SNAP, COUNTER0, and COUNTER1) or internal registers. The internal registers are not user accessible, and they must remain at their default values. To protect the integrity of all configuration registers, a write protection mechanism is available. By default, the protection is disabled and the user accessible configuration registers can be written without restriction. When the protection is enabled, no writes to any configuration register are allowed. The registers can always be read, without restriction, independent of the write protection state. To enable the protection, write 0xCA to the 8-bit lock register (Address 0xA). To disable the protection, write 0x9C to the 8bit lock register. It is recommended that the write protection be enabled after the CONFIG and EMI_CTRL registers are initialized. If any user accessible register must be changed, for example, during the synchronization process of multiple ADE7912/ADE7913 devices, disable the protection, change the value of the register, and then reenable the protection. CRC OF CONFIGURATION REGISTERS Every output cycle, the ADE7912/ADE7913 compute the CRC of the CONFIG, EMI_CTRL, and TEMPOS registers, as well as Bit 2 (IC_PROT) of the STATUS0 register, and Bit 7 of the STATUS1 register. The CRC algorithm is called CRC-16CCITT. The 16-bit result is written in the CTRL_CRC register. The input registers to the CRC circuit form a 64-bit array that is introduced bit by bit into an LFSR-based generator, similar to Figure 28 and Figure 29, with one byte at a time, least significant byte first. Each byte is then processed with the most significant bit first. The formulas that govern the LFSR are as follows: bi(0) = 1, where i = 0, 1, 2, …, 15, the initial state of the bits that form the CRC. Bit b0 is the least significant bit, and Bit b15 is the most significant bit. gi, where i = 0, 1, 2, …, 15 are the coefficients of the generating polynomial defined by the CRC-16-CCITT algorithm in Equation 1 and Equation 2. FB(j) = aj − 1 XOR b15(j − 1) (7) b0(j) = FB(j) AND g0 (8) bi(j) = FB(j) AND gi XOR bi − 1(j − 1), i = 1, 2, 3, … , 15 (9) Equation 7, Equation 8, and Equation 9 must be repeated for j = 1, 2, … , 64. The value written into the CTRL_CRC register contains Bit bi(64), i = 0, 1, …, 15. Because each ADE7912/ ADE7913 has a particular TEMPOS register value, each ADE7912/ ADE7913 has a different CTRL_CRC register default value. ADE7912/ADE7913 STATUS The bits in the STATUS0 and STATUS1 registers of the ADE7912/ADE7913 characterize the state of the device. If the value of the CTRL_CRC register changes, Bit 1 (CRC_STAT) is set to 1 in the STATUS0 register. This bit clears to 0 when the STATUS0 register is read. After the configuration registers are protected by writing 0xCA into the lock register, Bit 2 (IC_PROT) in the STATUS0 register is set to 1. It clears to 0 when the STATUS0 register is read, and it is set back to 1 at the next ADC output cycle. At power-up, or after a hardware or software reset, the ADE7912/ADE7913 signal the end of the reset period by clearing Bit 0 (RESET_ON) to 0 in the STATUS0 register. If the ADC output values of IWV, V1WV, and V2WV are not read during an output cycle, Bit 3 (ADC_NA) in the STATUS1 register becomes 1. It clears to 0 when the STATUS1 register is read. The STATUS0 and STATUS1 registers can be read by executing an SPI register read. STATUS0 can also be read as part of the SPI burst mode read operation. See the SPI Read Operation and the SPI Read Operation in Burst Mode sections for more information. Rev. 0 | Page 21 of 44 ADE7912/ADE7913 Data Sheet The voltage shown in Figure 31 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. The insulation lifetime of the ADE7912/ADE7913 devices depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 30, Figure 31, and Figure 32 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the bipolar ac condition determines the maximum working voltage recommended by Analog Devices. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows Rev. 0 | Page 22 of 44 RATED PEAK VOLTAGE 0V 11115-040 The values shown in Table 8 summarize the maximum CSA/VDE approved working voltage for 50 years of service life for a bipolar ac operating condition. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The working voltages listed in Table 8 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage case. Treat any cross-insulation voltage waveform that does not conform to Figure 31 or Figure 32 as a bipolar ac waveform, and limit its peak voltage to the 50-year lifetime voltage value listed in Table 8. Figure 30. Bipolar AC Waveform RATED PEAK VOLTAGE 11115-041 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period of time. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADE7912/ ADE7913 devices. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. operation at higher working voltages while still achieving a year service life. 0V Figure 31. Unipolar AC Waveform RATED PEAK VOLTAGE 11115-042 INSULATION LIFETIME 0V Figure 32. DC Waveform Data Sheet ADE7912/ADE7913 APPLICATIONS INFORMATION V1P VM GNDISO IM 11115-011 IP IA Figure 33. Phase A ADE7912/ADE7913 Current and Voltage Sensing Figure 33 shows the Phase A of a 3-phase energy meter. The Phase A current, IA, is sensed with a shunt. A pole of the shunt is connected to the IM pin of the ADE7912/ADE7913 and becomes the ground, GNDISO (Pin 10), of the isolated side of the ADE7912/ADE7913. The Phase A to neutral voltage, VAN, is sensed with a resistor divider, and the VM pin is also connected to the IM and GNDISO pins. Note that the voltages measured by the ADCs of the ADE7912/ADE7913 are opposite to VAN and IA, a classic approach in single-phase metering. The other ADE7912/ADE7913 devices that monitor Phase B and Phase C are connected in a similar way. The microcontroller uses the SPI port to communicate with the ADE7912/ADE7913 devices. Three of its I/O pins, CS_A, CS_B, and CS_C, are used to generate the SPI CS signals. The SCLK, MOSI, and MISO pins of the microcontroller are directly connected to the corresponding SCLK, MOSI, and MISO pins of each ADE7912/ADE7913 device (see Figure 39). To simplify Figure 35 to Figure 38, these connections are not shown. IM CS SCLK IP MOSI 4.096MHz CRYSTAL MISO GNDMCU PHASE B ADE7912/ADE7913 CS_A XTAL2 CS_B VM XTAL1 CS_C IM CS SCLK SCLK IP MOSI GNDISO_B VM MICROCONTROLLER V1P V2P V1P MISO CLKOUT/ DREADY GNDMCU MOSI MISO I/O PHASE C ADE7912/ADE7913 IM GNDISO V1P XTAL2 IP VM XTAL1 IM CS SCLK IP MOSI 11115-012 EARTH XTAL1 GNDISO_A ADE7912/ ADE7913 IN XTAL2 VM CLKOUT/ DREADY NEUTRAL LINE VN V1P V2P The V2P voltage channel is intended to measure an auxiliary voltage, and it is available only on the ADE7913. If V2P is not used, as is the case of the ADE7912, connect V2P to VM. NEUTRAL PHASE A ADE7912/ADE7913 Figure 34. Neutral Line and Neutral to Earth Voltage Monitoring with the ADE7912/ADE7913 LOAD Figure 34 shows how the ADE7912/ADE7913 inputs are connected when the neutral line of a 3-phase system is monitored. The neutral current is sensed using a shunt and the voltage across the shunt is measured at the fully differential inputs, IP and IM. The earth to neutral voltage is sensed with a voltage divider at the single-ended inputs, V1P and VM. V2P GNDISO_C MISO CLKOUT/ DREADY GNDMCU ISOLATION BARRIER Figure 35. 3-Phase Energy Meter Using Three ADE7912/ADE7913 Devices Figure 35 shows a block diagram of a 3-phase energy meter that uses three ADE7912/ADE7913 devices and a microcontroller. The neutral current is not monitored in this example. One 4.096 MHz crystal provides the clock to the ADE7912/ADE7913 that Rev. 0 | Page 23 of 44 11115-013 VAN PHASE C PHASE A ADE7912/ ADE7913 PHASE B NEUTRAL PHASE A PHASE A The ADE7912/ADE7913 are designed for use in 3-phase energy metering systems in which two, three, or four ADE7912/ADE7913 devices are managed by a master device containing an SPI interface, usually a microcontroller. senses the Phase A current and voltage. The ADE7912/ADE7913 devices that sense the Phase B and Phase C currents and voltages are clocked by a signal generated at the CLKOUT/DREADY pin of the ADE7912/ADE7913 that is placed to sense the Phase A current and voltage. As an alternative configuration, the microcontroller can generate a 4.096 MHz clock to all ADE7912/ADE7913 devices at the XTAL1 pin (see Figure 36). Note that the XTAL1 pin can receive a clock with a frequency within the 3.6 MHz to 4.21 MHz range, as specified in Table 1. NEUTRAL ADE7912/ADE7913 IN POLYPHASE ENERGY METERS PHASE B PHASE C PHASE A PHASE A ADE7912/ADE7913 V1P XTAL2 V1P XTAL2 VM XTAL1 VM XTAL1 IM CS SCLK IM CS SCLK IP MOSI IP MOSI V2P MISO CLKOUT/ DREADY GNDISO_A GNDISO_A GNDMCU PHASE B ADE7912/ADE7913 MICROCONTROLLER XTAL2 CS_B VM XTAL1 CS_C IM CS SCLK CS_N IP MOSI MOSI MISO CLKOUT/ DREADY MISO VM XTAL1 CS_C IM CS SCLK SCLK MISO CLKOUT/ DREADY GNDISO_B MOSI MISO CLK I/O V2P GNDISO_B GNDMCU PHASE C ADE7912/ADE7913 V1P XTAL2 V1P XTAL2 VM XTAL1 VM XTAL1 IM CS SCLK IM CS SCLK IP MOSI IP MOSI MISO CLKOUT/ DREADY GNDISO_C V2P GNDMCU ISOLATION BARRIER GNDISO_C At power-up, or after a hardware or software reset, follow the procedure described in the Power-Up Procedure for Systems with Multiple Devices That Use a Single Crystal section or the Power-Up Procedure for Systems with Multiple Devices That Use Clock Generated from Microcontroller section to ensure that the ADE7912/ADE7913 devices function appropriately. SCLK I/O MISO CLKOUT/ DREADY GNDMCU PHASE N ADE7912/ADE7913 Figure 36. Microcontroller Generating Clock to Three ADE7912/ADE7913 Devices In Figure 36, the CLKOUT/DREADY pin of the ADE7912/ADE7913 that is used to sense the Phase C current and voltage is connected to the I/O pin of the microcontroller. CLKOUT/DREADY provides an active low pulse for 64 CLKIN cycles (15.625 µs at CLKIN = 4.096 MHz) when the ADC conversion data is available. It signals when the ADC outputs of all ADE7912/ADE7913 devices become available and when the microcontroller starts to read them. See the Synchronizing Multiple ADE7913 Devices section for more information about synchronizing multiple ADE7912/ADE7913 devices. CS_A GNDMCU PHASE C ADE7912/ADE7913 V2P MICROCONTROLLER V1P CS_B V2P GNDMCU CS_A XTAL2 MOSI MISO CLKOUT/ DREADY PHASE B ADE7912/ADE7913 V1P IP 4.096MHz CRYSTAL V1P XTAL2 VM XTAL1 IM CS SCLK IP MOSI V2P LOAD GNDISO_N EARTH MISO CLKOUT/ DREADY GNDMCU ISOLATION BARRIER 11115-015 PHASE A ADE7912/ADE7913 V2P LOAD NEUTRAL Data Sheet 11115-014 PHASE C PHASE A PHASE B NEUTRAL ADE7912/ADE7913 Figure 37. 3-Phase Energy Meter Using Four ADE7912/ADE7913 Devices Figure 38 shows an energy meter using two ADE7912/ADE7913 devices in a delta configuration. The meter ground is on the Phase B line. One ADE7912/ADE7913 device measures Phase A current and Phase A to Phase B voltage. A second ADE7912/ ADE7913 device measures Phase C current and Phase C to Phase B voltage. Phase B current and Phase A to Phase C voltage are computed by the system microcontroller. The configuration of an energy meter using four ADE7912/ ADE7913 devices is similar, shown in Figure 37. The microcontroller uses an additional I/O pin, CS_N, to generate the SPI CS signal to the ADE7912/ADE7913 device that is monitoring the neutral current. Rev. 0 | Page 24 of 44 ADE7912/ADE7913 PHASE C PHASE B PHASE A Data Sheet ADE7912/ADE7913 CLOCK PHASE A ADE7912/ADE7913 V1P XTAL2 XTAL1 VM Provide a digital clock signal at the XTAL1 pin to clock the ADE7912/ADE7913. The frequency at which the ADE7912/ ADE7913 are clocked at XTAL1 is called CLKIN. The ADE7912/ ADE7913 are specified for CLKIN = 4.096 MHz, but frequencies between 3.6 MHz and 4.21 MHz are acceptable. 4.096MHz CRYSTAL CS SCLK IM MOSI IP V2P GNDISO_A MISO CLKOUT/ DREADY GNDMCU MICROCONTROLLER PHASE C ADE7912/ADE7913 V1P XTAL2 VM XTAL1 IM CS SCLK IP MOSI V2P GNDISO_C The total capacitance, TC, at the XTAL1 and XTAL2 pins is TC = C1 + CP1 = C2 + CP2 MISO CLKOUT/ DREADY GNDMCU 11115-016 LOAD CS_A CS_C SCLK MOSI MISO I/O ISOLATION BARRIER Alternatively, a 4.096 MHz crystal with a typical drive level of 0.5 mW and an equivalent series resistance (ESR) of 20 Ω can be connected across the XTAL1 and XTAL2 pins to provide a clock source for the ADE7912/ADE7913 (see Figure 40). Figure 38. 3-Phase Meter Using Two ADE7912/ADE7913 Devices in Delta Configuration where: C1 and C2 are the ceramic capacitors between XTAL1 and GND and between XTAL2 and GND, respectively. CP1 and CP2 are the parasitic capacitors of the wires connecting the crystal to the ADE7912/ADE7913. The load capacitance, LC, of the crystal is equal to half the total capacitance, TC, because it is the capacitance of the series circuit composed by C1 + CP1 and C2 + CP2. LC = CS ADE7912/ ADE7913 SCLK Therefore, the value of the C1 and C2 capacitors as a function of the load capacitance of the crystal is MOSI PHASE A MISO VDD C1 = C2 = 2 × LC − CP1 = 2 × LC − CP2 10kΩ In the case of the ADE7912/ADE7913, the typical total capacitance, TC, of the XTAL1 and XTAL2 pins is 40 pF (see Table 1). Select a crystal with a load capacitance of CS_A CS CS_B SCLK SCLK MOSI MOSI PHASE B MISO MISO CS_C ADE7912/ ADE7913 C1 + CP1 C2 + CP2 TC = = 2 2 2 LC = TC = 20 pF 2 Assuming the parasitic capacitances, CP1 and CP2, are equal to 20 pF, select Capacitors C1 and C2 equal to 20 pF. MICROCONTROLLER CP1 CS SCLK MOSI XTAL1 11115-017 PHASE C MISO TC C1 C2 XTAL2 Figure 39. SPI Connections Between Three ADE7912/ADE7913 Devices and a Microcontroller TC CP2 Figure 40. Crystal Circuitry Rev. 0 | Page 25 of 44 11115-018 ADE7912/ ADE7913 ADE7912/ ADE7913 ADE7912/ADE7913 Data Sheet SPI-COMPATIBLE INTERFACE stays in high impedance when no data is transmitted from the ADE7912/ADE7913. At power-up or during hardware or software reset, the microcontroller reads the STATUS0 register to detect when Bit 0 (RESET_ON) clears to 0. See Figure 39 for details of the connections between the SPI ports of three ADE7912/ADE7913 devices and a microcontroller containing an SPI interface. The SPI of the ADE7912/ADE7913 is the slave of the communication and consists of four pins: SCLK, MOSI, MISO, and CS. The serial clock for a data transfer is applied at the SCLK logic input. All data transfer operations synchronize to the serial clock. Data shifts into the ADE7912/ADE7913 at the MOSI logic input on the falling edge of SCLK, and the ADE7912/ADE7913 sample the data on the rising edge of SCLK. Data shifts out of the ADE7912/ADE7913 at the MISO logic output on the falling edge of SCLK and can be sampled by the master device on the rising edge of SCLK. The most significant bit of the word is shifted in and out first. The maximum and minimum serial clock frequencies supported by this interface are 5.6 MHz and 250 kHz, respectively. MISO The CS logic input is the chip select input. Drive the CS input low for the entire data transfer operation. Bringing CS high during a data transfer operation leaves the ADE7912/ADE7913 register that is the object of the data transfer unaffected, but aborts the transfer and places the serial bus in a high impedance state. A new transfer can then be initiated by returning the CS logic input to low. CS SCLK ADDR[4:0] 1 0 0 7 1 6 MISO 0 11115-019 MOSI REGISTER VALUE Figure 41. SPI Read Operation of an 8-Bit Register CS SCLK 0 0 0 0 0 1 0 0 MOSI 0 IWV MISO 15 0 CNT_SNAPSHOT 11115-020 23 Figure 42. SPI Read Operation in Burst Mode CS SCLK MOSI ADDR[4:0] 0 0 0 6 1 REGISTER VALUE Figure 43. SPI Write Operation Rev. 0 | Page 26 of 44 0 11115-021 7 Data Sheet ADE7912/ADE7913 SPI Read Operation The read operation using the ADE7912/ADE7913 SPI interface is initiated when the master sets the CS pin low and begins sending one command byte on the MOSI line. The master places data on the MOSI line starting with the first high to low transition of SCLK. The bit composition of the command byte is shown in Table 11. Bits[1:0] are don’t care bits, and they can have any value. The examples presented throughout this section show them set to 00. Bit 2 (READ_EN) determines the type of the operation. For a read, READ_EN must be set to 1. For a write, READ_EN must be cleared to 0. Bits[7:3] (ADDR) represent the address of the register to be read or written. The ADE7912/ADE7913 SPI samples data on the low to high transitions of SCLK. After the ADE7912/ADE7913 device receives the last bit of the command byte on a low to high transition of SCLK, it begins to transmit its contents on the MISO line when the next SCLK high to low transition occurs; thus, the master can sample the data on a low to high SCLK transition. After the master receives the last bit, it sets the CS and SCLK lines high and the communication ends. The data lines, MOSI and MISO, go into a high impedance state. Figure 41 shows an 8-bit register read operation; 16-bit and 32-bit registers are read in the same manner. Table 11. Command Byte for SPI Read/Write Operations Bit Location 1:0 2 7:3 Bit Name Reserved READ_EN ADDR Description These bits can have any value. Set this bit to 1 if a SPI read operation is executed. Clear this bit to 0 if a SPI write operation is executed. Address of the register to be read or written. SPI Read Operation in Burst Mode All ADE7912/ADE7913 output registers (IWV, V1WV, V2WV, ADC_CRC, STATUS0, and CNT_SNAPSHOT) can be read in one of two ways: one register at a time (see the SPI Read Operation section) or by reading multiple consecutive registers simultaneously in burst mode. Burst mode is initiated when the master sets the CS pin low and begins sending the command byte (see Table 11) on the MOSI line with Bits[7:3] (ADDR) set to the IWV register address, 00000. This means a command byte set to 0x04. The master places data on the MOSI line starting with the first high to low transition of SCLK. The SPI of the ADE7912/ADE7913 samples data on the low to high transitions of SCLK. After the ADE7912/ADE7913 device receives the last bit of the command byte on a low to high transition of SCLK, it begins to transmit the 24-bit IWV register on the MISO line when the next SCLK high to low transition occurs; thus, the master can sample the data on a low to high SCLK transition. After the master receives the last bit of the IWV register, the ADE7912/ADE7913 device sends V1WV, which is placed at the next location, and continues in this manner until the master sets the CS and SCLK lines high and the communication ends. The data lines, MOSI and MISO, go into a high impedance state. See Figure 42 for details of the SPI read operation in burst mode. If a register does not need to be read, for example, the 16-bit CNT_SNAPSHOT register, the master sets the CS and SCLK lines high after the STATUS0 register is received. If the IWV register, for example, is not required, but V1WV is, set the ADDR bits to the V1WV address, 00001, in the command byte, and execute the burst mode operation. SPI Write Operation The SPI write operation is initiated when the master sets the CS pin low and begins sending one command byte (see Table 11). Bit 2 (READ_EN) must be cleared to 0. The master places data on the MOSI line starting with the first high to low transition of SCLK. The SPI of the ADE7912/ADE7913 samples data on the low to high transitions of SCLK. Next, the master sends the 8-bit value of the register without losing any SCLK cycles. After the last bit is transmitted, at the end of the SCLK cycle, the master sets the CS and SCLK lines high and the communication ends. The data lines, MOSI and MISO, go into a high impedance state. See Figure 43 for details of the SPI write operation. Note that the SPI write operation can execute 8-bit writes only. The 16-bit synchronization counter register (composed of COUNTER0 and COUNTER1) is written by executing the write operation twice: the less significant byte is written first, followed by the most significant byte. See the Synchronizing Multiple ADE7912/ADE7913 Devices section for details on the functionality controlled by the synchronization counter register. Because the ADE7912/ADE7913 do not need to acknowledge a write command in any way, this operation can be broadcast to multiple ADE7912/ADE7913 devices when the same register must be initialized with the same value. After executing a write operation, it is recommended to read back the register to ensure that it was initialized correctly. SYNCHRONIZING MULTIPLE ADE7912/ADE7913 DEVICES The ADE7912/ADE7913 allow the user to sample all currents and voltages simultaneously and to provide coherent ADC output samples, which is a highly desired feature in polyphase metering systems. The EMI reduction scheme managed by the EMI_CTRL register (see the DC-to-DC Converter section for details) requires that the ADE7912/ADE7913 provide coherent samples. The ADE7912/ADE7913 in Polyphase Energy Meters section describes how a polyphase energy meter containing multiple ADE7912/ADE7913 devices can use one crystal to clock all the ADE7912/ADE7913 devices. At power-up, only one ADE7912/ ADE7913 device is clocked from the crystal, as the other devices are set to receive the clock from the CLKOUT/DREADY pin of the first ADE7912/ADE7913 device. This pin has DREADY Rev. 0 | Page 27 of 44 ADE7912/ADE7913 Data Sheet functionality enabled by default. In Figure 35, Figure 37, and Figure 38, the ADE7912/ADE7913 device on Phase A is clocked from the crystal, and the CLKOUT/DREADY pin generates the DREADY signal. The other ADE7912/ADE7913 devices are clocked by the DREADY signal because the CLKOUT signal has not yet been received by their XTAL1 pins. The microcontroller enables CLKOUT functionality when Bit 0 (CLKOUT_EN) is set to 1 in the CONFIG register. This operation ensures that the other ADE7912/ ADE7913 devices in the system receive the same clock as the ADE7912/ADE7913 on Phase A and that all ADCs within all ADE7912/ADE7913 devices in the system sample data at the same exact moment. As shown in Figure 35, Figure 37, and Figure 38, the CLKOUT/ DREADY pin of one ADE7912/ADE7913 is connected to an I/O input of the microcontroller. This ADE7912/ADE7913 device has Bit 0 (CLKOUT_EN) in the CONFIG register set to the default value, 0, to enable the DREADY functionality. When the ADC output period starts, the CLKOUT/DREADY pin goes low for 64 CLKIN cycles (15.625 µs when CLKIN = 4.096 MHz), signaling that all ADC outputs from all ADE7912/ADE7913 devices are available and the microcontroller must start reading them. It is recommended that the SPI read in burst mode be used to ensure that all data is read in the shortest amount of time. As an alternative to using one crystal, the microcontroller can generate a clock signal to the XTAL1 pins of every ADE7912/ ADE7913, ensuring precise ADC sampling synchronization (see Figure 36). The ADE7912/ADE7913 contain an internal 12-bit counter that functions at the CLKIN frequency. The counter is synchronized with the ADC output period and the CLKOUT/DREADY pin. When a new output period starts, the counter starts decreasing from a value determined by Bits[5:4] (ADC_FREQ) in the CONFIG register. Table 12 shows these values. To configure all ADE7912/ADE7913 devices in an energy meter to provide coherent ADC output samples, that is, samples obtained in the same output cycle, all ADE7912/ADE7913 devices must have the same ADC output frequency and the outputs must be synchronized. Bits[5:4] (ADC_FREQ) in the CONFIG register select the ADC output frequency; therefore, they must be initialized to the same value (see the ADC Output Values section for more details). To synchronize the ADC outputs, that is, to set all ADE7912/ADE7913 devices to generate ADC outputs at the same exact moment, after power-up, the microcontroller must broadcast a write to the 8-bit SYNC_SNAP register with the value 0x01. All ADE7912/ADE7913 devices then start a new ADC output period simultaneously when Bit 0 (sync) of the SYNC_SNAP register is written. The sync bit clears itself to 0 after one CLKIN cycle. Table 12. Counter Initial Values as a Function of ADC_FREQ Bits Bits[5:4] (ADC_FREQ) in CONFIG Register 00 ADC Output Frequency (kHz) 8 Counter C0 Initial Value (CLKIN = 4.096 MHz) 511 01 4 1023 10 2 2047 11 1 4095 Rev. 0 | Page 28 of 44 Counter C0 Initial Value as a Function of CLKIN CLKIN −1 8000 CLKIN −1 4000 CLKIN −1 2000 CLKIN −1 1000 Data Sheet ADE7912/ADE7913 ADC CYCLE 0 ADC CYCLE 1 ADC CYCLE 2 ADC CYCLE 3 ADC CYCLE 4 DREADY C0 ADE7912 C ADE7913 C CC C0 ADE7912 B ADE7913 B CB C0 CA ADE7912 A/ADE7913 A COUNTER STARTS FROM A NEW VALUE SYNC_SNAP = 0x02 CA, CB, CC ARE READ * = C + C – C IS WRITTEN (C < C ) NEW CA 0 C A C A * = C – C IS WRITTEN (C > C ) NEW CB C B C B ALL ADE7912/ADE7913s ARE IN SYNC ADE7912 B/ADE7913 B COUNTER STARTS FROM A NEW VALUE 11115-022 ADE7912 A ADE7913 A 12 11 0000 8 7 COUNTER VALUE 0 Figure 45. CNT_SNAPSHOT Register The 8-bit SYNC_SNAP register latches the value of the counter when it is written with 0x02, that is, Bit 1 (snap) set to 1. A broadcast write to all ADE7912/ADE7913 devices ensures that all the counters of every ADE7912/ADE7913 are latched at the same moment. The snap bit clears itself to 0 after one CLKIN cycle. The values of the counters offer a measure of the ADC output synchronization across all ADE7912/ADE7913 devices. Ideally, the values should be perfectly equal, indicating that all ADE7912/ADE7913 devices are fully synchronized. In reality, due to the uncertainty between the SPI clock generated by the microcontroller and the ADE7912/ADE7913 CLKIN, a ±1 count difference between counters is acceptable. The 12-bit counter is accessed via the 16-bit CNT_SNAPSHOT register (see Figure 45). If the internal counter of one ADE7912/ADE7913 device does not have a value correlated with the values of the counters of the other ADE7912/ADE7913 devices, this means that the ADC outputs of one phase are no longer synchronized with the ADC outputs from the other phases. The ADE7912/ADE7913 provide two options to resynchronize all the ADE7912/ADE7913 devices: one is to broadcast a write to the 8-bit SYNC_SNAP register with the value 0x01. This action immediately forces all ADE7912/ADE7913 devices to start an ADC output cycle simultaneously. However, all phases present ADC output distortions of various degrees, a function of when a SYNC_SNAP = 0x01 write is executed within the current output period. Therefore, it is recommended that this command be executed at power-up or after a hardware or software reset. The other option is to compute a new starting value for the internal counter of the ADE7912/ADE7913 device that is out of synchronization. This value forces the internal counter to start a new ADC output cycle, counting down from it, and end simultaneously with the other counters of the other ADE7912/ ADE7913 devices. The 12-bit value is stored in two 8-bit registers, COUNTER1 and COUNTER0 (see Figure 46). COUNTER0 contains the least significant eight bits and must be written first. COUNTER1 contains the four most significant bits and must be written after COUNTER0. The advantage of this option compared to writing SYNC_SNAP = 0x01 is that only the ADC outputs of out of sync phases are affected. The other phases already in synchronization remain unaffected. As a general rule, it is recommended that the synchronization of the ADE7912/ ADE7913 devices be verified every couple of seconds. COUNTER[11:0] 11 4 3 7 0000 8 7 0 4-BIT UNSIGNED NUMBER COUNTER1[7:0] 0 7 0 8-BIT UNSIGNED NUMBER COUNTER0[7:0] 11115-024 15 11115-023 Figure 44. Synchronizing Phase A and Phase B ADE7912/ADE7913 Devices with Phase C ADE7912/ADE7913 Figure 46. Counter Start Value Communicated Using Two 8-Bit Registers Consider the example shown in Figure 44: the Phase A, Phase B, and Phase C counters of three ADE7912/ADE7913 devices are shown for the meter configuration shown in Figure 35. All three phases are out of synchronization. It is desirable to synchronize the Phase A and Phase B ADE7912/ADE7913 devices with the Phase C ADE7912/ADE7913, which is considered the reference because it generates the DREADY signal. Rev. 0 | Page 29 of 44 ADE7912/ADE7913 Data Sheet Phase Y that is required to bring Phase Y in synchronization to Phase X is as follows: When the DREADY active low pulses are generated, execute the following steps immediately after the output registers (IWV, V1WV, V2WV, ADC_CRC, STATUS0, and CNT_SNAPSHOT) are read: 1. 2. 3. ADC Cycle 0. Disable the protection of the configuration registers by setting the lock register to 0x9C (see the Protecting the Integrity of Configuration Registers section). Set the 8-bit register SYNC_SNAP to 0x02 using a write broadcast command. The CA, CB, and CC values of the three counters are latched and stored in the CNT_SNAPSHOT register of each device. ADC Cycle 1. The ADE7912/ADE7913 counters (CA, CB, and CC) latched at Cycle 0 are read in burst mode from the CNT_SNAPSHOT register together with the IWV, V1WV, V2WV, ADC_CRC, and STATUS0 registers. ADC Cycle 2. Because CA > CC, the following equation can be written: 4. 5. 6. If CY > CX, then CY* = C X + C 0 − CY (10) If CY ≤ CX, then CY* = C X − CY (11) ADC Cycle 3. The Phase A and Phase B ADE7912/ADE7913 counters start counting down based on the COUNTER1 and COUNTER0 values written during ADC Cycle 2. ADC Cycle 4. All ADE7912/ADE7913 devices generate ADC outputs synchronously. To verify this, as a good programming practice, read the counters again so that the SYNC_SNAP = 0x02 command is executed one more time. ADC Cycle 5. The ADE7912/ADE7913 counters (CA, CB, and CC), latched after the SYNC_SNAP = 0x02 command, are stored in the CNT_SNAPSHOT register and are read in burst mode. They show the same value, ±1 LSB, which means ±1 CLKIN cycle (±244 ns for CLKIN = 4.096 MHz). CC = CA ± 1 = CB ± 1 CC + C 0 = C A + C *A 7. where C *A is the new value that must be determined. The new initial counter value, C*A = CC + C0 − C A , is written into the Phase A ADE7912/ADE7913 (labeled ADE7912A/ADE7913A in Figure 44) in two consecutive 8-bit writes to the COUNTER0 and COUNTER1 registers. The Phase A ADE7912/ADE7913 device is in synchronization with the Phase C ADE7912/ADE7913 starting with ADC Cycle 4. Because CB < CC, the following equation can be written: CC = C B + C B* where C B* is the new value that must be determined. The new initial counter value, C*B = CC − C B , is written into the Phase B ADE7912/ADE7913 in two consecutive 8bit writes to the COUNTER0 and COUNTER1 registers. Phase B ADE7912/ADE7913 is in synchronization with the Phase C ADE7912/ADE7913 starting with ADC Cycle 4. As demonstrated, if the latched value of the counter on the reference Phase X is CX and the initial value of the counter is C0 (see Table 1), the new value of the counter on Reenable protection of the configuration registers by setting the lock register to 0xCA (see the Protecting the Integrity of Configuration Registers section). The ±1 LSB error may appear because CLKIN, the internal clock of the ADE7912/ADE7913, is asynchronous to the serial port clock generated by the microcontroller and is used to write the COUNTER1 and COUNTER0 values during ADC Cycle 2. The EMI reduction scheme managed by the EMI_CTRL register (see the DC-to-DC Converter section for details) requires that the ADE7912/ADE7913 devices of the meter system provide coherent samples. This EMI reduction scheme ensures that one ADE7912/ADE7913 device does not generate the PWM signals required to manage the dc-to-dc converter at the same moment as another ADE7912/ADE7913. The ±1 LSB error in the counter synchronization means that at least two ADE7912/ ADE7913 devices generate PWM signals simultaneously for one CLKIN cycle and the EMI reduction scheme may be affected. Although there are no guarantees, both synchronization procedures outlined in this section can be repeated until CC = CA = CB. Rev. 0 | Page 30 of 44 Data Sheet ADE7912/ADE7913 POWER MANAGEMENT DC-TO-DC CONVERTER The dc-to-dc converter section of the ADE7912/ADE7913 works on principles that are common to most modern power supply designs. VDD power is supplied to an oscillating circuit that drives the primary side of a chip scale air core transformer. Power is transferred to the secondary side, where it is rectified to a 3.3 V dc voltage. This voltage is then supplied to the ADC side section through a 2.5 V LDO regulator. The internal dc-to-dc converter state of the ADE7912/ADE7913 is controlled by the input, VDD. In normal operation mode, maintain VDD between 2.97 V and 3.63 V. The block diagram of the isolated dc-to-dc converter is shown in Figure 47. The ADE7912/ADE7913 primary supply voltage VDD input supplies an alternative current (ac) source. The ac signal passes through a chip scale air core transformer, and it is transferred to the secondary side. A rectifier then produces the isolated power supply, VDDISO. Using another chip scale air core transformer, a feedback circuit measures VDDISO and passes the information back into the VDD domain, where a PWM control block controls the ac source to maintain VDDISO at 3.3 V. ISOLATION BARRIER RECTIFIER AC SOURCE FEEDBACK CIRCUIT PWM CONTROL VDD = 3.3V The clock that manages the PWM control block is divided into eight periodical slots, 0 to 7, as shown in Figure 48. Each bit of the EMI_CTRL register controls one slot: Bit 0 controls Slot 0, Bit 1 controls Slot 1, …, Bit 7 controls Slot 7. When the bit is 1, the default value, the PWM control block generates a pulse. When the bit is 0, the PWM control block does not generate a pulse. The recommendation is to have only four of these bits set to 1 while keeping the others at 0 for every ADE7912/ADE7913 used in the system to further reduce the emissions generated by the ADE7912/ADE7913 dc-to-dc converter. If the 3-phase energy meter contains four ADE7912/ADE7913 devices, the ADE7912/ADE7913 devices must first be synchronized (see the Synchronizing Multiple ADE7912/ADE7913 Devices section). Then the EMI_CTRL register of every ADE7912/ADE7913 must be initialized. The dc-to-dc converters of only two ADE7912/ADE7913 devices generate EMI at the same moment, lowering the overall EMI level of the meter. Initialize the EMI_CTRL register of the Phase A ADE7912/ADE7913 (EMI_CTRLA) to 0x55, EMI_CTRLB to 0xAA, EMI_CTRLC to 0x55, and EMI_CTRLN to 0xAA (see Figure 49). ADE7912/ADE7913 PHASE B, PHASE N PWM PULSE Figure 47. Isolated DC-to-DC Converter Block Diagram The PWM control block works at a CLKIN/4 (1.024 MHz) clock, and every half period generates a PWM pulse to the ac source (see Figure 48). ADE7912/ADE7913 PHASE A, PHASE C PWM PULSE 1.024MHz CLOCK PWM CONTROL PULSE 0 1 2 3 4 5 6 7 0 1 1.024MHz CLOCK 0 1 2 3 4 5 6 7 0 1 11115-026 A, C B, N A, C B, N A, C B, N A, C B, N A, C B, N Figure 48. PWM Control Block Generates Pulses Based on a 1.024 MHz Clock Figure 49. EMI Management of a 3-Phase Meter with Four ADE7912/ADE7913 Devices If the system contains one, two, or three ADE7912/ADE7913 devices, set four bits to 1 in the EMI_ CTRL register according to the approach shown in Figure 49, while leaving some of the slots unused. Rev. 0 | Page 31 of 44 11115-027 VDDISO 11115-025 TO ADC BLOCK Every time a PWM pulse is generated, the ac source transmits very high frequency signals across the isolation barrier to allow efficient power transfer through the small chip scale transformers. This transfer creates high frequency currents that can propagate in the circuit board ground and power planes, causing edge and dipole radiation. The Layout Guidelines section describes the best PCB layout approach to manage the electromagnetic interference (EMI) issues. In addition to the layout approach, the 8-bit EMI_CTRL register helps to reduce the emissions generated by the ADE7912/ADE7913 dc-to-dc converter. ADE7912/ADE7913 Data Sheet MAGNETIC FIELD IMMUNITY The ADE7912/ADE7913 are immune to dc magnetic fields because they use air core transformers. The limitation on the ADE7912/ADE7913 ac magnetic field immunity is set by the condition in which the induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3.3 V operating condition is examined because it is the nominal supply of the ADE7912/ADE7913. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by dB 2 V = − ∑ πrn dt n =1 N (12) where: B is the ac magnetic field: Β(t) = B × sin(ωt). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil. Given the geometry of the receiving coil in the ADE7912/ ADE7913 and an imposed requirement that the induced voltage, VTHR, be at most 50% of the 0.5 V margin at the decoder, a maximum allowable external magnetic field, B, is calculated, as shown in Equation 13 and Figure 50. VTHR (13) N 2πf × ∑ π rn2 The preceding magnetic field values correspond to specific current magnitudes at given distances from the ADE7912/ ADE7913 transformers. I= (14) n =1 where µ0 is 4π × 10 H/m, the magnetic permeability of the air. −7 Figure 51 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 51, the ADE7912/ADE7913 are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 10 kHz example previously noted, a current with an amplitude of 69 kA placed mm from the ADE7912/ADE7913 is required to affect component operation. Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Take care in the layout of such traces to avoid this possibility (see the Layout Guidelines section). n =1 1000 MAXIMUM ALLOWABLE CURRENT (kA) where: f is the frequency of the magnetic field. B is the amplitude of the ac magnetic field. 100 10 1 0.1 100 0.005m 0.1m 1m 10 1 0.1 0.01 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 0.01 Figure 51. Maximum Allowable Current for Various Current-toADE7912/ADE7913 Spacings 0.001 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 11115-028 MAGNETIC FIELD MAXIMUM AMPLITUDE (T) B V ×d × 2πd = N μ0 μ 0 × f × ∑ π rn2 Figure 50. Maximum Allowable External Magnetic Field Rev. 0 | Page 32 of 44 11115-029 B= For example, at a magnetic field frequency of 10 kHz, the maximum allowable magnetic field of 2.8 T induces a voltage of 0.25 V at the receiving coil. This voltage is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from more than 1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. Data Sheet ADE7912/ADE7913 POWER-UP AND INITIALIZATION PROCEDURES until Bit 0 (RESET_ON) is cleared to 0. This happens approximately 20 ms after the ADE7912/ADE7913 start to function and indicates that the nonisolated side of the ADE7912/ADE7913 is fully functional using the default settings. Initialize the CONFIG register and the EMI_CTRL emissions control register. Protect the user accessible and internal configuration registers by setting the lock register to 0xCA. See the Protecting the Integrity of Configuration Registers section. When the ADC conversion data is available, the ADE7912/ADE7913 device begins generating a signal that is active low at the CLKOUT/DREADY pin for 64 CLKIN cycles (15.625 µs for CLKIN = 4.096 MHz). DREADY functionality is enabled by default at the CLKOUT/DREADY pin. The microcontroller reads the IWV, V1WV, V2WV, ADC_CRC, and STATUS0 registers in SPI burst mode (see the SPI Read Operation in Burst Mode section for more information). At power-up or after a hardware or software reset, the following steps must be executed for a microcontroller managing a system formed by one or multiple ADE7912/ADE7913 devices. Power-Up Procedure for Systems with a Single ADE7912/ADE7913 5. For one standalone ADE7912/ADE7913 device managed by a microcontroller, the power-up procedure is as follows (see Figure 52): 6. 1. 2. 7. 4. 8. Note that this power-up procedure also applies in the same way to systems that have multiple ADE7912/ADE7913 devices, each clocked from its own crystal. Every ADE7912/ADE7913 device is powered up and started independently. 3.3V – 10% ≈2.6V ADE7912/ADE7913 NONISOLATED SIDE READY ADE7912/ADE7913 ISOLATED SIDE READY 0V 20ms 23ms ADE7912/ADE7913 POWERED UP POR TIMER TURNED ON 100ms ADE7912/ADE7913 START FUNCTIONING BIT STATUS0[0] (RESET_ON) CLEARED TO 0 DC-TO-DC CONVERTER POWERED UP AND Σ-Δ MODULATORS FUNCTIONAL Figure 52. Power-Up Procedure for Systems with One or Multiple ADE7912/ADE7913 Devices, Each Clocked from Its Own Crystal Rev. 0 | Page 33 of 44 11115-030 3. Connect a crystal between the XTAL1 and XTAL2 pins. Supply VDD to the ADE7912/ADE7913 device. To ensure that the ADE7912/ADE7913 device starts functioning correctly, the supply must reach 3.3 V − 10% in less than 23 ms from approximately a 2.6 V level. The ADE7912/ ADE7913 device starts to function. The dc-to-dc converter powers up and supplies the isolated side of the ADE7912/ADE7913. The Σ-Δ modulators become functional. This process takes approximately 100 ms to execute when the recommended capacitors on the VDDISO, LDO, and REF pins described in Table 9 are used. After this time, the isolated side of the ADE7912/ADE7913 is fully functional. To determine when the ADE7912/ADE7913 device is ready to accept commands, read the STATUS0 register ADE7912/ADE7913 Data Sheet Power-Up Procedure for Systems with Multiple Devices That Use a Single Crystal For the polyphase energy meters shown in Figure 35, Figure 37, and Figure 38, in which one single crystal is used, the power-up procedure is as follows (see Figure 53): 1. 2. 3. 4. 5. 6. Supply VDD to the ADE7912/ADE7913 devices. To ensure that the Phase A ADE7912/ADE7913 (labeled ADE7912A/ ADE7913A in Figure 53) device starts functioning correctly, the supply must reach 3.3 V − 10% in less than 23 ms from approximately a 2.6 V level. The ADE7912A/ADE7913A device is clocked by the 4.096 MHz crystal and starts functioning. The other ADE7912/ADE7913 devices are not clocked yet. The dc-to-dc converter powers up and supplies the isolated side of the ADE7912A/ADE7913A. The Σ-Δ modulators become functional. This process takes approximately 100 ms to execute when the recommended capacitors on the VDDISO, LDO, and REF pins described in Table 9 are used. After this time, the isolated side of the ADE7912A/ADE7913A is fully functional. To determine when the ADE7912A/ADE7913A device is ready to accept commands, the STATUS0 register is read until Bit 0 (RESET_ON) is cleared to 0. This happens approximately 20 ms after the ADE7912A/ADE7913A start to function and indicates that the nonisolated side of the ADE7912A/ADE7913A is fully functional using the default settings. Initialize the CONFIG register of the ADE7912A/ADE7913A with Bit 0 (CLKOUT_EN) set to 1. The CLKOUT signal is provided at the CLKOUT/DREADY pin, and the ADE7912/ ADE7913 devices on the other phases are now clocked. Initialize EMI_CTRL, the emissions control register, of the ADE7912A/ADE7913A. The dc-to-dc converters of the other ADE7912/ADE7913 devices power up and supply their isolated sides. The Σ-Δ modulators become functional. This process takes approximately 100 ms to execute when the recommended capacitors on the VDDISO, LDO, and REF pins described in Table 9 are used. The isolated sides of the ADE7912/ ADE7913 devices are now fully functional. 7. Read the STATUS0 registers of the other ADE7912/ ADE7913 devices until Bit 0 (RESET_ON) is cleared to 0, indicating that their nonisolated sides are fully functional with default settings. This happens approximately 20 ms after the clock signal is provided. 8. Initialize the CONFIG register of all remaining ADE7912/ ADE7913 devices. Select one ADE7912/ADE7913 device (Phase C ADE7912/ADE7913 in Figure 35, Figure 37, and Figure 38 examples; labeled ADE7912C/ADE7913C in Figure 53) and connect its CLKOUT/DREADY pin to an external interrupt I/O pin of the microcontroller. ADE7912C/ ADE7913C must have Bit 0 (CLKOUT_EN) in the CONFIG register left at the default value of 0 to use the DREADY functionality of the CLKOUT/DREADY pin. 9. Initialize EMI_CTRL, the emissions control register, of all remaining ADE7912/ADE7913 devices. 10. Execute a SYNC_SNAP = 0x01 write broadcast to synchronize all the ADE7912/ADE7913 devices of the meter (see the Synchronizing Multiple ADE7912/ADE7913 Devices sections). 11. Execute a lock = 0xCA write broadcast to protect the configuration registers of all ADE7912/ADE7913 devices. See the Protecting the Integrity of Configuration Registers section. 12. Every couple of seconds, disable the protection of the configuration registers, execute a SYNC_SNAP = 0x02 write broadcast to read the CNT_SNAPSHOT register of every ADE7912/ADE7913, and verify if resynchronization is necessary. Resynchronize the ADE7912/ADE7913 devices that are out of synchronization (see the Synchronizing Multiple ADE7912/ADE7913 Devices section) and then reenable the protection of the configuration registers. Rev. 0 | Page 34 of 44 Data Sheet ADE7912/ADE7913 ADE7912 B/ADE7913 B, ADE7912 C/ADE7913 C, ADE7912 N/ADE7913 N, NONISOLATED SIDE READY ≈2.6V ADE7912 A/ADE7913 A ISOLATED SIDE READY ADE7912 A/ADE7913 A NONISOLATED SIDE READY 3.3V – 10% ADE7912 B/ADE7913 B, ADE7912 C/ADE7913 C, ADE7912 N/ADE7913 N, ISOLATED SIDE READY 0V 20ms ALL ADE7912/ADE7913s POWERED UP ADE7912 A/ ADE7913 A POR TIMER TURNED ON 100ms ADE7912 A/ ADE7913 A START FUNCTIONING 100ms ADE7912 A/ ADE7913 A BIT STATUS0[0] (RESET_ON) CLEARED TO 0 MICROPROCESSOR SETS ADE7912 A/ ADE7913 A BIT CONFIG[0] TO 1. ADE7912 A/ADE7913 A GENERATE CLKOUT ADE7912 A/ADE7913 A DC-TO-DC CONVERTER POWERED UP AND ITS Σ-Δ MODULATORS FUNCTIONAL ADE7912 B/ADE7913 B, ADE7912 C/ADE7913 C, ADE7912 N/ADE7913 N DC-TO-DC CONVERTERS POWERED UP AND Σ-Δ MODULATORS FUNCTIONAL ADE7912 B/ADE7913 B, ADE7912 C/ADE7913 C, ADE7912 N/ADE7913 N BIT STATUS0[0] (RESET_ON) CLEARED TO 0 11115-031 23ms 20ms Figure 53. Power-Up Procedure for Systems with Multiple ADE7912/ADE7913 Devices; Only Phase A ADE7912/ADE7913 Are Clocked from a Crystal 3.3V – 10% ≈2.6V ALL ADE7912/ ADE7913s NONISOLATED SIDE READY ALL ADE7912/ ADE7913s ISOLATED SIDE READY 0V 20ms ALL ADE7912/ADE7913s POWERED UP ADE7912/ADE7913s POR TIMERS TURNED ON MICROPROCESSOR ADE7912/ADE7913s BIT GENERATES CLOCK STATUS0[0] (RESET_ON) TO ADE7912/ADE7913s CLEARED TO 0 ADE7912/ADE7913s DC-TO-DC CONVERTERS POWERED UP AND Σ-Δ MODULATORS FUNCTIONAL Figure 54. Power-Up Procedure for Systems with Multiple ADE7912/ADE7913 Devices Clocked from a Microcontroller Rev. 0 | Page 35 of 44 11115-032 100ms ADE7912/ADE7913 Data Sheet Power-Up Procedure for Systems with Multiple Devices That Use Clock Generated from Microcontroller For polyphase energy meters in which the microcontroller generates the clock signal used by all ADE7912/ADE7913 devices (see Figure 36), the power-up procedure is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. Supply VDD to the ADE7912/ADE7913 devices. To ensure that the ADE7912/ADE7913 devices start functioning correctly, the supply must reach 3.3 V − 10% in less than 23 ms from approximately a 2.6 V level. Generate the clock signal from the microcontroller to all ADE7912/ADE7913 devices. The dc-to-dc converters power up and supply the isolated side of the ADE7912/ADE7913 devices. The Σ-Δ modulators become functional. This process takes approximately 100 ms to execute when the recommended capacitors on the VDDISO, LDO, and REF pins described in Table 9 are used. After this time, the isolated sides of the ADE7912/ADE7913 devices are fully functional. Read the STATUS0 registers of the ADE7912/ADE7913 devices until Bit 0 (RESET_ON) is cleared to 0, indicating that the nonisolated side of the ADE7912/ADE7913 devices is fully functional with default settings. This happens approximately 20 ms after the clock signal is provided. Initialize the CONFIG register of the ADE7912/ADE7913 devices with Bit 0 (CLKOUT_EN) cleared to 0 to avoid generating an unnecessary clock at the CLKOUT/DREADY pin. Select one ADE7912/ADE7913 device (Phase C ADE7912/ADE7913 in Figure 36, for example) and connect its CLKOUT/DREADY pin to an external interrupt I/O pin of the microcontroller. Initialize EMI_CTRL, the emissions control register, of all ADE7912/ADE7913 devices. Execute a SYNC_SNAP = 0x01 write broadcast to synchronize all the ADE7912/ADE7913 devices of the meter (see the Synchronizing Multiple ADE7912/ADE7913 Devices sections for details). Execute a lock = 0xCA write broadcast to protect the configuration registers of all ADE7912/ADE7913 devices. See the Protecting the Integrity of Configuration Registers section. Every couple of seconds, disable the registers protection, execute a SYNC_SNAP = 0x02 write broadcast to read the COUNTER1 and COUNTER0 registers of every ADE7912/ADE7913, and verify if resynchronization is necessary. Resynchronize the ADE7912/ADE7913 devices that are out of synchronization (see the Synchronizing Multiple ADE7912/ADE7913 Devices section) and then reenable protection of the configuration registers. HARDWARE RESET The ADE7912/ADE7913 do not have a dedicated reset pin. Instead, while the SCLK pin is receiving the serial clock, the CS and MOSI pins can be kept low by executing a SPI broadcast write operation in which the lines are kept low for 64 SCLK cycles. This is equivalent to sending eight bytes equal to 0x00 to the ADE7912/ADE7913 to accomplish a hardware reset. During a hardware reset, all the registers are set to their default values and the dc-to-dc converter is shut down. This procedure can be done simultaneously for all ADE7912/ADE7913 devices in a polyphase energy meter. At the end of the reset period, the ADE7912/ADE7913 clears Bit 0 (RESET_ON) to 0 in the STATUS0 register. At this point, one of the procedures described in the Power-Up and Initialization Procedures section must be followed to initialize the ADE7912/ADE7913 devices correctly. SOFTWARE RESET Bit 6 (SWRST) in the CONFIG register manages the software reset functionality. The default value of this bit is 0. If this bit is set to 1, the ADE7912/ADE7913 enter the software reset state. In this state, all the internal registers are reset to their default values. The dc-to-dc converter continues to function. When the software reset ends, Bit 6 (SWRST) in the CONFIG register clears automatically to 0 and Bit 0 (RESET_ON) in the STATUS0 register is cleared to 0. If the configuration registers are protected using a lock = 0xCA register write, first unlock the registers by writing lock = 0x9C and then write to the CONFIG register by setting Bit 6 (SWRST) to 1 to start a software reset. At this point, one of the procedures described in the Power-Up and Initialization Procedures section must be followed to initialize the ADE7912/ADE7913 correctly. POWER-DOWN MODE There are situations in which the ADCs of the ADE7912/ ADE7913 do not need to function and it is desirable to lower the current consumption of the device. When set to 1, Bit 2 (PWRDWN_EN) in the CONFIG register turns off the dc-todc converter and shuts down the Σ-Δ modulators. Although the ADE7912/ADE7913 configuration registers maintain their values, the IWV, V1WV, and V2WV ADC output registers are in an undefined state. If PWRDWN_EN is cleared to 0, the default value, the dc-to-dc converter is functional and the Σ-Δ modulators are active. If the microcontroller generates the clock to all ADE7912/ ADE7913 devices (the configuration shown in Figure 36), the current consumption can be further reduced by shutting down the clock. The ADE7912/ADE7913 stop functioning. When the clock is restarted, as a good programming practice, execute a hardware reset to restart the ADE7912/ADE7913. In systems in which the CLKOUT/DREADY pin of one ADE7912/ ADE7913 device is used to clock other ADE7912/ADE7913 devices (the configuration shown in Figure 35, Figure 37, and Figure 38), lower current consumption of the ADE7912/ADE7913 devices can be achieved by clearing Bit 0 (CLKOUT_EN) to 0 in the CONFIG register. Rev. 0 | Page 36 of 44 Data Sheet ADE7912/ADE7913 LAYOUT GUIDELINES Figure 20 shows the test circuit of the ADE7912/ADE7913. The test circuit contains three ADE7912/ADE7913 devices together with the surrounding circuitry required to sense the phase currents and voltages in a 3-phase system. The ADE7912/ ADE7913 devices are managed by a microcontroller using the SPI interface. The microcontroller is not shown in the schematic. Figure 20 replicates the schematic of the ADE7913 evaluation board (see the ADE7913 Evaluation Board section). Figure 55 and Figure 56 show a proposed layout of a printed circuit board (PCB) with two layers that have the components placed on the top of the board only. Follow these layout guidelines to create a low noise design with higher immunity to EMC influences. Note that the layout is cropped from a board containing other circuitry besides the three ADE7913 devices. The layout of an ADE7912-based meter is very similar to the one designed for the ADE7913. The only difference is the absence of the V2P voltage channel, which means the absence of the related circuitry: the resistor divider and the protection diodes. Use a 10 µF capacitor and a 100 nF ceramic capacitor to decouple VDDISO, Pin 1, from GNDISO, Pin 2. Apply the same rules in the placement of these capacitors as for the VDD pin. Use a 4.7 µF capacitor and a 100 nF, ceramic capacitor to decouple LDO, Pin 8, and REF, Pin 9, from GNDISO, Pin 10. Use the same rules in the placement of these capacitors as for the VDD pin. Note that the ADE7912/ADE7913 isolated ground point is one of the shunt poles. This point is directly connected to GNDISO, Pin 10. There is no need to connect the shunt ground pole to GNDISO, Pin 2. Pin 2 is internally connected to Pin 10. The crystal load capacitors must be placed closest to the ADE7912/ADE7913, whereas the crystal can be placed in close proximity. Note that the bottom layer extends the ground of the primary side below the ADE7912/ADE7913 and the related circuitry. A distance of at least 8 mm is maintained on the bottom layer between the input pins on the board and the primary side ground plane. 11115-043 The primary supply voltage is supplied at VDD, Pin 19. Place a 10 µF decoupling capacitor and a 100 nF ceramic decoupling capacitor between the VDD pin and GND, Pin 20. The 10 µF capacitor must be placed in close proximity to the part, but the ceramic capacitor must be placed closer to the ADE7912/ ADE7913 because it decouples the high frequency noise. Figure 55. 2-Layer Circuit Board: Top Layer Rev. 0 | Page 37 of 44 ADE7912/ADE7913 Data Sheet 11115-044 8mm Figure 56. 2-Layer Circuit Board: Bottom Layer 11115-045 8mm Figure 57. 4-Layer Circuit Board: Top Layer Rev. 0 | Page 38 of 44 ADE7912/ADE7913 11115-046 Data Sheet Figure 58. 4-Layer Circuit Board: Bottom Layer ISOLATED SIDE GROUND PLANE ON TOP LAYER PRIMARY SIDE GROUND PLANE ON TOP LAYER ADE7912/ADE7913 PRIMARY SIDE GROUND PLANE ON LAYER 2 C12 C23 4mils = 0.1016mm 28mils = 0.7112mm 1mm 8mm PRIMARY SIDE GROUND PLANE ON BOTTOM LAYER 11115-047 28mils = 0.7112mm ISOLATED SIDE GROUND PLANE ON LAYER 3 Figure 59. Stitching Capacitors Created by 4-Layer PCB If a 4-layer PCB is used, additional stitching capacitors can be created. On the top layer, all components placed on the isolated secondary side are surrounded by a ground plane connected to GNDISO, Pin 10 (see Figure 57). Layer 2 (see Figure 60) replicates the bottom layer of the 2-layer circuit board approach, extending the ground of the primary side below the ADE7912/ADE7913 and the related circuitry. Layer 3 (see Figure 61) replicates the ground plane of the top layer. The bottom layer does not have the ground of the primary side below the ADE7912/ADE7913 and the related circuitry as in the 2-layer circuit board approach because the corresponding stitching capacitor created with Layer 3 does not have any effect in reducing the emissions. The structure of the stitching capacitors created by a 4-layer PCB is shown in Figure 59. The isolated ground plane of the top layer creates the 10 pF capacitor (C12) with the primary side ground plane placed on Layer 2. In a similar manner, the 400 pF (C23) capacitor is created between Layer 2 and Layer 3. These capacitances have an important role in reducing the emissions generated by the ADE7912/ADE7913 dc-to-dc converter. ADE7913 EVALUATION BOARD An evaluation board built upon the ADE7913 allows users to quickly evaluate this IC. It is used in conjunction with the system demonstration platform (EVAL-SDP-CB1Z). Order both the ADE7913 evaluation board and the system demonstration platform to evaluate the ADE7913. Visit www.analog.com/ADE7913 for details. ADE7912/ADE7913 VERSION Bits[2:0] (version) in the STATUS1 register identify the version of the ADE7912/ADE7913. Rev. 0 | Page 39 of 44 Data Sheet 11115-048 ADE7912/ADE7913 11115-049 Figure 60. 4-Layer Circuit Board: Layer 2 Figure 61. 4-layer Circuit Board: Layer 3 Rev. 0 | Page 40 of 44 Data Sheet ADE7912/ADE7913 REGISTER LIST In Table 13 to Table 20, R means a register can be read, and W means a register can be written. U means an unsigned register, and S means a signed register in twos complement format. Table 13. Register List Address 0x0 0x1 0x2 0x3 0x4 Register Name IWV V1WV V2WV Reserved ADC_CRC R/W R R R R R Bit Length 24 24 24 24 16 Type S S S S U Default Value 0x000000 0x000000 0x000000 0x000000 N/A 0x5 CTRL_CRC R 16 U N/A 0x6 0x7 Reserved CNT_SNAPSHOT R R 16 16 S U 0x0000 0x00 0x8 0x9 0xA CONFIG STATUS0 Lock R/W R W 8 8 8 U U U 0 0x01 0x00 0xB 0xC SYNC_SNAP COUNTER0 W R/W 8 8 U U 0x00 N/A 0xD COUNTER1 R/W 8 U N/A 0xE EMI_CTRL R/W 8 U 0xFF 0xF 0x10, 0x11 0x12, 0x13 0x14 0x15, 0x16, 0x17 0x18 STATUS1 Reserved Reserved Reserved Reserved R R/W R 8 8 8 U U U 0x00 0x00 0x00 R 8 U 0x00 TEMPOS R 8 S N/A Description Instantaneous value of Current I. Instantaneous value of Voltage V1. Instantaneous value of Voltage V2. Reserved. This location always reads 0x000000. CRC value of IWV, V1WV, and V2WV registers. See the ADC Output Values CRC section for details. CRC value of configuration registers. See the CRC of Configuration Registers for details. Reserved. This location always reads 0x0000. Snapshot value of the counter used in synchronization operation. See Table 14 and the Synchronizing Multiple ADE7912/ADE7913 Devices section for details. Configuration register. See Table 15 for details. Status register. See Table 16 for details. Memory protection register. See the Protecting the Integrity of Configuration Registers section and Table 17 for details. Synchronization register. See Table 18 for details. Contains the least significant eight bits of the internal synchronization counter. COUNTER1[3:0] bits contain the most significant four bits of the internal synchronization counter. See the Synchronizing Multiple ADE7912/ADE7913 Devices section for details. EMI control register. Manages the PWM control block of the isolated dc-to-dc converter to reduce EMI emissions (see Table 19 and the DC-to-DC Converter section for details). Status register. See Table 20 for details. For proper operation, do not write to these registers. Reserved registers. No functionality assigned at this address. Reserved registers. Temperature sensor offset. See the Temperature Sensor section for more information. Table 14. CNT_SNAPSHOT Register (Address 0x7) Bit Location 11:0 15:12 Bit Name Counter Reserved Default Value 0x000 0000 Description Snapshot value of the counter used in synchronization operation. Reserved. These bits do not represent any functionality. Rev. 0 | Page 41 of 44 ADE7912/ADE7913 Data Sheet Table 15. CONFIG Register (Address 0x8) Bit Location 0 Bit Name CLKOUT_EN Default Value 0 1 2 Reserved PWRDWN_EN 0 0 3 TEMP_EN 0 5:4 ADC_FREQ 00 6 SWRST 0 7 BW 0 Description Enables CLKOUT functionality at the CLKOUT/DREADY pin. When CLKOUT_EN = 0, the default value, DREADY functionality is enabled. When CLKOUT_EN = 1, CLKOUT functionality is enabled. Reserved. This bit does not manage any functionality. Shuts down the dc-to-dc converter. When PWRDWN_EN = 0, the default value, the dc-to-dc converter is functional and the Σ-Δ modulators are active. When PWRDWN_EN = 1, the dc-to-dc converter is turned off and the Σ-Δ modulators are shut down. This bit selects the second voltage channel measurement. When the TEMP_EN bit is set to 0, the default value, the voltage between the V2P and VM pins is measured. When this bit is 1, the internal temperature sensor is measured (see the Temperature Sensor section for more information). In the case of the ADE7912, the internal temperature sensor is always measured, and this bit does not have any significance. These bits select the ADC output frequency. 00 = 8 kHz, 125 µs period. 01 = 4 kHz, 250 µs period. 10 = 2 kHz, 500 µs period. 11 = 1 kHz, 1 ms period. When this bit is set to 1, a software reset is initiated. This bit clears itself to 0 after one CLKIN cycle. Selects the bandwidth of the digital low-pass filter of the ADC. When BW = 0, the default value, the bandwidth is 3.3 kHz. When BW = 1, the bandwidth is 2 kHz. The bandwidth data is for CLKIN = 4.096 MHz and an ADC output frequency of 8 kHz. See the Analog-to-Digital Conversion section for details on how CLKIN and the ADC output frequency influence the bandwidth selection. Table 16. STATUS0 Register (Address 0x9) Bit Location 0 Bit Name RESET_ON Default Value 1 1 2 CRC_STAT IC_PROT 0 0 7:3 Reserved 0 Description During reset, the RESET_ON bit is set to 1. When the reset ends and the ADE7912/ADE7913 are ready to be configured, the RESET_ON bit is cleared to 0. If the CRC of the configuration registers changes value, CRC_STAT bit is set to 1. If the configuration registers are not protected, this bit is 0. After the configuration registers are protected (lock register = 0xCA), this bit is set to 1. Reserved. These bits do not represent any functionality. Table 17. Lock Register (Address 0xA) Bit Location 7:0 Bit Name LOCK_KEY Default Value 00000000 Description When the LOCK_KEY bits are equal to 0xCA, protection of the configuration registers is enabled. When the LOCK_KEY bits are equal to 0x9C, the protection is disabled and the configuration registers can be written. This is a write only register. If the address location is read, the value is 0x00. Table 18. SYNC_SNAP Register (Address 0xB) Bit Location 0 Bit Name Sync Default Value 0 1 Snap 0 7:2 Reserved 0 Description When the sync bit is set to 1 via a broadcast SPI write operation, the ADE7912/ADE7913 devices in the system generate ADC outputs in the same exact moment. The bit clears itself back to 0 after one CLKIN cycle. See the Synchronizing Multiple ADE7912/ADE7913 Devices section for more details. When snap is set to 1 via a broadcast SPI write operation, the internal counters of the ADE7912/ADE7913 devices in the system are latched. The bit clears itself back to 0 after one CLKIN cycle. See the Synchronizing Multiple ADE7912/ADE7913 Devices section for more details. Reserved. These bits do not represent any functionality. Rev. 0 | Page 42 of 44 Data Sheet ADE7912/ADE7913 Table 19. EMI_CTRL Register (Address 0xE) Bit Location 0 Bit Name SLOT0 Default Value 1 1 2 3 4 5 6 7 SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 1 1 1 1 1 1 1 Description Controls the PWM control block pulse during Slot 0 of the CLKIN/4 clock (see the DC-to-DC Converter section for details). Controls the PWM control block pulse during Slot 1 of the CLKIN/4 clock. Controls the PWM control block pulse during Slot 2 of the CLKIN/4 clock. Controls the PWM control block pulse during Slot 3 of the CLKIN/4 clock. Controls the PWM control block pulse during Slot 4 of the CLKIN/4 clock. Controls the PWM control block pulse during Slot 5 of the CLKIN/4 clock. Controls the PWM control block pulse during Slot 6 of the CLKIN/4 clock. Controls the PWM control block pulse during Slot 7 of the CLKIN/4 clock. Table 20. STATUS1 Register (Address 0xF) Bit Location 2:0 3 Bit Name Version ADC_NA Default Value 0 0 6:4 7 Reserved Reserved 0 0 Description The ADE7912/ADE7913 version number. If the ADC outputs are not accessed during one ADC output period, the ADC_NA bit is set to 1. When the STATUS1 register is read, the bit is cleared to 0. Reserved. These bits do not represent any functionality. Reserved. Internal functionality is associated with this bit. Rev. 0| Page 43 of 44 ADE7912/ADE7913 Data Sheet OUTLINE DIMENSIONS 15.40 15.30 15.20 1.93 REF 20 11 7.60 7.50 7.40 10.51 10.31 10.11 10 PIN 1 MARK 2.64 2.54 2.44 2.44 2.24 0.30 0.20 0.10 COPLANARITY 0.1 0.71 0.50 0.31 0.25 BSC GAGE PLANE 45° SEATING PLANE 1.27 BSC 1.01 0.76 0.51 0.46 0.36 0.32 0.23 8° 0° 11-15-2011-A 1 COMPLIANT TO JEDEC STANDARDS MS-013 Figure 62. 20-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-20-1) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADE7912ARIZ ADE7912ARIZ-RL ADE7913ARIZ ADE7913ARIZ-RL EVAL-ADE7913EBZ EVAL-SDP-CB1Z 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 20-Lead SOIC_IC 20-Lead SOIC_IC, 13” Tape and Reel 20-Lead SOIC_IC 20-Lead SOIC_IC, 13” Tape and Reel Evaluation Board Evaluation System Controller Board Package Option RI-20-1 RI-20-1 RI-20-1 RI-20-1 Z = RoHS Compliant Part. The EVAL-SDP-CB1Z is the controller board that manages the EVAL-ADE7913EBZ evaluation board. Both boards must be ordered together. ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11115-0-11/13(0) Rev. 0 | Page 44 of 44