PD- 91847A
IRFSL11N50A
HEXFET® Power MOSFET
l
l
l
l
l
Dynamic dv/dt Rating
Repetitive Avalanche Rated
Fast Switching
Ease of Paraleling
Simple Drive Requirements
D
VDSS = 500V
RDS(on) = 0.55Ω
G
ID = 11A
S
Description
Third Generation HEXFETs from International Rectifier provide the designer
with the best combination of fast switching, ruggedized device design, low onresistance and cost-effectiveness.
T O -26 2
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
11
7.0
44
190
1.3
± 30
390
11
19
4.1
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
0.75
40
°C
1
9/2/99
IRFSL11N50A
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
500
–––
–––
2.0
6.0
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.57
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
14
34
32
27
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
1426
208
9.6
1954
53
110
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.55
Ω
VGS = 10V, ID = 6.6A
4.0
V
VDS = VGS, ID = 250µA
–––
S
VDS = 50V, ID = 6.6A
25
VDS = 500V, VGS = 0V
µA
250
VDS = 400V, VGS = 0V, TJ = 150°C
100
VGS = 30V
nA
-100
VGS = -30V
51
ID = 11A
12
nC
VDS = 400V
23
VGS = 10V, See Fig. 6 and 13
–––
VDD = 250V
–––
ID = 11A
ns
–––
RG = 9.1Ω
–––
RD = 22Ω,See Fig. 10
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 400V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
11
––– –––
showing the
A
G
integral reverse
––– ––– 44
S
p-n junction diode.
––– ––– 1.5
V
TJ = 25°C, IS = 11A, VGS = 0V
––– 530 790
ns
TJ = 25°C, IF = 11A
––– 3.4 5.1
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 6.4mH
RG = 25Ω, IAS = 11A. (See Figure 12)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
ISD ≤ 11A, di/dt ≤ 185A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
2
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IRFSL11N50A
100
100
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
10
1
4.5V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
10
4.5V
100
1
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 175 ° C
TJ = 25 ° C
1
V DS = 50V
20µs PULSE WIDTH
6.0
7.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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100
Fig 2. Typical Output Characteristics
100
5.0
10
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
0.1
4.0
20µs PULSE WIDTH
TJ = 175 ° C
1
VDS , Drain-to-Source Voltage (V)
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
8.0
ID = 11A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFSL11N50A
V GS
C is s
C rs s
C os s
C , C ap acitanc e (pF )
10000
=
=
=
=
20
0V,
f = 1M Hz
C g s + C g d , Cd s S H O R T E D
C gd
C ds + C gd
VGS , Gate-to-Source Voltage (V)
100000
C iss
1000
C os s
100
10
C rs s
1
10
100
VDS = 400V
VDS = 250V
VDS = 100V
16
12
8
4
A
1
ID = 11A
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
1000
10
20
30
40
50
QG , Total Gate Charge (nC)
V C E , C o lle c to r-to -Em itte r V o lta g e (V )
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
1000
100
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10
TJ = 175 ° C
TJ = 25 ° C
1
10
100us
1ms
1
0.1
0.0
V GS = 0 V
0.4
0.8
1.2
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10us
1.6
0.1
10ms
TC = 25 ° C
TJ = 175 ° C
Single Pulse
10
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFSL11N50A
12
RD
VDS
VGS
10
D.U.T.
I D , Drain Current (A)
RG
+
-VDD
8
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
4
Fig 10a. Switching Time Test Circuit
VDS
2
90%
0
25
50
75
100
TC , Case Temperature
125
150
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
D = 0.50
0.20
0.1
0.10
P DM
0.05
t1
0.02
0.01
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFSL11N50A
D R IV E R
L
VDS
D .U .T
RG
+
- VD D
IA S
20V
0 .0 1 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
1000
1 5V
TOP
800
BOTTOM
ID
4.5A
7.8A
11A
600
400
200
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature( ° C)
IAS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
660
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
640
620
600
580
+
V
- DS
560
VGS
A
0
2
4
6
8
10
12
I av , A v alanc he C urrent (A)
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
V D S a v , A valanche V oltage (V )
QGS
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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IRFSL11N50A
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D=
Period
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRFSL11N50A
Package Outline
TO-262 Outline
Part Marking Information
TO-262
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
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IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
http://www.irf.com/
Data and specifications subject to change without notice. 9/99
8
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