MOTOROLA MC33493DTB

Freescale Semiconductor, Inc.
Technical Data
TANGO3
MC33493/D
Rev. 1.6, 6/2002
Freescale Semiconductor, Inc...
PLL tuned UHF
Transmitter for Data
Transfer Applications
PIN CONNECTIONS
FEATURES
•
Selectable frequency bands:
315-434MHz and 868-928MHz
•
OOK and FSK modulation
•
Adjustable output power range
•
Fully integrated VCO
•
Supply voltage range: 1.9-3.6V
•
Very low standby current: 0.1nA @ TA =25°C
•
Low supply voltage shutdown
•
Data clock output for microcontroller
•
Extended temperature range: -40°C to 125°C
•
Low external component count
•
Typical application compliant with ETSI standard
DATACLK
1
14
MODE
DATA
2
13
ENABLE
BAND
3
12
VCC
GND
4
11
GNDRF
XTAL1
5
10
RFOUT
XTAL0
6
9
VCC
REXT
7
8
CFSK
Ordering Information
Figure 1: Simplified block diagram
Device
Ambiant
Temperature
Range
Package
MC33493
DTB
-40°C to
125°C
TSSOP14
This document contains information on a new product under development. Motorola
reserves the right to change or discontinue this product without notice.
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© Motorola, Inc., 2002
PIN FUNCTION DESCRIPTION
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
PIN FUNCTION DESCRIPTION
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DATACLK
DATA
BAND
GND
XTAL1
XTAL0
REXT
CFSK
VCC
RFOUT
GNDRF
VCC
ENABLE
MODE
Description
Clock output to the microcontroller
Data input
Frequency band selection
Ground
Reference oscillator input
Reference oscillator output
Power amplifier output current setting input
FSK switch output
Power supply
Power amplifier output
Power amplifier ground
Power supply
Enable input
Modulation type selection input
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VCC
VGND - 0.3 to 3.7
V
VGND - 0.3
to VCC + 0.3
V
ESD HBM Voltage Capability on Each Pin (note 1)
±2000
V
ESD MM Voltage Capability on Each Pin (note 2)
±150
V
Supply Voltage
Voltage Allowed on Each Pin
Storage Temperature
Ts
-65 to +150
°C
Junction Temperature
Tj
+150
°C
Notes:
1 Human Body model, AEC-Q100-002 Rev. C.
2 Machine Model, AEC-Q100-003 Rev. E.
TRANSMITTER FUNCTIONAL DESCRIPTION
MC33493 is a PLL tuned low power UHF transmitter. The different modes of operation are controlled by the
microcontroller through several digital input pins. The power supply voltage ranges from 1.9V to 3.6V allowing
operation with a single lithium cell.
PHASE LOCKED LOOP AND LOCAL OSCILLATOR
The VCO is a completely integrated relaxation oscillator. The Phase Frequency Detector (PFD) and the loop filter
are fully integrated. The exact output frequency is equal to: fRFOUT = fXTAL x [PLL Divider Ratio]. The frequency
band of operation is selected through the BAND pin.
Table 1 provides details for each frequency band selection.
2
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RF OUTPUT STAGE
Table 1: Band selection and associated divider ratios
BAND Input
Frequency
PLL Divider
Crystal Oscillator
Level
Band (MHz)
Ratio
Frequency (MHz)
315
9.84
High
32
434
13.56
Low
868
64
An out-of-lock function is performed by monitoring the PFD output voltage. When it exceeds defined limits, the
RF output stage is disabled.
Freescale Semiconductor, Inc...
RF OUTPUT STAGE
The output stage is a single ended square wave switched current source. Harmonics are present in the output
current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical
application demonstrates compliance to ETSI standard.
A resistor Rext connected to the REXT pin controls the output power allowing a trade-off between radiated power
and current consumption.
The output voltage is internally clamped to Vcc ±2Vbe (typ. Vcc ±1.5V @ TA=25°C).
MODULATION
A low logic level has to be applied on pin MODE to select the On Off Keying (OOK) modulation. This modulation
is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output
stage state:
DATA=0 → output stage off,
DATA=1 → output stage on.
If a high logic level is applied on pin MODE, then Frequency Shift Keying (FSK) modulation is selected. This
modulation is achieved by crystal pulling. An internal switch connected to CFSK pin enables to switch the
external crystal load capacitors. Figure 2 shows the possible configurations: serial and parallel.
The logic level applied on pin DATA controls the state of this internal switch:
DATA=0 → switch off,
DATA=1 → switch on.
DATA input is internally re-synchronized by the crystal reference signal. The corresponding jitter on the data duty
cycle cannot exceed ±1 reference period (±75ns for a 13.56MHz crystal).
This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation
multiplied by the PLL Divider Ratio (see table 1).
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MICROCONTROLLER INTERFACE
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Figure 2: Crystal pulling configurations
MICROCONTROLLER INTERFACE
Four digital input pins (ENABLE, DATA, BAND and MODE) enable the circuit to be controlled by a
microcontroller. It is recommended to configure the band frequency and the modulation type before enabling the
circuit.
One digital output (DATACLK) provides to the microcontroller a reference frequency for data clocking. This
frequency is equal to the crystal oscillator frequency divided by 64 (see table 2).
Table 2: DATACLK frequency vs crystal oscillator frequency
Crystal Oscillator Frequency (MHz)
DATACLK Frequency (kHz)
9.84
154
13.56
212
STATE MACHINE
Figure 3 details the state machine.
4
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STATE MACHINE
Figure 3: State machine
Power ON
AND ENABLE=0
State 1
Standby mode
Freescale Semiconductor, Inc...
ENABLE=0
ENABLE=1
State 2
PLL out of lock-in range
No RF output
PLL in
lock-in range
PLL out of
lock-in range
ENABLE=0
State 4
Shutdown mode
Vbattery < Vshutdown
State 3
Transmission mode
State 1:
The circuit is in standby mode and draws only a leakage current from the power supply.
State 2:
In this state, the PLL is out of the lock-in range. Therefore the RF output stage is switched off preventing RF
transmission. Data clock is available on pin DATACLK. Each time the device is enabled, the state machine
passes through this state.
State 3:
In this state, the PLL is within the lock-in range. If t<tPLL_lock_in then the PLL can still be in acquisition mode. If
t≥tPLL_lock_in, then the PLL is locked.
Data entered on pin DATA are output on pin RFOUT according to the modulation selected by the level applied on
pin MODE.
State 4:
When the supply voltage falls below the shutdown voltage threshold (VSDWN) the whole circuit is switched off.
Applying a low level on pin ENABLE is the only condition to get out of this state.
Figure 4 shows the waveforms of the main signals for a typical application cycle.
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POWER MANAGEMENT
Figure 4: Signals waveforms and timings definition
ENABLE
DATACLK
tDATACLK_settling > tPLL_lock_in
tPLL_lock_in
€
Freescale Semiconductor, Inc...
DATA
MODE=0 (OOK)
RFOUT
MODE=1 (FSK)
fcarrier
fhigh
State 1
flow
State 2
fcarrier
fhigh
flow
State 3
fhigh
State 1
€ : PLL locked
POWER MANAGEMENT
When the battery voltage falls below the shutdown voltage threshold (VSDWN) the whole circuit is switched off. It
has to be noted that after this shutdown, the circuit is latched until a low level is applied on pin ENABLE (see
state 4 of the state machine).
DATA CLOCK
At start-up data clock timing is valid after the data clock settling time. As clock is switched off asynchronously,
the last period duration cannot be guaranteed.
6
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ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40°C;+125°C],
Rext=12kΩ+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output
load RL=50Ω+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics:
figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25°C.
Limits
Parameter
Test Conditions, Comments
Typ.
Max.
TA≤25°C
-
0.1
5
nA
TA=60°C
-
7
30
nA
TA=85°C
-
40
100
nA
1.4
TA=125°C
-
800
1700
nA
1.7
315 & 434 bands,
OOK and FSK modulation,
continuous wave, TA=25°C
-
11.6
13.5
mA
1.5
315 & 434 bands,
DATA=0, -40°C≤TA≤125°C
-
4.4
6.0
mA
868MHz band,
DATA=0, -40°C≤TA≤125°C
-
4.6
6.2
mA
1.8
315 & 434 bands,
OOK and FSK modulation,
continuous wave, -40°C≤TA≤125°C
-
11.6
14.9
mA
1.9
868MHz band,
OOK and FSK modulation,
continuous wave, -40°C≤TA≤125°C
-
11.8
15.1
mA
-
3
3.6
V
1
General Parameters
1.1
Freescale Semiconductor, Inc...
Unit
Min.
1.2
1.3
1.6
1.10
Supply Current in
Standby Mode
Supply Current in
Transmission Mode
Supply Voltage
1.11
TA=-40°C
-
2.04
2.11
V
1.12
TA=-20°C
-
1.99
2.06
V
TA=25°C
-
1.86
1.95
V
TA=60°C
-
1.76
1.84
V
1.15
TA=85°C
-
1.68
1.78
V
1.16
TA=125°C
-
1.56
1.67
V
1.13
1.14
Shutdown Voltage Threshold
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ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40°C;+125°C],
Rext=12kΩ+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output
load RL=50Ω+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics:
figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25°C.
Limits
Parameter
2
Freescale Semiconductor, Inc...
2.1
Test Conditions, Comments
Unit
Min.
Typ.
Max.
12
-
21
kΩ
RF Parameters
Rext value
2.2
315 & 434MHz bands,
with 50Ω matching network
-
5
-
dBm
2.3
868MHz band,
with 50Ω matching network
-
1
-
dBm
2.4
315 & 434MHz bands,
-40°C≤TA≤125°C
-3
0
3
dBm
2.8
868MHz band,
-40°C≤TA≤125°C
-7
-3
0
dBm
315 & 434MHz bands,
with 50Ω matching network
-
-0.35
-0.25
-
dB/kΩ
mA/
kΩ
315 & 434MHz bands,
with 50Ω matching network
-
-34
-
dBc
868MHz band,
with 50Ω matching network
-
-49
-
dBc
2.15
315 & 434MHz bands
-
-23
-17
dBc
2.16
868MHz band
-
-38
-27
dBc
2.17
315 & 434MHz bands,
with 50Ω matching network
-
-32
-
dBc
868MHz band,
with 50Ω matching network
-
-57
-
dBc
2.19
315 & 434MHz bands
-
-21
-15
dBc
2.20
868MHz band
-
-48
-39
dBc
315 & 434MHz bands
-
-36
-24
dBc
868MHz band
-
-29
-17
dBc
315 MHz band
-
-37
-30
dBc
434MHz band
-
-44
-34
dBc
868MHz band
-
-37
-27
dBc
315MHz band
-
-62
-53
dBc
434MHz band
-
-80
-60
dBc
868MHz band
-
-45
-39
dBc
Output Power
2.12
Current & Output Power
Variation vs. Rext value
2.13
2.14
2.18
2.21
2.22
2.23
2.24
2.25
2.41
2.26
2.27
8
Harmonic 2 Level
Harmonic 3 Level
Spurious Level
@ fcarrier ±f DATACLK
Spurious Level
@ fcarrier ±f reference
Spurious Level
@ fcarrier/2
MC33493 Technical Data
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ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40°C;+125°C],
Rext=12kΩ+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output
load RL=50Ω+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics:
figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25°C.
Limits
Parameter
Test Conditions, Comments
2.30
Phase Noise
Freescale Semiconductor, Inc...
2.31
2.32
PLL Lock-in Time,
tPLL_lock_in
2.33
XTAL1 Input Capacitance
2.34
2.35
OOK Modulation Depth
2.36
FSK Modulation
Carrier Frequency
Total Deviation
2.37
2.38
2.39
CFSK Output Capacitance
2.40
Data Rate
2.41
Max.
315 & 434MHz bands,
±175kHz from f carrier
-
-75
-68
dBc/
Hz
868MHz band,
±175kHz from f carrier
-
-73
-66
dBc/
Hz
fcarrier within 30kHz from the final value,
crystal series resistor=150Ω
-
400
1600
µs
-
1
-
pF
-
20
200
20
50
75
90
-
dBc
315 & 434MHz bands, see note 1
-
-
100
kHz
868MHz band, see note 1
-
-
200
kHz
MODE=0, DATA=x
MODE=1, DATA=0
50
70
-
kΩ
MODE=1, DATA=1
-
90
300
Ω
-
1
-
pF
Manchester coding
-
-
10
kBit/s
MODE=0, see note 2
3.5
5.25
7.5
µs
MODE=1, see note 2
-200
-
200
ns
FSK modulation
CFSK Output Resistance
2.43
Typ.
OOK modulation
Crystal Resistance
2.44
Unit
Min.
Data to RF delay difference
between falling and rising edges,
2.42
tdelay_difference
Ω
Note 1: This parameter is depending on crystal characteristics, load capacitor values (see Table 6) and PCB
track capacitance.
Note 2: Delay difference definition
Input data
From 50% of data edge to corresponding
demodulated signal envelope edge:
tdelay_difference=tdelay_fall-tdelay_rise
Demodulated data
tdelay_rise
MOTOROLA
tdelay_fall
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RF OUTPUT SPECTRUM
Freescale Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, voltage range Vcc=[Vshutdown;3.6V], temperature range TA=[-40°C;+125°C],
Rext=12kΩ+/-5%, RF output frequency fcarrier=433.92MHz, reference frequency freference=13.560MHz, output
load RL=50Ω+/-1% (figure 9). Values refer to the circuit shown in the recommended application schematics:
figure 12 (14) for OOK (FSK) modulation. Typical values reflect average measurement at VCC=3V, TA=25°C.
Limits
Parameter
Test Conditions, Comments
Freescale Semiconductor, Inc...
3
Unit
Min.
Typ.
Max.
0
-
0.3 x
VCC
V
0.7 x
VCC
-
VCC
V
-
-
120
mV
-
-
100
nA
Microcontroller Interfaces
3.1
Input Low Voltage
3.2
Input High Voltage
3.3
Input Hysteresis Voltage
3.4
Input Current
3.5
ENABLE Pull Down Resistor
-
180
-
kΩ
3.6
DATACLK Output Low Voltage
0
-
0.25 x
VCC
V
0.75 x
VCC
-
VCC
V
Cload = 2pF, measured from 20% to
80% of the voltage swing
-
250
500
ns
-
150
400
ns
45% < Duty Cycle fDATACLK < 55%
-
800
2000
µs
Pins BAND, MODE, ENABLE, DATA
Pins BAND, MODE, DATA = 1
Cload = 2pF
3.7
DATACLK Output High Voltage
3.8
DATACLK Rising Time
3.9
DATACLK Falling Time
3.10
DATACLK Settling Time,
tDATACLK_settling
RF OUTPUT SPECTRUM
Following are spectrums of transmitter carrier, measured in conduction mode. Three different spans have been
used. The 5MHz span spectrum (figure ) shows phase noise response close to the RF carrier, and the noise
suppression within the PLL loop bandwidth. The 50MHz span spectrum (figure 6) shows both phase noise and
reference spurious. Finally figure 7 shows second and third harmonics of carrier. All these spectrums are
measured in OOK modulation, at DATA=1.
Figure 8 shows spectrum in case of FSK modulation, with 45kHz deviation, at 4kbit/s data rate.
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RF OUTPUT SPECTRUM
Figure 5: RF spectrum at 434MHz frequency band displayed with a 5MHz span
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Resolution
bandwidth:
100kHz
Resolution
bandwidth:
30kHz
Figure 6: RF spectrum at 434MHz frequency band displayed with a 50MHz span
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RF OUTPUT SPECTRUM
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Figure 7: RF spectrum at 434MHz frequency band displayed with a 1.5GHz span
Figure 8: RF spectrum at 434MHz band for a 70kHz FSK deviation at 4.8kbit/s
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OUTPUT POWER MEASUREMENT
OUTPUT POWER MEASUREMENT
The RF output levels given in the electrical characteristics section are measured with a 50Ω load directly
connected to the pin RFOUT as shown below in figure 9. This wideband coupling method gives results
independent of the application.
Figure 9: Output power measurement configurations
VCC
Impeder: TDK MMZ1608Y102CTA00
RFOUT
RF output
100pF
Freescale Semiconductor, Inc...
RL=50 Ω
The configuration shown in figure 10-a provides a better efficiency in terms of output power and harmonics
rejection. Schematic on figure 10-b gives the equivalent circuit of the pin RFOUT and the DC bias impeder as
well as the matching network components for 434MHz frequency band.
Figure 10: Output model and matching network for 434MHz band
VCC
Impeder: TDK MMZ1608Y102CTA00
RFOUT
(a)
Matching
Network
RF output
RL=50 Ω
Matching
Network
L1
39nH
(b)
C0
R0
1.5pF 250Ω
RFOUT pin
3kΩ
C3
330pF
Ri
Impeder
50Ω
RL
Load
Figure 11 gives the output power versus the Rext resistor value with 50Ω load and with matching network.
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COMPLETE APPLICATION SCHEMATIC AND PCB FOR OOK MODULATION
Figure 11: Output power at 434MHz band vs Rext value
Output power measurement in typical conditions (434MHz - Vcc=3V - 25°C)
REXT SPECIFIED RANGE
8
6
Output power when matched (dBm)
-0.35dB/kΩ
Ω # -0.35mA/kΩ
Ω
4
2
RFOUT
Level (dBm)
-2
Output power on 50Ω
Ω load (dBm)
-4
-6
6
9
12
15
Rext (kΩ
Ω)
18
21
24
The 50Ω matching network used for the 868MHz band is similar to the 434MHz, except components values: in
figure 10b, L1 is changed to 8.2nH and C3 to 470pF. The typical gain of this 868MHz matching network is 4dB
compared to unmatched configuration.
COMPLETE APPLICATION SCHEMATIC AND PCB FOR OOK MODULATION
Figure 12 gives a complete application schematic using a Motorola MC68HC908RK2 microcontroller. OOK
modulation is selected, fcarrier= 433.92MHz. C2 to C5 capacitors can be removed if switches debounce is done by
software.
Figure 12: Application schematic for OOK modulation, 434MHz frequency band
Vbat
SW1
SW1a
SW2a
SW2
Vbat
LED1
1
B1
C2
C3
C4
C5
2.2nF
2.2nF
2.2nF
2.2nF
R1
2
Freescale Semiconductor, Inc...
0
750
Vbat
U1
1
2
3
U2
1
2
3
4
5
6
7
8
9
10
PTA0
PTA1/KBD1
PTB0/MCLK
PTA2/KBD2
PTB1
PTA3/KBD3
PTB2/TCH0
PTA4/KBD4
PTB4/TCH1
PTA5/KBD5
PTB5
PTA6/KBD6
PTB3/TCLK
PTA7
OSC1
RST
OSC2
IRQ1
VSS
VDD
MC68HC908RK2
4
C6 8.2pF
20
5
19
Y1
6
13.56MHz
18
7
17
R2
16
DATACLK
DATA
BAND
MODE
ENABLE
VCC
GND
GNDRF
XTAL1
RFOUT
XTAL0
VCC
REXT
CFSK
MC33493
12K
14
C7
22nF
13
12
11
10
C9
2.2pF
9
8
C8
100pF
15
14
13
12
11
Vbat
C10
100nF
Note that for 868MHz band application, the input pin BAND must be wired to ground. See component description
14
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COMPLETE APPLICATION SCHEMATIC AND PCB FOR FSK MODULATION
on following tables 3 and 4.
Component
Y1
R2
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C6
C7
C8
Table 3: External components description for OOK
Function
Value
315MHz band: 9.84
Crystal,
434MHz band: 13.56
see table 4
868MHz band: 13.56
RF output level setting
12
resistor (Rext)
Crystal load capacitor
Power supply decoupling
capacitors
8.2, see note 3
22
100
Unit
MHz
MHz
MHz
kΩ
pF
nF
pF
Note 3: C6 value equals recommended crystal load capacitance reduced by the PCB stray capacitances.
Examples of crystal reference are given below (see characteristics on table 4) for different application bands:
- at 315MHz band (freference= 9.84375MHz, -40°C < TA < 85°C): NDK LN-G102-950,
- at 434/868MHz bands (freference= 13.56MHz, -40°C < TA < 125°C):
NDK NX8045GB/CSJ S1-40125-8050-12 and NDK NX1255GA.
Parameter
Load capacitance
Motional capacitance
Static capacitance
Loss resistance
Table 4: Typical crystal characteristics (SMD package)
NDK NX8045GB/CSJ
NDK LN-G102-950
NDK NX1255GA
S1-40125-8050-12
(for 315MHz)
(for 434MHz & 868MHz)
(for 434MHz & 868MHz)
12
12
12
3.33
4.4
10.5
1.05
1.5
2.46
28
18.5
10
Unit
pF
fF
pF
Ω
Figure 13 shows a two buttons keyfob board. Size is 30 x 45 millimeters.
Figure 13: Two buttons keyfob board layout
COMPLETE APPLICATION SCHEMATIC AND PCB FOR FSK MODULATION
Figure 14 gives a complete application schematic using a Motorola MC68HC908RK2 microcontroller. FSK
modulation is selected, fcarrier= 433.92MHz. C1 capacitor can be removed if switch debounce is done by
software.
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COMPLETE APPLICATION SCHEMATIC AND PCB FOR FSK MODULATION
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Figure 14: .Application schematic for FSK modulation, serial configuration, 434MHz frequency band
Note that for 868MHz band application, the input pin BAND must be wired to ground. See component description
on table 5.
Component
Y1
R1
C3
C4
C2
C6
Table 5: External components description for FSK
Function
Value
315MHz band: 9.84,
see table 4
434MHz band: 13.56,
Crystal
see table 4
868MHz band: 13.56,
see table 4
RF output level setting
12
resistor (Rext)
Crystal load capacitor
See table 6
Power supply decoupling
capacitor
22
100
Unit
MHz
MHz
MHz
kΩ
pF
pF
nF
pF
Figure 15 gives the corresponding PCB layout.
16
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RECOMMENDATIONS FOR FSK MODULATION
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Figure 15: Application PCB layout for FSK modulation, serial configuration, 434MHz frequency band
Table 6 gives the measured FSK deviations respective to C3 and C4 capacitor values for three deviations.
Crystal reference is NDK NX8045GB/CSJ S1-40125-8050-12.
Table 6 : Crystal pulling capacitor values versus carrier frequency total deviation -1Carrier frequency
Carrier frequency
C3 capacitor
C4 capacitor
Recommended
(MHz)
total deviation (kHz)
(pF)
(pF)
R_off value (kΩ)
45
4.7
6.8
10
434
70
2.2
10
100
1
15
22
90
4.7
6.8
10
868
140
2.2
10
200
1
15
22
Another crystal reference, NDK NX1255GA (see table 4), enables to reach higher deviation as mentioned on
table 7. These results are due to the higher crystal motional capacitor.
Table 7 : Crystal pulling capacitor values versus carrier frequency total deviation -2Carrier frequency
Carrier frequency
C3 capacitor
C4 capacitor
Recommended
(MHz)
total deviation (kHz)
value (pF)
value (pF)
R_off value (kΩ)
434
150
1
27
868
300
1
27
-
RECOMMENDATIONS FOR FSK MODULATION
FSK deviation is function of total load capacitance presented to the crystal. This load capacitance is constituted
by various contributors:
- the crystal characteristic, especially its static capacitance,
- the external load capacitors (C3, C4 as defined in figure 14 and table 6),
- the device internal capacitance of pins XTAL0, XTAL1, CFSK,
- the PCB track capacitance.
The schematic given in figure 16 shows a typical FSK application using serial capacitor configuration, where
device pads and PCB track capacitances are mentioned.
Device pad capacitance is defined by the package capacitance and by the internal circuitry. Typical capacitance
values for these pads are given in table 8.
Some realistic assumptions and measurements have been made concerning track parasitic capacitances for a
0.8mm FR4 double side application PCB. They are given in table 8 and the corresponding PCB layout is shown
in figure 15.
To achieve large deviations, this total load capacitance need to be lowered. For a given crystal, the PCB must be
very carefully laid out in order to reduce as much as possible the capacitance of the tracks wired to XTAL0,
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RECOMMENDATIONS FOR FSK MODULATION
XTAL1, CFSK pins.
Recommendation: a R_off resistor can be added in parallel with the FSK switch to optimize the transient
response of demodulated signal. Table 6 gives the optimized R_off values for two deviations. Note that there is
no footprint for R_off resistor on the layout figure 15. When used, this component can be soldered on top of C3.
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Figure 16: Schematic detailing the crystal load capacitance contributors
Table 8: Pads and tracks parasitic values
Capacitance
Value
Unit
C_pad_XTAL0
1
pF
C_pad_XTAL1
1
pF
C_pad_CFSK
1
pF
C_track_XTAL0
1.5
pF
C_track_XTAL1
1.5
pF
C_track_CFSK
1.5
pF
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CASE OUTLINE DIMENSIONS
CASE OUTLINE DIMENSIONS
14X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.10 (0.004)M T U S V S
0.15 (0.006)T U S
N
2X
L/2
14
0.25 (0.010)
8
M
B
-U-
L
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PIN 1
IDENT.
N
F
7
1
0.15 (0.006)T U S
DETAIL E
K
A
-V-
K1
J J1
SECTION N-N
-W-
C
0.10 (0.004)
-T- SEATING
D
PLANE
G
H
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
DETAIL E
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0°
8°
INCHES
MIN MAX
0.193 0.200
0.169 0.177
--- 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0°
8°
CASE 948G-01
ISSUE O
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81-3-3440-3569
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