MOTOROLA MC74HC153D

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC153 is identical in pinout to the LS153. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The Address Inputs select one of four Data Inputs from each multiplexer.
Each multiplexer has an active–low Strobe control and a noninverting
output.
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
1
The HC153 is similar in function to the HC253, which has 3–state outputs.
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 108 FETs or 27 Equivalent Gates
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
STROBE a
1
16
VCC
A1
2
15
STROBE b
D3a
3
14
A0
D2a
4
13
D3b
D1a
5
12
D2b
D0a
6
11
D1b
Ya
7
10
D0b
GND
8
9
Yb
A0 14
A1 2
DATA–
WORD a
INPUTS
D0a 6
D1a 5
D2a 4
D3a 3
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
ADDRESS
INPUTS
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
7 Y
a
FUNCTION TABLE
STROBE a 1
DATA–
WORD b
INPUTS
Inputs
D0b 10
D1b 11
D2b 12
D3b 13
9 Y
b
A0
Strobe
Y
X
L
L
H
H
X
L
H
L
H
H
L
L
L
L
L
D0
D1
D2
D3
D0, D1, D2, and D3 = the level of the
respective data input.
STROBE b 15
PIN 16 = VCC
PIN 8 = GND
10/95
 Motorola, Inc. 1995
Output
A1
1
REV 6
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MC74HC153
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
6.0
± 0.1
± 1.0
± 1.0
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
Maximum Input Leakage Current
4.0 mA
5.2 mA
Vin = VCC or GND
4.0 mA
5.2 mA
V
µA
Vin = VCC or GND
6.0
8
80
160
µA
Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ICC
MOTOROLA
Maximum Quiescent Supply
Current (per Package)
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC153
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y
(Figures 1, and 4)
2.0
4.5
6.0
140
28
24
175
35
30
210
42
36
ns
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 2 and 4)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH,
tPHL
Maximum Propagation Delay, Strobe to Output Y
(Figures 3, and 4)
2.0
4.5
6.0
95
19
16
120
24
20
145
29
25
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
Unit
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Multiplexer)*
pF
31
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
tr
tf
VALID
90%
50%
10%
INPUT D
VCC
50%
INPUT A
GND
tPLH
GND
tPLH
tPHL
90%
50%
10%
OUTPUT Y
OUTPUT Y
tPHL
50%
tTHL
tTLH
Figure 1.
Figure 2.
tf
STROBE
tr
90%
50%
10%
TEST POINT
VCC
OUTPUT
DEVICE
UNDER
TEST
GND
tPLH
90%
50%
10%
OUTPUT Y
VALID
VCC
tPHL
tTLH
CL*
tTHL
* Includes all probe and jig capacitance
Figure 3.
High–Speed CMOS Logic Data
DL129 — Rev 6
Figure 4. Test Circuit
3
MOTOROLA
MC74HC153
PIN DESCRIPTIONS
DATA INPUTS
Strobe (Pins 1, 15)
D0a – D3a, D0b – D3b (Pins 3, 4, 5, 6, 10, 11, 12, 13)
Active–low Strobe. A low level applied to these pins enables the corresponding outputs.
Data Inputs. With the outputs enabled, the addressed Data
Inputs appear at the Y outputs.
OUTPUTS
CONTROL INPUTS
Ya, Yb (Pins 7, 9)
A0, A1 (Pins 2, 14)
Noninverting data outputs.
Address Inputs. These inputs address the pair of Data
Inputs which appear at the corresponding outputs.
EXPANDED LOGIC DIAGRAM
D0a 6
STROBE a
DATA
WORD a
INPUTS
D1a
5
D2a
4
1
7 Y
a
D3a 3
NONINVERTING
DATA
OUTPUTS
D0b 10
DATA
WORD b
INPUTS
D1b 11
D3b 13
ADDRESS
INPUTS
MOTOROLA
9
D2b 12
Yb
STROBE b 15
A1 2
A0 14
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC153
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
M
T
B
S
A
S
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
5
*MC74HC153/D*
MC74HC153/D
MOTOROLA