SN54/74LS273 OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing. • • • • OCTAL D FLIP-FLOP WITH CLEAR 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) 4 J SUFFIX CERAMIC CASE 732-03 20 1 PIN NAMES N SUFFIX PLASTIC CASE 738-03 20 LOADING (Note a) 1 CP D0 – D7 MR Q0 – Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs (Note b) HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 20 1 NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. ORDERING INFORMATION TRUTH TABLE MR CP Dx Qx L H H X X H L L H L DW SUFFIX SOIC CASE 751D-03 SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM FAST AND LS TTL DATA 5-447 SN54/74LS273 FUNCTIONAL DESCRIPTION The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA – 20 VCC = VCC MIN, VIN = VIL or VIH per Truth Table 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 27 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ 30 40 fMAX Maximum Input Clock Frequency tPHL Propagation Delay, MR to Q Output 18 tPLH tPHL Propagation Delay, Clock to Output 17 18 Unit Test Conditions MHz Figure 1 27 ns Figure 2 27 27 ns Figure 1 Max FAST AND LS TTL DATA 5-448 SN54/74LS273 AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Unit Test Conditions tw Symbol Pulse Width, Clock or Clear Parameter 20 ns Figure 1 ts Data Setup Time 20 ns Figure 1 th Hold Time 5.0 ns Figure 1 trec Recovery Time 25 ns Figure 2 Min Typ Max AC WAVEFORMS *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. FAST AND LS TTL DATA 5-449 Case 751D-03 DW Suffix 20-Pin Plastic SO-20 (WIDE) "! ! " -A11 1 10 ! " # P C -T- " #! D J F K ! #! * * !" $ !" M * R X 45° " " %# G ! " ! -B- ! " 20 & ! ! ° ° ° ° ) ) ) ! Case 732-03 J Suffix 20-Pin Ceramic Dual In-Line "! ! $" '' " # !" " !" " %# 20 " 11 1 10 B L C F N H G D J M K Case 738-03 N Suffix 20-Pin Plastic ! ! ° ° ° ° ! " " ! ( " " B ! ! $ ! ( ! " # ! C -T- L K G ! & 11 E ! 10 1 #! !#! "! -A20 ! $ A " " " N M F J D " " FAST AND LS TTL DATA 5-450 * !" $ !" * ! ! ! ! ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. tPZL Closed Open ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-451