SN54/74LS375 4-BIT D LATCH The SN54/ 74LS375 is a 4-Bit D-Type Latch for use as temporary storage for binary information between processing limits and input /output or indicator units. When the Enable (E) is HIGH, information present at the D input will be transferred to the Q output and, if E is HIGH, the Q output will follow the input. When E goes LOW, the information present at the D input prior to its setup time will be retained at the Q outputs. 4-BIT D LATCH LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. J SUFFIX CERAMIC CASE 620-09 16 1 N SUFFIX PLASTIC CASE 648-08 16 TRUTH TABLE (Each latch) tn tn+1 D H L Q H L 1 NOTES: tn = bit time before enable negative-going transition. tn+1 = bit time after enable negative-going transition. PIN NAMES 16 1 LOADING (Note a) Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) ORDERING INFORMATION LOW HIGH D1 – D4 E0 – 1 E2 – 3 Q1 – Q4 Q1 – Q4 D SUFFIX SOIC CASE 751B-03 0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L. SN54LSXXXJ SN74LSXXXN SN74LSXXXD 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. LOGIC DIAGRAM LOGIC SYMBOL Ceramic Plastic SOIC FAST AND LS TTL DATA 5-528 SN54/74LS375 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Typ Max Unit 2.0 54 0.7 74 0.8 – 0.65 – 1.5 Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA D Input E Input 20 80 µA VCC = MAX, VIN = 2.7 V D Input E Input 0.1 0.4 mA VCC = MAX, VIN = 7.0 V D Input E Input – 0.4 – 1.6 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 12 mA VCC = MAX Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Typ Max Unit Propagation Delay, Data to Q 15 9.0 27 17 ns Propagation Delay, Data to Q 12 7.0 20 15 ns tPLH tPHL Propagation Delay, Enable to Q 15 14 27 25 ns tPLH tPHL Propagation Delay, Enable to Q 16 7.0 30 15 ns tPLH tPHL tPLH tPHL Parameter Min FAST AND LS TTL DATA 5-529 Test Conditions VCC = 5.0 V CL = 15 pF SN54/74LS375 LOGIC DIAGRAM GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Unit Max tW Enable Pulse Width 20 ns ts Setup Time 20 ns th Hold Time 0 ns Test Conditions VCC = 5.0 V AC WAVEFORMS DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. FAST AND LS TTL DATA 5-530 Case 751B-03 D Suffix 16-Pin Plastic SO-16 -A- "! ! " " ! " # 1 %# ) ! !" $ !" 8 C -T- D M K " ! #! J F ! Case 648-08 N Suffix 16-Pin Plastic R X 45° G " ! ) #! P ! " " 9 -B- ! 16 & ! ! ° ° ° ° ( ( ( ( "! ! " " ! ! ' " " ! ' ! " # & -A- 16 9 1 8 ! ! $ ! B # ) " ! " # ) !" $ !" ) F L C S -T- K H G M J D " Case 620-09 J Suffix 16-Pin Ceramic Dual In-Line -A- ! ! ! ! ° ° ° ° "! ! " 16 " ) " L K M N J G D " $ " $ ! " " ! ! FAST AND LS TTL DATA 5-531 & # ) !" $ !" ) -T $ " " C F & 8 E ! ! ! " " -B1 & 9 * * ! ! ! ! * * ! ° ° ! ° ° Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. ◊ FAST AND LS TTL DATA 5-532