19-2100; Rev 0; 8/01 Quad Bus LVDS Driver with Flow-Through Pinout The power-on reset ensures that all four outputs are disabled and high impedance during power up and power down. The outputs can be set to high impedance by two enable inputs, EN and EN, thus dropping the device to a low-power state of 11mW. The enables are common to all four drivers. The flow-through pinout simplifies PC board layout and reduces crosstalk by keeping the LVTTL/LVCMOS inputs and BLVDS outputs separated. The MAX9129 operates from a single +3.3V supply and is specified for operation from -40°C to +85°C. It is available in 16-pin QFN and TSSOP packages. Refer to the MAX9121 data sheet for a quad LVDS line receiver with flow-through pinout. Applications Features ♦ Drive LVDS Levels into a 27Ω Load ♦ 1ns (0% to 100%) Minimum Transition Time Reduces Reflections ♦ Guaranteed 200Mbps (100MHz) Data Rate ♦ Enable Pins for High-Impedance Output ♦ High-Impedance Outputs when Powered Off ♦ Glitch-Free Power-Up and Power-Down ♦ Hot Swappable ♦ Flow-Through Pinout ♦ Available in Tiny QFN Package (50% Smaller than TSSOP) ♦ Single +3.3V Supply Ordering Information TEMP. RANGE PIN-PACKAGE MAX9129EGE PART -40°C to +85°C 16 QFN MAX9129EUE -40°C to +85°C 16 TSSOP Cell Phone Base Stations Add/Drop Muxes Digital Cross-Connects Functional Diagram appears at end of data sheet. DSLAMs Pin Configurations appear at end of data sheet. Network Switches/Routers Backplane Interconnect Clock Distribution Typical Applications Circuit CARD 1A MAX9129 CARD 10A MAX9121 MAX9129 CARD 1B MAX9121 MAX9129 CARD 2B MAX9121 MAX9129 MAX9121 BUS A Rt Rt BUS B Rt MULTIPOINT FULL-DUPLEX TRANSMIT AND RECEIVE BUS Rt Rt = TERMINATION RESISTOR ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9129 General Description The MAX9129 is a quad bus low-voltage differential signaling (BLVDS) driver with flow-through pinout. This device is designed to drive a heavily loaded multipoint bus with controlled transition times (1ns 0% to 100% minimum) for reduced reflections. The MAX9129 accepts four LVTTL/LVCMOS input levels and translates them to output levels of 250mV to 450mV (standard LVDS levels) into a 27Ω load at speeds up to 200Mbps (100MHz). MAX9129 Quad Bus LVDS Driver with Flow-Through Pinout ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V IN_, EN, EN to GND....................................-0.3V to (VCC + 0.3V) OUT_+, OUT_- to GND..........................................-0.3V to +4.0V Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin QFN (derate 18.5mW/°C above +70°C) .........1481mW 16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW Storage Temperature Range .............................-65°C to +150°C Maximum Junction Temperature .....................................+150°C Operating Temperature Range ...........................-40°C to +85°C ESD Protection Human Body Model, OUT_+, OUT_- ...............................±8kV Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 27Ω ±1%, EN = high, EN = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 250 371 450 mV 1 25 mV 1.29 1.375 V 5 25 mV 1.465 1.6 V BLVDS OUTPUTS (OUT_+, OUT_-) Differential Output Voltage VOD Figure 1 ∆VOD Figure 1 VOS Figure 1 Change in Magnitude of VOS Between Complementary Output States ∆VOS Figure 1 Output High Voltage VOH Output Low Voltage VOL Differential Output Short-Circuit Current IOSD Change in Magnitude of VOD Between Complementary Output States Offset Voltage 1.125 0.90 1.085 V VOD = 0 20 mA -20 mA Output Short-Circuit Current IOS OUT_+ = 0 at IN_ = VCC or OUT_- = 0 at IN_ = 0 Output High-Impedance Current IOZ Disabled, OUT_+ = 0 or VCC, OUT_- = 0 or VCC -1 1 µA Power-Off Output Current IOFF VCC = 0 or open, EN = EN = IN_ = 0, OUT_+ = 0 or 3.6V, OUT_- = 0 or 3.6V -1 1 µA Output Capacitance COUT Capacitance from OUT_+ or OUT_- to GND 4.3 pF INPUTS (IN_, EN, EN) High-Level Input Voltage VIH 2.0 VCC V Low-Level Input Voltage VIL GND 0.8 V Input Current IIN -15 15 µA 70 5 mA mA IN_, EN, EN = 0 or VCC SUPPLY CURRENT Supply Current Disabled Supply Current 2 ICC ICCZ RL = 27Ω, IN_ = VCC or 0 for all channels Disabled 58 3.2 _______________________________________________________________________________________ Quad Bus LVDS Driver with Flow-Through Pinout (VCC = +3.0V to +3.6V, RL = 27Ω ±1%, CL = 15pF, EN = high, EN = low, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Notes 3, 4, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Propagation Delay High to Low tPHLD Figures 2 and 3 1.0 1.98 3.0 ns Differential Propagation Delay Low to High tPLHD Figures 2 and 3 1.0 1.92 3.0 ns Differential Pulse Skew (Note 6) tSKD1 Figures 2 and 3 300 ps Differential Channel-to-Channel Skew (Note 7) tSKD2 Figures 2 and 3 450 ps Differential Part-to-Part Skew (Note 8) tSKD3 Figures 2 and 3 1.2 ns Differential Part-to-Part Skew (Note 9) tSKD4 Figures 2 and 3 2.0 ns Rise Time tTLH Figures 2 and 3 Fall Time tTHL Figures 2 and 3 Disable Time High to Z tPHZ Figures 4 and 5 8 Disable Time Low to Z tPLZ Figures 4 and 5 8 ns Enable Time Z to High tPZH Figures 4 and 5 10 ns Enable Time Z to Low tPZL Figures 4 and 5 10 ns Maximum Operating Frequency (Note 10) fMAX Figure 2 MAX9129EGE 0.60 1.19 1.55 MAX9129EUE 0.60 1.09 1.40 MAX9129EGE 0.60 1.12 1.55 MAX9129EUE 0.60 1.02 1.40 100 ns ns ns MHz Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25°C. Note 2: Current into the device is defined as positive, and current out of the device is defined as negative. All voltages are referenced to ground except VOD and ∆VOD. Note 3: AC parameters are guaranteed by design and characterization. Note 4: CL includes probe and jig capacitance. Note 5: Signal generator conditions: VOL = 0, VOH = VCC, f = 100MHz, 50% duty cycle, RO = 50Ω, tR = tF = 1ns (10% to 90%). Note 6: tSKD1 is the magnitude difference of differential propagation delays. tSKD1 = | tPHLD - tPLHD |. Note 7: tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on the same device. Note 8: tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and within 5°C of each other. Note 9: tSKD4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and temperature ranges. Note 10: Signal generator conditions: VOL = 0, VOH = VCC, f = 100MHz, 50% duty cycle, RO = 50Ω, tR = tF = 1ns (10% to 90%). MAX9129 output criteria: duty cycle = 45% to 55%, VOD ≥ 250mV, all channels switching. _______________________________________________________________________________________ 3 MAX9129 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (MAX9129EUE (TSSOP package), VCC = +3.3V, RL = 27Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) (Note 5) OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE 1.46 1.45 1.10 1.08 1.06 3.0 3.3 -14.11 -14.10 -14.09 -14.08 3.0 3.6 MAX9129 toc03 -14.12 1.04 1.44 3.3 3.6 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT HIGH-IMPEDANCE CURRENT vs. SUPPLY VOLTAGE DIFFERENTIAL OUTPUT VOLTAGE vs. SUPPLY VOLTAGE DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE 424 422 420 371.5 371.0 370.5 3.3 3.6 1.500 1.250 1.000 0.750 0.500 0.250 0 370.0 3.0 3.3 10 3.6 30 50 70 90 110 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) LOAD RESISTANCE (Ω) OUTPUT OFFSET VOLTAGE vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. FREQUENCY SUPPLY CURRENT vs. SUPPLY VOLTAGE 63 SUPPLY CURRENT (mA) 1.295 1.290 1.285 1.280 1.275 57.7 57.5 SUPPLY CURRENT (mA) 1.300 61 59 57 130 150 MAX9129 toc09 65 MAX9129 toc07 1.305 MAX9129 toc08 3.0 MAX9129 toc06 1.750 DIFFERENTIAL OUTPUT VOLTAGE (V) 426 MAX9129 toc05 428 372.0 DIFFERENTIAL OUTPUT VOLTAGE (mV) VOUT_ = VCC OR 0 MAX9129 toc04 SUPPLY VOLTAGE (V) 430 OUTPUT HIGH-IMPEDANCE CURRENT (pA) MAX9129 toc02 MAX9129 toc01 1.47 1.12 OUTPUT LOW VOLTAGE (V) OUTPUT HIGH VOLTAGE (V) 1.48 OUTPUT SHORT CURRENT (IOS) vs. SUPPLY VOLTAGE OUTPUT SHORT CURRENT (mA) OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE OUTPUT OFFSET VOLTAGE (V) MAX9129 Quad Bus LVDS Driver with Flow-Through Pinout 57.3 57.1 56.9 1.270 55 1.265 3.0 3.3 SUPPLY VOLTAGE (V) 4 3.6 56.7 0 1 10 100 FREQUENCY (MHz) 1000 3.0 3.3 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.6 Quad Bus LVDS Driver with Flow-Through Pinout (MAX9129EUE (TSSOP package), VCC = +3.3V, RL = 27Ω, CL = 15pF, TA = +25°C, unless otherwise noted.) (Note 5) 56 55 MAX9129 toc11 2.00 1.95 1.90 tPLHD 1.85 -15 10 35 60 85 2.00 1.90 tPLHD 1.80 1.70 3.0 3.3 -40 3.6 -15 10 35 60 TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C) DIFFERENTIAL SKEW vs. SUPPLY VOLTAGE DIFFERENTIAL SKEW vs. TEMPERATURE TRANSITION TIME vs. SUPPLY VOLTAGE 50 40 30 20 60 40 0 3.6 tTLH 1.1 1.0 tTHL 0.8 0 3.3 1.2 85 0.9 20 10 20% TO 80% TRANSITION TIME (ns) 80 DIFFERENTIAL SKEW (ps) 60 1.3 MAX9129 toc14 100 MAX9129 toc13 70 -40 -15 SUPPLY VOLTAGE (V) 10 35 60 85 3.0 3.3 3.6 SUPPLY VOLTAGE (V) TEMPERATURE (°C) TRANSITION TIME vs. TEMPERATURE 1.250 20% TO 80% 1.200 tTLH 1.150 TRANSITION TIME (ns) 3.0 tPHLD 1.60 1.80 -40 2.10 MAX9129 toc15 57 tPHLD DIFFERENTIAL PROPAGATION DELAY (ns) 58 2.05 2.20 MAX9129 toc16 SUPPLY CURRENT (mA) 59 2.10 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9129 toc10 60 DIFFERENTIAL SKEW (ps) DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE DIFFERENTIAL PROPAGAION DELAY vs. SUPPLY VOLTAGE MAX9129 toc12 SUPPLY CURRENT vs. TEMPERATURE 1.100 1.050 1.000 tTHL 0.950 0.900 0.850 0.800 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX9129 Typical Operating Characteristics (continued) Quad Bus LVDS Driver with Flow-Through Pinout MAX9129 Pin Description PIN QFN TSSOP 15 1 1, 4, 5, 16 2 3 6 NAME FUNCTION EN LVTTL/LVCMOS Enable Input. The driver is disabled when EN is low. EN is internally pulled down. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and are high impedance. 2, 3, 6, 7 IN_ LVTTL/LVCMOS Driver Inputs 4 VCC Power-Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF ceramic capacitors. 5 GND 8 Ground LVTTL/LVCMOS Enable Input. The driver is disabled when EN is high. EN is internally pulled down. EN 7, 10, 11, 14 9, 12, 13, 16 OUT_- Inverting BLVDS Driver Outputs 8, 9, 12, 13 10, 11, 14, 15 OUT_+ Noninverting BLVDS Driver Outputs CL OUT_+ OUT_ + RL/2 S IN_ VOS GND VOD IN_ GENERATOR VO VCC RL/2 RL OUT_ - 50Ω CL OUT_- Figure 1. Driver VOD and VOS Test Circuit Figure 2. Driver Propagation Delay and Transition Time Test Circuit VCC IN_ 50% 50% tPLHD tPHLD 0 OUT_ - VOH 0 DIFFERENTIAL 0 OUT_+ VOL 80% 0 VOD 80% VOD = (VOUT_+) - (VOUT_-) 0 20% 20% tTLH tTHL Figure 3. Driver Propagation Delay and Transition Time Waveforms 6 _______________________________________________________________________________________ Quad Bus LVDS Driver with Flow-Through Pinout ENABLES OUT_+ VCC IN_ RL/2 INPUTS EN EN H L or open IN_ GND +1.2V EN GENERATOR RL/2 EN MAX9129 Table 1. Input/Output Function Table CL 50Ω All other combinations of EN and EN OUTPUTS OUT_+ OUT_ - L L H H H L X Z Z OUT_1/4 MAX9129 CL Figure 4. Driver High-Impedance Delay Test Circuit EN WHEN EN = 0 OR OPEN VCC 50% 50% 0 VCC 50% 50% 0 EN WHEN EN = VCC tPZH tPHZ OUT_+ WHEN IN_ = VCC OUT_- WHEN IN_ = 0 VOH 50% 50% 1.2V 1.2V 50% OUT_+ WHEN IN_ = 0 OUT_- WHEN IN_ = VCC 50% VOL tPLZ tPZL Figure 5. Driver High-Impedance Delay Waveform Detailed Description The MAX9129 is a 200Mbps quad differential BLVDS driver designed for multipoint, heavily loaded backplane applications. This device accepts LVTTL/LVCMOS input levels and translates them to output levels of 250mV to 450mV into a 27Ω load. The flow-through pinout simplifies board layout and reduces the potential for crosstalk between single-ended inputs and differential outputs. Transition times are designed to reduce reflections, yet enable high data rates. The MAX9129 can be used in conjunction with standard quad LVDS receivers, such as the MAX9121, to implement full-duplex multipoint buses more efficiently than with transceivers. Effect of Capacitive Loading The characteristic impedance of a differential PC board trace is uniformly reduced when equal capacitive loads are attached at equal intervals (provided the transition time of the signal being driven on the trace is longer than the delay between loads). This kind of loading is typical of multipoint buses where cards are attached at 1in or 0.8in intervals along the length of a backplane. _______________________________________________________________________________________ 7 MAX9129 Quad Bus LVDS Driver with Flow-Through Pinout The reduction in characteristic impedance is approximated by the following formula: ZDIFF-loaded = ZDIFF-unloaded ✕ SQRT [Co / (Co + N ✕ CL / L)] where: ZDIFF-unloaded = unloaded differential characteristic impedance Co = unloaded trace capacitance (pF/unit length) CL = value of each capacitive load (pF) N = number of capacitive loads minimum transition time of 1ns (rated 0.6ns from 20% to 80%, or about 1ns 0% to 100%) to reduce reflections while being fast enough for high-speed backplane data transmission. Power-On Reset The power-on reset voltage of the MAX9129 is typically 2.25V. When the supply falls below this voltage, the device is disabled and the outputs are in high impedance. Applications Information Power-Supply Bypassing L = trace length For example, if Co = 2.5pF/in, CL = 10pF, N = 18, L = 18in, and ZDIFF-unloaded = 120Ω, the loaded differential impedance is: Bypass V CC with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC. ZDIFF-loaded = 120Ω ✕ SQRT [2.5pF / (2.5pF + 18 ✕ 10pF/18in)] In the example above, the loaded differential impedance of the bus is reduced to 54Ω. Since it can be driven from any card position, the bus must be terminated at each end. A parallel termination of 54Ω at each end of the bus placed across the traces that make up the differential pair provides a proper termination. The total load seen by the driver is 27Ω. ZDIFF-loaded = 54Ω In this example, capacitive loading reduces the characteristic impedance from 120Ω to 54Ω. The load seen by a driver located on a card in the middle of the bus is 27Ω because the driver sees two 54Ω loads in parallel. A typical LVDS driver (rated for a 100Ω load) would not develop a large enough differential signal to be reliably detected by an LVDS receiver. Maxim’s BLVDS driver is designed and specified to drive a 27Ω load to differential voltage levels of 250mV to 450mV (which are standard LVDS driver levels). A standard LVDS receiver is able to detect this level of differential signal. Short extensions off the bus, called stubs, contribute to capacitive loading. Keep stubs less than 1in for a good balance between ease of component placement and good signal integrity. The MAX9129 is a current source driver and drives larger differential signal levels into loads higher than 27Ω and smaller levels into loads less than 27Ω (see typical operating curves). To keep loading from reducing bus impedance below the rated 27Ω load, PC board traces can be designed for higher unloaded characteristic impedance. Effect of Transition Time For transition times (measured from 0% to 100%) shorter than the delay between capacitive loads, the loads are seen as low-impedance discontinuities from which the driven signal is reflected. Reflections add and subtract from the signal being driven and cause decreased noise margin and jitter. The MAX9129 is designed for a 8 Termination The MAX9129 drives higher differential signal levels into lighter loads. A multidrop bus with the driver at one end and receivers connected at regular intervals along the bus has a lowered impedance due to capacitive loading. Assuming the same impedance calculated in the multidrop example above (54Ω), the multidrop bus can be terminated with a single, parallel-connected 54Ω resistor at the far end from the driver. Only a single resistor is required because the driver sees one 54Ω differential trace. The signal swing is larger with a 54Ω load. In general, parallel terminate each end of the bus with a resistor matching the differential impedance of the bus (taking into account any reduced impedance due to loading). Board Layout A four-layer PC board that provides separate power, ground, input, and output signals is recommended. Keep the LVTTL/LVCMOS and BLVDS signals separated to prevent coupling as shown in the suggested layout for the QFN package (not drawn to scale) (Figure 6). _______________________________________________________________________________________ Quad Bus LVDS Driver with Flow-Through Pinout OUT1- IN1 OUT1+ MAX9129 EN GND IN2 OUT2+ VCC OUT2- GND OUT3- IN3 OUT3+ IN4 OUT4+ EN OUT4- Figure 6. Suggested Layout for QFN Package Chip Information TRANSISTOR COUNT: 948 PROCESS: CMOS _______________________________________________________________________________________ 9 Quad Bus LVDS Driver with Flow-Through Pinout MAX9129 Pin Configurations TOP VIEW 14 OUT2+ IN2 1 13 OUT2- VCC 2 GND 5 12 OUT3- IN3 6 11 OUT3+ IN4 7 10 OUT4+ EN 8 9 OUT4- TSSOP 16 GND 3 IN3 4 MAX9129 5 MAX9129 GND 6 VCC 4 13 IN2 3 GND IN4 EN OUT4- OUT4+ 12 OUT2+ 11 OUT2- 10 OUT3- 9 OUT3+ 8 15 OUT1+ EN OUT1- OUT1+ 14 IN1 2 GND 7 16 OUT1- 15 IN1 EN 1 GND GND QFN (4mm x 4mm) (CONTACTS UNDER QFN) Functional Diagram OUT1+ IN1 OUT1- OUT2+ IN2 OUT2- OUT3+ IN3 OUT3- OUT4+ IN4 OUT4- EN MAX9129 10 EN ______________________________________________________________________________________ Quad Bus LVDS Driver with Flow-Through Pinout TSSOP,NO PADS.EPS ______________________________________________________________________________________ 11 MAX9129 Package Information Quad Bus LVDS Driver with Flow-Through Pinout 12, 16,20, 24L QFN.EPS MAX9129 Package Information (continued) 12 ______________________________________________________________________________________ Quad Bus LVDS Driver with Flow-Through Pinout Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX9129 Package Information (continued)