19-4776; Rev 1; 11/98 KIT ATION EVALU LE B A IL A AV +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC ♦ Signal-to-Noise Ratio of 83dB ♦ Spurious-Free Dynamic Range of 91dB ♦ Differential Nonlinearity Error: ±0.3LSB ♦ Integral Nonlinearity Error: ±1.2LSB ♦ Single +5V Analog Supply, +3V Digital Supply ♦ Low Power Dissipation: 269mW ♦ On-Demand Self-Calibration ♦ Three-State, Two’s Complement Output Data Ordering Information PART TEMP. RANGE MAX1201CMH 0°C to +70°C 44 MQFP MAX1201EMH -40°C to +85°C 44 MQFP TEST0 34 35 RFPS RFPF CM 36 37 38 INP RFNS RFNF 39 40 41 INN N.C. N.C. 33 2 32 3 31 4 30 5 29 6 28 MAX1201 21 22 20 D1 DGND D5 D9 D8 19 23 18 24 11 D4 D3 D2 25 10 17 26 9 16 27 8 15 7 12 Spectrum Analysis 1 14 IR Imaging ST_CAL AGND AVDD AGND AGND AVDD DOR D13 D12 D11 D10 D7 D6 DRVDD Scanners 42 Instrumentation END_CAL TOP VIEW 43 Pin Configuration xDSL Medical Imaging PIN-PACKAGE 44 Applications ♦ Monolithic 14-Bit, 2.2Msps ADC 13 The MAX1201 is a 14-bit, monolithic, analog-to-digital converter (ADC) capable of conversion rates up to 2.2Msps. This integrated circuit, built on a CMOS process, uses a fully differential, pipelined architecture with digital error correction and a short self-calibration procedure that corrects for capacitor and gain mismatches and ensures 14-bit linearity at full sample rates. An on-chip track-and-hold (T/H) maintains superb dynamic performance up to the Nyquist frequency. The MAX1201 operates from a single +5V supply. The fully differential inputs allow an input swing of ±VREF. A single-ended input is also possible using two operational amplifiers. The reference is also differential with the positive reference (RFPF) typically connected to +4.096V and the negative reference (RFNF) tied to analog ground. Additional sensing pins (RFPS, RFNS) are provided to compensate for any resistive divider action that may occur due to finite internal and external resistances. The power dissipation is typically only 269mW at +5V and a sampling rate of 2.2Msps. The device employs a CMOS compatible, 14-bit parallel, two’s complement output data format. The MAX1201 is available in a 44-pin MQFP package and is specified over the commercial temperature (0°C to +70°C) and extended (-40°C to +85°C) temperature ranges. Features OE DAV CLK DVDD DGND DGND DVDD TEST1 TEST2 TEST3 D0 MQFP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX1201 General Description MAX1201 +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC ABSOLUTE MAXIMUM RATINGS AVDD to AGND, DGND ..........................................................+7V DVDD to DGND, AGND..........................................................+7V DRVDD to DGND, AGND .......................................................+7V INP, INN, RFPF, RFPS, RFNF, RFNS, CLK, CM..........(AGND - 0.3V) to (AVDD + 0.3V) Digital Inputs to DGND ............................-0.3V to (DVDD + 0.3V) Digital Output (DAV) to DGND ..............-0.3V to (DRVDD + 0.3V) Other Digital Outputs to DGND .............-0.3V to (DRVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 44-Pin MQFP (derate 11.11mW/°C above +70°C).......889mW Operating Temperature Ranges (TA) MAX1201CMH ....................................................0°C to +70°C MAX1201EMH .................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048, VIN = -0.5dBFS, fCLK = 4.5056MHz, digital output load ≤ 20pF, TA = TMIN to TMAX = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Input Voltage Range (Notes 2, 3) VIN Input Resistance (Note 4) RI Input Capacitance CI Reference Voltage (Note 3) CONDITIONS Single-ended Differential Per side in Track Mode 700 RES Integral Nonlinearity INL Differential Nonlinearity DNL After calibration, guaranteed Gain Error Maximum Sampling Rate 4.096 4.5 ±4.096 ±4.5 fSAMPLE = fCLK/2 Conversion Time (Pipeline Delay/Latency) V kΩ 21 pF 4.5 V Ω 1000 Bits LSB -1 ±0.3 +1 LSB -0.1 ±0.004 +0.1 %FSR -5 -1.7 +5 75 2.2528 %FSR µVRMS Msps 4 fSAMPLE Cycles 100 ns ns Acquisition Time tACQ Overvoltage Recovery Time tOVR 410 Aperture Delay tAD 3 ns Full-Power Bandwidth 3.3 MHz Small-Signal Bandwidth 78 MHz 2 To full-scale step (0.006%) UNITS 25 14 fCLK fSAMPLE MAX ±1.2 Offset Error Input-Referred Noise TYP 4.096 VREF Reference Input Resistance Resolution (no missing codes; Note 5) MIN _______________________________________________________________________________________ +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC (AVDD = +5V ±5%, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, VCM = +2.048, VIN = -0.5dBFS, fCLK = 4.5056MHz, digital output load ≤ 20pF, TA = TMIN to TMAX = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Signal-to-Noise Ratio (Note 5) Spurious-Free Dynamic Range (Note 5) Total Harmonic Distortion (Note 6) Signal-to-Noise Ratio + Distortion (Note 5) SYMBOL CONDITIONS fIN = 100.1kHz SNR THD 78 83 82 fIN = 1.0021MHz 81 84 89 fIN = 1.0021MHz 86 fIN = 100.1kHz -88 fIN = 502.7kHz -85 fIN = 1.0021MHz -83 77 MAX UNITS dB 91 fIN = 502.7kHz fIN = 100.1kHz SINAD TYP fIN = 502.7kHz fIN = 100.1kHz SFDR MIN dB -80 dB 82 fIN = 502.7kHz 79 fIN = 1.0021MHz 78 dB POWER REQUIREMENTS Analog Supply Voltage AVDD Analog Supply Current I(AVDD) Digital Supply Voltage DVDD Digital Supply Current I(DVDD) Output Drive Supply Voltage DRVDD Output Drive Supply Current I(DRVDD) Power Dissipation 4.75 5 5.25 V 53 75 mA 3 1 3 10pF loads on D0–D13 and DAV PDSS Warm-Up Time 5.25 V 2 mA DVDD V 0.3 1 mA 269 380 mW 0.1 Power-Supply Rejection Ratio PSRR Offset 55 Gain 55 sec dB TIMING CHARACTERISTICS (AVDD = +5V, DVDD = DRVDD = +3.3V, fCLK = 4.5056MHz, TA = TMIN to TMAX = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 4/fSAMPLE UNITS Conversion Time tCONV ns Clock Period tCLK Clock High Time tCH 85 113.5 137 ns Clock Low Time tCL 85 113.5 137 ns 150 ns 227 ns Output Delay tOD 70 DAV Pulse Width tDAV 1/fCLK tS 65 145 ns 16 75 ns 16 75 CLK-to-DAV Rising Edge Data Access Time tAC Bus Relinquish Time tREL Calibration Time tCAL CL = 20pF ST_CAL = DVDD 17,400 ns ns fCLK cycles _______________________________________________________________________________________ 3 MAX1201 ELECTRICAL CHARACTERISTICS (continued) MAX1201 +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC DIGITAL INPUT AND OUTPUT CHARACTERISTICS (AVDD = +5V, DVDD = DRVDD = +3.3V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Input Low Voltage VIL Input High Voltage VIH CONDITIONS MIN TYP CLKVIL CLK Input High Voltage CLKVIH CLK Input Current ICLK CLK Input Capacitance CCLK Digital Input Current IIN Output Low Voltage VOL Three-State Output Capacitance 0.8 V V 4.0 CLK Input Low Voltage Three-State Leakage Current UNITS DVDD - 0.8 Input Capacitance Output High Voltage MAX VOH pF 0.8 V ±10 µA AVDD - 0.8 VIN_ = 0 or DVDD V ±1 9 pF VIN_ = 0 ±0.1 ±10 VIN_ = DVDD ±0.1 ±10 70 400 ISINK = 1.6mA ISOURCE = 200µA DVDD - 0.4 DVDD - 0.03 ILEAKAGE ±0.1 COUT 3.5 µA mV V ±10 µA pF Note 1: Reference inputs driven by operational amplifiers for Kelvin-sensed operation. Note 2: For unipolar mode, the analog input voltage, VINP, must be within 0V and VREF, VINN = VREF /2; where VREF = VRFPS VRFNS. For differential mode, the analog input voltages VINP and VINN must be within 0V and VREF; where VREF = VRFPS VRFNS. The common-mode voltage of the inputs INP and INN is VREF /2. Note 3: Minimum and maximum parameters are not tested. Guaranteed by design. Note 4: Input resistance varies inversely with sample rate. Note 5: Calibration remains valid for temperature changes within ±20°C and power-supply variations ±5%. Note 6: All AC specifications are shown for the differential mode. 4 _______________________________________________________________________________________ +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC dBFS 80 70 SINAD (dB) dBc 60 50 40 30 -60 -50 -40 -30 -20 -10 MAX1201 toc03 AIN = -20dBFS -74 -76 AIN = -6dBFS -78 -80 -82 AIN = -6dBFS -84 AIN = -20dBFS -86 -88 AIN = -0.5dBFS -90 1k 0 -72 10k 100k 1k 1M 10k 100k 1M INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (Hz) INPUT FREQUENCY (Hz) SIGNAL-TO-NOISE-RATIO vs. INPUT FREQUENCY SIGNAL-TO-NOISE-RATIO PLUS DISTORTION vs. SAMPLE RATE (fIN = 100.1kHz) TYPICAL FFT, fIN = 100.1kHz, 2048 VALUE RECORD AIN = -0.5dBFS 0 88 -15 86 -30 82 AMPLITUDE (dBFS) SINAD (dB) 84 AIN = -6dBFS AIN = -0.5dBFS 80 78 76 AIN = -20dBFS 100k 1M -75 -90 -135 70 100k -60 -120 72 1M 3M 0 200k SAMPLE RATE (sps) INPUT FREQUENCY (Hz) -30 800k 1M 1.2M INTEGRAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE 2.0 MAX1201 toc07 0 600k FREQUENCY (Hz) TYPICAL FFT, fIN = 1.0021MHz, 2048 VALUE RECORD -15 400k MAX1201 toc08 10k -45 -105 74 1k MAX1201 toc06 90 MAX1201 toc04 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 1.5 1.0 -45 INL (LSB) AMPLITUDE (dBFS) SNR (dB) -70 -70 MAX1201 toc05 SFDR (dB) 90 AIN = -0.5dBFS THD (dB) 100 84 86 82 80 78 76 74 72 70 68 66 64 62 60 MAX1201 toc02 MAX1201 toc01 110 TOTAL HARMONIC DISTORTION vs. INPUT FREQUENCY SIGNAL-TO-NOISE PLUS DISTORTION vs. INPUT FREQUENCY SINGLE-TONE SPURIOUS-FREE DYNAMIC RANGE vs. INPUT AMPLITUDE (fIN = 100.1kHz) -60 -75 0.5 0 -90 -0.5 -105 -1.0 -120 -1.5 -135 0 200k 400k 600k 800k FREQUENCY (Hz) 1M 1.2M -2.0 -8192 -6144 -4096 -2048 0 2048 4096 6144 8192 TWO’S COMPLEMENT OUTPUT CODE _______________________________________________________________________________________ 5 MAX1201 __________________________________________Typical Operating Characteristics (AVDD = +5V, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, fCLK = 4.5056MHz, differential input, VCM = +2.048V, calibrated, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (AVDD = +5V, DVDD = DRVDD = +3.3V, VRFPS = +4.096V, VRFNS = AGND, fCLK = 4.5056MHz, differential input, VCM = +2.048V, calibrated, TA = +25°C, unless otherwise noted.) 14.0 MAX1201 toc9 1.0 AIN = -0.5dBFS 13.5 MAX1201 toc10 EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY DIFFERENTIAL NONLINEARITY vs. TWO’S COMPLEMENT OUTPUT CODE 13.0 ENOB (BITS) 0.5 DNL (LSB) MAX1201 +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC 0 12.5 12.0 AIN = -6dBFS 11.5 11.0 -0.5 AIN = -20dBFS 10.5 -1.0 -8192 -6144 -4096 -2048 0 10.0 2048 4096 6144 8192 1k 10k 100k 1M INPUT FREQUENCY (Hz) TWO’S COMPLEMENT OUTPUT CODE Pin Description 6 PIN NAME FUNCTION 1 ST_CAL 2, 4, 5 AGND Analog Ground 3, 6 AVDD Analog Power Supply, +5V ±5% 7 DOR Data Out-of-Range Bit 8 D13 Bit 13 (MSB) 9 D12 Bit 12 10 D11 Bit 11 11 D10 Bit 10 12 D9 Bit 9 13 D8 Bit 8 14 D7 Bit 7 15 D6 Bit 6 16 DRVDD Digital Power Supply for the Output Drivers. +3V to +5.25V, DRVDD ≤ DVDD. 17, 28 DGND Digital Ground 18 D5 Bit 5 19 D4 Bit 4 20 D3 Bit 3 Digital Input to Start Calibration. ST_CAL = 0: Normal conversion mode. ST_CAL = 1: Start self-calibration. _______________________________________________________________________________________ +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC PIN NAME FUNCTION 21 D2 Bit 2 22 D1 Bit 1 23 D0 Bit 0 (LSB) 24 TEST3 Test Pin 3. Leave unconnected. 25 TEST2 Test Pin 2. Leave unconnected. 26 TEST1 Test Pin 1. Leave unconnected. 27, 30 DVDD Digital Power Supply, +3V to +5.25V. 31 CLK Input Clock. Receives power from AVDD to reduce jitter. 32 DAV Data Valid Clock. Digital Output. This clock can be used to transfer the data to a memory or any other data-acquisition system. 33 OE 34 TEST0 35 CM 36 RFPF Positive Reference Voltage. Force Input. 37 RFPS Positive Reference Voltage. Sense Input. 38 RFNF Negative Reference Voltage. Force Input. 39 RFNS Negative Reference Voltage, Sense Input. Output Enable: Digital Input. OE = 0: D0–D13 and DOR are high impedance. OE = 1: All bits are active. Test Pin 0. Leave unconnected. Common-Mode Voltage. Analog Input. Drive midway between positive and negative reference voltages. 40 INP Positive Input Voltage 41, 42 N.C. Not Connected. No internal connection. 43 INN Negative Input Voltage 44 END_CAL Digital Output for End of Calibration. END_CAL = 0: Calibration in progress. END_CAL = 1: Normal conversion mode. _______________________________________________________________________________________ 7 MAX1201 Pin Description (continued) MAX1201 +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC Detailed Description Converter Operation The MAX1201 is a 14-bit, monolithic, analog-to-digital converter (ADC) capable of conversion rates up to 2.2Msps. It uses a multistage, fully differential, pipelined architecture with digital error correction and selfcalibration to provide 90dB (typ) spurious-free dynamic range at a 2.2Msps sampling rate. Its signal-to-noise ratio, harmonic distortion, and intermodulation products are also consistent with 14-bit accuracy up to the Nyquist frequency. This makes the device suitable for applications such as xDSL, digital radio, instrumentation, and imaging. Figure 1 shows the simplified, internal structure of the ADC. A switched-capacitor pipelined architecture is used to digitize the signal at a high throughput rate. The first four stages of the pipeline use a low resolution quantizer to approximate the input signal. The multiplying digital-to-analog converter (MDAC) stage is used to subtract the quantized analog signal from the input. The residue is then amplified with a fixed gain and passed on to the next stage. The accuracy of the converter is improved by a digital calibration algorithm which corrects for mismatches between the capacitors RFP_ RFN_ • Virtual elimination of the even-order harmonics • Less stringent requirements on the input signal processing amplifiers Requirements for Reference and Analog Signal Inputs Fully differential switched capacitor circuits (SC) are used for both the reference and analog inputs (Figure 2). This allows either single-ended or differential signals to be used in the reference and/or analog signal paths. The signal voltage on these pins (INP, INN, RFP_, RFN_) should neither exceed the analog supply rail, AVDD nor fall below ground. CM STAGE1 INP INN in the switched capacitor MDAC. Note that the pipeline introduces latency of four sampling periods between the input being sampled and the output appearing at D13–D0. While the device can handle both singleended or differential inputs (see Requirements for Reference and Analog Signal Inputs), the latter mode of operation will guarantee best THD and SFDR performance. The differential input provides the following advantages compared to a single-ended operation: • Twice as much signal input span • Common-mode noise immunity STAGE2 AVDD STAGE3 AGND STAGE4 8X S/H ADC ADC MDAC 7 CLK DVDD CLOCK GENERATOR DAV CORRECTION AND CALIBRATION LOGIC END_CAL ST_CAL DGND 17 MAX1201 OE OUTPUT DRIVERS DRVDD DOR D13–D0 Figure 1. Internal Block Diagram 8 _______________________________________________________________________________________ +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC MAX1201 CM RFPF RFPS RFPF INP RFNF INN RFNF RFPF CM Figure 2. Simplified MDAC Architecture RFNS Figure 3. Equivalent Input at the Reference Pins. The sense pins should not draw any DC current. Choice of Reference It is important to choose a low-noise reference, such as the MAX6341, which can provide both excellent load regulation and low temperature drift. The equivalent input circuit for the reference pins is shown in Figure 3. Note that the reference pins drive approximately 1kΩ of resistance on chip. They also drive a switched capacitor of 21pF. To meet the dynamic performance, the reference voltage is required to settle to 0.0015% within one clock cycle. Carefully choose an appropriate driving circuit (Figure 4). The capacitors at the reference pins (RFPF, RFNF) provide the dynamic charge required during each clock cycle, while the op amps ensure accuracy of the reference signals. These capacitors must have low dielectric-absorption characteristics, such as polystyrene or teflon capacitors. The reference pins can be connected to either singleended or differential voltages within the specified maximum levels. Typically, the positive reference pin (RFPF) would be driven to 4.096V, and the negative reference pin (RFNF) connected to analog ground. There are sense pins, RFPS and RFNS, which can be used with external amplifiers to compensate for any resistive drop on these lines, internal or external to the chip. Assure a correct reference voltage by using proper Kelvin connections at the sense pins. VRFP = 4.096V 5k CHIP BOUNDARY RFPF MAX410 RFPS 5k VRFN = 0V RFNF MAX410 RFNS CM MAX410 Common-Mode Voltage The switched capacitor circuit at the analog input allows signals between AGND and the analog power supply. Since the common-mode voltage has a strong influence on the performance of the ADC, the best results are obtained by choosing VCM to be at half the difference between the reference voltages VRFP and VRFN. Achieve Figure 4. Drive Circuit for Reference Pins and Common-Mode Pin this by using a resistive divider between the two reference potentials. Figure 4 shows the driving circuit for good dynamic performance. _______________________________________________________________________________________ 9 MAX1201 +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC Analog Signal Conditioning For single-ended inputs, the negative analog input pin (INN) is tied to the common-mode voltage pin (CM), and the positive analog input pin (INP) is connected to the input signal. The common-mode voltage of INP must be equal to the common-mode input. To take full advantage of the ADC’s superior AC performance up to Nyquist frequency, drive the chip with differential signals. While in communication systems the signals may inherently be available in differential mode, medical and/or other applications may only provide singleended inputs. In this case, convert the single-ended signals into differential ones by using the circuit recommended in Figure 5. Use low-noise, wideband amplifiers, such as the MAX4108, to maintain the signal purity over the full-power bandwidth of the MAX1201. Lowpass or bandpass filters may be required to improve the signal-to-noise-and-distortion ratio of the incoming signal. For low-frequency signals (<100kHz), active filters may be used. For higher frequencies, passive filters are more convenient. Single-Ended to Differential Conversion Using Transformers An alternative single-ended to differential-ended conversion method is a balun transformer such as the CTX03-13675 from Coiltronics. An important benefit of these transformers is their ability to level-shift a singleended signal, referred to ground on the primary side, to optimum common-mode voltages on the secondary side. At frequencies below 20kHz, the transformer core begins to saturate, causing odd-order harmonics. Clock Source Requirements Pipelined ADCs typically need a 50% duty cycle clock. To avoid this constraint, the MAX1201 provides a divide-by-two circuit which relaxes this requirement. The clock generator should be chosen commensurate with the frequency range, amplitude and slew rate of the signal source. If the slew rate of the input signal is low, the jitter requirement on the clock is relaxed. However, if the slew rate is high, the clock jitter needs to be kept at a minimum. For a full-scale amplitude input sine wave, the maximum possible SNR due completely to clock jitter is given by SNRMAX = V+ IN INP MAX4108 1 2 ⋅ π ⋅ fIN ⋅ σ JITTER For example, if fIN is 1MHz and σJITTER is 10ps RMS, then the SNR limit due to jitter is approximately 84dB. Generating such a clock source requires a low-noise comparator and a low-phase noise signal generator. The clock circuit shown in Figure 6 is a possible solution. CM VV+ V+ 0.1µF 0.1µF CLK_IN INN MAX4108 1k 5k CLK MAX961 V+ V0.1µF 1k CM Figure 5. A simple circuit generates differential signals from a single-ended input referred to analog ground. The commonmode voltage at INP and INN is the same as CM. 10 Figure 6. Clock Generation Circuit Using Low-Noise Comparator ______________________________________________________________________________________ +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC Once calibrated, the MAX1201 is insensitive to small changes (±5%) in power supply, voltage, or temperature. Following calibration, if the temperature changes more than ±20°C, the device should be recalibrated to maintain optimum performance. N N+1 AIN N+5 N+2 N+4 N+3 tCH tCL CLK SAMPLE CLOCK tS DAV D0–D13 tOD N-3 N-2 N-1 N N+1 MAX1201 Calibration Procedure Since the MAX1201 is based on a pipelined architecture, low-resolution quantizers (“coarse ADCs”) are used to approximate the input signal. MDACs of the same resolution are then used to reconstruct the input signal, which is subtracted from the input and the residue is amplified by the switched-capacitor gain stage. This residue is then passed on to the next stage. The accuracy of the MAX1201 is limited by the precision of the MDAC, which is strongly dependent on the matching of the capacitors used. The mismatch between the capacitors is determined and stored in an on-chip memory, which is later used during the conversion of the input signal. During the calibration procedure, the clock must be running continuously. ST_CAL (start of calibration) is initiated by a positive pulse with a minimum width of four clock cycles but no longer than about 17,400 clock cycles (Figure 8). The ST_CAL input may be asynchronous with the clock, since it is retimed internally. With ST_CAL activated, END_CAL goes low one or two clock cycles later and remains low until the calibration is complete. During this period, the reference voltages must be stable to less than 0.01%; otherwise, the calibration will be invalid. During calibration, the analog inputs INP and INN are not used; however, better performance is achieved if these inputs are static. Once END_CAL goes high (indicating that the calibration procedure is complete), the ADC is ready for conversion. CLK ST_CAL MIN 4 tCLK END_CAL ~17,400 CLK CYCLES Figure 8. Timing for Start and End of Calibration OE tAC D0–D13 DOR Z tREL Z Z = HIGH IMPEDANCE (THREE-STATED) Figure 9. Timing for Bus Access and Bus Relinquish— Controlled by Output Enable (OE) Two’s Complement Output The MAX1201 outputs data in two’s complement format. Table 1 shows how to convert the various fullscale inputs into their two’s complement output codes. Applications Information Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR(MAX) = (6.02 · N + 1.76)dB In reality, there are other noise sources besides quantization noise including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamental, the first nine harmonics, and the DC offset. Figure 7. Main Timing Diagram ______________________________________________________________________________________ 11 MAX1201 +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC Table 1. Binary Output Codes SCALE OFFSET BINARY ONE’S COMPLEMENT TWO’S COMPLEMENT +FSR - 1LSB 1111 .... 1111 0111 .... 1111 0111 .... 1111 +3/4FSR 1110 .... 0000 0110 .... 0000 0110 .... 0000 +1/2FSR 1100 .... 0000 0100 .... 0000 0100 .... 0000 +1/4FSR 1010 .... 0000 0010 .... 0000 0010 .... 0000 +0 1000 .... 0000 0000 .... 0000 0000 .... 0000 -0 —— .... —— 1111 .... 1111 —— .... —— -1/4FSR 0110 .... 0000 1101 .... 1111 1110 .... 0000 -1/2FSR 0100 .... 0000 1011 .... 1111 1100 .... 0000 -3/4FSR 0010 .... 0000 1001 .... 1111 1010 .... 0000 -FSR +1LSB 0000 .... 0001 1000 .... 0000 1000 .... 0001 -FSR 0000 .... 0000 —— .... —— 1000 .... 0000 Signal-to-Noise Plus Distortion (SINAD) Spurious-Free Dynamic Range (SFDR) SINAD is the ratio of the fundamental input frequency’s RMS amplitude to all other ADC output signals. SFDR is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SINAD (dB) = 20 · log [SignalRMS / (Noise + Distortion)RMS] Effective Number of Bits (ENOB) ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists only of quantization noise. With an input range equal to the full-scale range of the ADC, the effective number of bits can be calculated as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first nine harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 ⋅ log (V 2 2 ) + V3 + V4 + ⋅ ⋅ ⋅ + V9 2 2 V1 2 where V1 is the fundamental amplitude, and V2 through V9 are the amplitudes of the 2nd through 9th-order harmonics. 12 Grounding and Power-Supply Decoupling Grounding and power-supply decoupling strongly influence the performance of the MAX1201. At 14-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, and ground connections; this adversely affects the signal-to-noise ratio or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or be generated by the MAX1201. Therefore, grounding and power-supply decoupling guidelines should be closely followed. First, a multilayer, printed circuit board (PCB) with separate ground and power-supply planes is recommended. Run high-speed signal traces on lines directly above the ground plane. Since the MAX1201 has separate analog and digital ground buses (AGND and DGND, respectively), the PCB should also have separate analog and digital ground sections connected at only one point (star ground). Digital signals should run above the digital ground plane and analog signals should run above the analog ground plane. Digital signals should be kept far away from the sensitive analog inputs, reference input senses, common-mode input, and clock input. ______________________________________________________________________________________ +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC The analog power-supply input (AV DD ) for the MAX1201 is typically +5V, while the digital supplies can vary from +5V to +3V. Usually, DVDD and DRVDD pins are connected to the same power supply. Note that the DVDD supply voltage must be greater than or equal to the DRV DD voltage. For example, a digital +3.3V supply could be connected to DRVDD while a cleaner +5V supply is connected to DVDD resulting in slightly improved performance. Alternatively, the +3.3V supply could be connected to both DRVDD and DVDD. However, the +3.3V supply should not be connected to DVDD while the +5V supply is connected to DRVDD (Table 2). Table 2. Power-Supply-Voltage Combinations AVDD (V) DVDD (V) DRVDD (V) ALLOWED/ NOT ALLOWED 5 5 5 Allowed 5 5 3.3 Allowed 5 3.3 3.3 Allowed 5 3.3 5 Not Allowed Chip Information TRANSISTOR COUNT: 56,577 SUBSTRATE CONNECTED TO AGND ______________________________________________________________________________________ 13 MAX1201 The MAX1201 has three power-supply inputs: analog V DD (AV DD ), digital V DD (DV DD ), and drive V DD (DRVDD). Each AVDD input should be decoupled with parallel ceramic chip capacitors of values 0.1µF and 0.001µF, with these capacitors as close to the pin as possible and with the shortest possible connection to the ground plane. The DVDD pins should also have separate 0.1µF capacitors again adjacent to their respective pins, as should the DRVDD pin. Minimize the digital load capacitance. However, if the total load capacitance on each digital output exceeds 20pF, the DRVDD decoupling capacitor should be increased or, preferably, digital buffers should be added. The power-supply voltages should also be decoupled with large tantalum or electrolytic capacitors at the point the voltages enter the PCB. Ferrite beads with additional decoupling capacitors forming a pi network could also improve performance. +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC MQFP44.EPS MAX1201 Package Information 14 ______________________________________________________________________________________ +5V Single-Supply, 2.2Msps, 14-Bit Self-Calibrating ADC ______________________________________________________________________________________ MAX1201 NOTES 15 +5V Single-Supply, 2.2Msps, 14-Bit Self Calibrating ADC MAX1201 NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.