ETC A42L0616SERIES

A42L0616 Series
Preliminary
1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Document Title
1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Revision History
Rev. No.
0.0
PRELIMINARY
History
Issue Date
Remark
Initial issue
June 13, 2001
Preliminary
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42L0616 Series
Preliminary
1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
Features
n Organization: 1,048,576 words X 16 bits
n Part Identification
- A42L0616
(1K Ref.)
- A42L06161-L
(1K Ref. with self-refresh)
n Single 3.3V power supply/built-in VBB generator
n Low power consumption
- Operating: 130mA (-45 max)
- Standby: 1mA (TTL), 0.2mA (CMOS)
250µA (Self-refresh current)
n High speed
- 45/50/60 ns RAS access time
- 23/25/30 ns column address access time
- 13/15/17 ns CAS access time
- 16/20/25 ns EDO Page Mode Cycle Time
n Fast Page Mode with Extended Data Out
n Separate CAS ( UCAS , LCAS ) for byte selection
n Refresh Cycle
Part No.
Refresh cycle
A42L0616
1K
Refresh interval
Normal
L-ver
16ms
128ms
n Read-modify-write, RAS -only, CAS -before- RAS ,
Hidden refresh capability
n TTL-compatible, three-state I/O
n JEDEC standard packages
- 400mil, 42-pin SOJ
- 400mil, 50/44 TSOP type II package
General Description
The A42L0616 is a new generation randomly accessed
memory for graphics, organized in a 1,048,576-word by
16-bit configuration. This product can execute Byte Write
and Byte Read operation via two CAS pins.
The A42L0616 offers an accelerated Fast Page Mode
cycle with a feature called Extended Data Out (EDO).
This allow random access of up to 1024 words within a
row at a 63/50/40 MHz EDO cycle, making the A42L0616
ideally suited for graphics, digital signal processing and
high performance computing systems.
Pin Configuration
n SOJ
PRELIMINARY
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A9
A8
A7
A6
24
23
22
A5
A4
VSS
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
1
2
3
4
5
6
7
8
9
10
11
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
12
13
14
15
16
17
18
19
20
21
VCC
22
(June, 2001, Version 0.0)
Pin Descriptions
A42L0616V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
A42L0616S
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
n TSOP
44
43
42
41
40
39
38
37
36
35
34
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
33
32
31
30
29
28
27
NC
LCAS
UCAS
OE
A9
A8
A7
26
25
24
A6
A5
A4
23
VSS
Symbol
Description
A0 – A9
Address Inputs
I/O0 - I/O15
Data Input/Output
RAS
Row Address Strobe
LCAS
Column Address Strobe for Lower Byte
(I/O0 – I/O7)
UCAS
Column Address Strobe for Upper Byte
(I/O8 – I/O15)
1
WE
Write Enable
OE
Output Enable
VCC
3.3V Power Supply
VSS
Ground
NC
No Connection
AMIC Technology, Inc.
A42L0616 Series
Selection Guide
Symbol
-45
-50
-60
Unit
Maximum RAS Access Time
45
50
60
ns
Maximum Column Address Access Time
23
25
30
ns
tCAC
Maximum CAS Access Time
13
15
17
ns
tOEA
Maximum Output Enable ( OE ) Access Time
13
13
15
ns
tRC
Minimum Read or Write Cycle Time
79
84
104
ns
tPC
Minimum EDO Cycle Time
16
20
25
ns
tRAC
tAA
Description
Functional Description
The A42L0616 reads and writes data by multiplexing an
20-bit address into a 10-bit row and 10-bit column
address. RAS and CAS are used to strobe the row
address and the column address, respectively.
keeps the output drivers on during the CAS precharge
time (tcp). Since data can be output after CAS goes high,
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
The A42L0616 has two CAS inputs: LCAS controls I/O0I/O7, and UCAS controls I/O8 - I/O15, UCAS and LCAS
function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS ( UCAS or
LCAS ) to transition low and by the last to transition high.
Byte Read and Byte Write are controlled by using LCAS
A memory cycle is terminated by returning both RAS and
CAS high. Memory cell data will retain its correct state by
maintaining power and accessing all 1024(1K)
combinations of the 10-bit row addresses, regardless of
sequence, at least once every 16ms through any RAS
cycle (Read, Write) or RAS Refresh cycle (RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh
counter and controller.
and UCAS separately.
A Read cycle is performed by holding the WE signal high
during RAS/ CAS operation. A Write cycle is executed by
holding the WE signal low during RAS/ CAS operation;
the input data is latched by the falling edge of WE or
CAS , whichever occurs later. The data inputs and outputs
are routed through 16 common I/O pins, with RAS, CAS ,
WE and OE controlling the in direction.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization
cycles containing a RAS clock. During Power-On, the
VCC current is dependent on the input levels of RAS and
CAS . It is recommended that RAS and CAS track with
VCC or be held at a valid VIH during Power-On to avoid
current surges.
EDO Page Mode operation all 1024(1K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
CAS . While holding RAS low, CAS can be toggled to
strobe changing column addresses, thus achieving
shorter cycle times.
The A42L0616 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
PRELIMINARY
(June, 2001, Version 0.0)
2
AMIC Technology, Inc.
A42L0616 Series
Block Diagram
RAS
UCAS
LCAS
WE
Control
Clocks
Vcc
Vss
VBB Generator
Lower
Data in
Buffer
Row Decoder
Refresh Timer
Memory Array
1,048,576 x 16
Cells
Refresh Counter
A0~A9
A0~A9
OE
Upper
Data in
Buffer
I/O 8
to
I/O 15
Row Address Buffer
Col. Address Buffer
Recommended Operating Conditions
Symbol
Lower
Data out
Buffer
Sense Amps & I/O
Refresh control
I/O 0
to
I/O 7
Description
Upper
Data out
Buffer
Column Decoder
(Ta = 0°C to +70°C)
Min.
Typ.
Max.
Unit
Notes
VCC
Power Supply
3.0
3.3
3.6
V
1
VSS
Input High Voltage
0.0
0.0
0.0
V
1
VIH
Input High Voltage
2.0
-
VCC + 0.3
V
1
VIL
Input Low Voltage
-1.0
-
0.8
V
1
PRELIMINARY
(June, 2001, Version 0.0)
3
AMIC Technology, Inc.
A42L0616 Series
Truth Table
Function
RAS
UCAS
LCAS
WE
OE
Address
I/Os
Standby
H
X
X
X
X
X
High-Z
Read: Word
L
L
L
H
L
Row/Col.
Data Out
Read: Lower Byte
L
H
L
H
L
Row/Col.
I/O0-7 = Data Out
Notes
I/O8-15 = High-Z
Read: Upper Byte
L
L
H
H
L
Row/Col.
I/O0-7 = High-Z
I/O8-15 = Data Out
Write: Word
L
L
L
L
H
Row/Col.
Data In
Write: Lower Byte
L
H
L
L
H
Row/Col.
I/O0-7 = Data In
I/O8-15 = X
Write: Upper Byte
L
L
H
L
H
Row/Col.
I/O0-7 = X
I/O8-15 = Data In
L
L
L
H→L
L→H
Row/Col.
Data Out → Data In
1,2
-First cycle
L
H→L
H→L
H
H→L
Row/Col.
Data Out
2
-Subsequent Cycles
L
H→L
H→L
H
H→L
Col.
Data Out
2
-First cycle
L
H→L
H→L
L
H
Row/Col.
Data In
1
-Subsequent Cycles
L
H→L
H→L
L
H
Col.
Data In
1
-First cycle
L
H→L
H→L
H→L
L→H
Row/Col.
Data Out → Data In
1, 2
-Subsequent Cycles
L
H→L
H→L
H→L
L→H
Col.
Data Out → Data In
1, 2
Hidden Refresh Read
L→H→L
L
L
H
L
Row/Col.
Data Out
2
Hidden Refresh Write
L→H→L
L
L
L
X
Row/Col.
Data In → High-Z
1
L
H
H
X
X
Row
High-Z
CBR Refresh
H→L
L
L
X
X
X
High-Z
Self Refresh
H→L
L
L
H
X
X
High-Z
Read-Write
EDO-Page-Mode Read: Hi-Z
EDO-Page-Mode Write
EDO-Page-Mode Read-Write
RAS-Only Refresh
Note:
3
1. Byte Write may be executed with either UCAS or LCAS active.
2. Byte Read may be executed with either UCAS or LCAS active.
3. Only one CAS signal ( UCAS or LCAS ) must be active.
PRELIMINARY
(June, 2001, Version 0.0)
4
AMIC Technology, Inc.
A42L0616 Series
Absolute Maximum Ratings*
*Comments
Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
Output Voltage (Vout) . . . . . . . . . . . . . . . . . -0.5V to +4.6V
Power Supply Voltage (VCC) . . . . . . . . . . -0.5V to +4.6V
Operating Temperature (TOPR ) . . . . . . . . . 0°C to +70°C
Storage Temperature (TSTG) . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER ) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA
Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this devi ce.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (VCC = 3.3V ± 0.3%, VSS = 0V, Ta = 0°C to +70°C)
-45
Symbol
-50
-60
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Test Conditions
Notes
IIL
Input Leakage
Current
-5
+5
-5
+5
-5
+5
µA
0V ≤ Vin ≤ Vin+0.3V
Pins not under
Test = 0V
IOL
Output Leakage
Current
-5
+5
-5
+5
-5
+5
µA
DOUT disabled,
0V ≤ Vout ≤ VCC
ICC1
Operating Power
Supply Current
-
130
-
120
-
110
mA
RAS, UCAS , LCAS and
Address cycling;
tRC = min.
ICC2
TTL Supply Current
Supply Current
-
1
-
1
-
1
mA
RAS= UCAS = LCAS = WE
= VIH
ICC3
Average Power
Supply Current,
RAS Refresh Mode
-
130
-
120
-
110
mA
ICC4
EDO Page Mode
Average Power
Supply Current
-
110
-
100
-
90
mA
RAS and address = VIL,
UCAS , LCAS and
Address cycling;
tPC = min.
1, 2
ICC5
CAS -before- RAS
Refresh Power
Supply Current
-
120
-
110
-
100
mA
RAS, UCAS or LCAS
cycling;
tRC = min.
1
ICC6
CMOS Standby
Power Supply
Current
-
0.2
-
0.2
-
0.2
mA
RAS= UCAS = LCAS = WE
= VCC - 0.2V
ICC7
Self Refresh Mode
Current
-
250
-
250
-
250
µA
RAS= CAS ≤VSS+0.2V
All other input high levels
are VCC-0.2V or input low
levels are VSS +0.2V
2.4
-
2.4
-
2.4
-
V
IOUT = -2mA
-
0.4
-
0.4
-
0.4
V
IOUT = 2mA
VOH
RAS and Address cycling,
1, 2
1
UCAS = LCAS = VIH,
tRC = min.
Output Voltage
VOL
PRELIMINARY
(June, 2001, Version 0.0)
5
AMIC Technology, Inc.
A42L0616 Series
AC Characteristics (VCC = 3.3V ± 0.3%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
#
Std
Symbol
-45
-50
-60
Parameter
Unit
Notes
50
ns
4, 5
-
16
ms
3
-
104
-
ns
30
-
40
-
ns
10K
50
10K
60
10K
ns
7
10K
8
10K
10
10K
ns
RAS to CAS Delay Time
19
31
20
35
20
43
ns
6
tRAD
RAS to Column Address Delay Time
14
22
15
25
15
30
ns
7
7
tRSH
CAS to RAS Hold Time
13
-
13
-
17
-
ns
8
tCSH
CAS Hold Time
36
-
40
-
50
-
ns
9
tCRP
CAS to RAS Precharge Time
5
-
5
-
5
-
ns
10
tASR
Row Address Setup Time
0
-
0
-
0
-
ns
11
tRAH
Row Address Hold Time
9
-
10
-
10
-
ns
12
tCLZ
CAS to Output in Low Z
3
-
3
-
3
-
ns
8
13
tRAC
Access Time from RAS
-
45
-
50
-
60
ns
6,7
14
tCAC
Access Time from CAS
-
13
-
15
-
17
ns
6, 13
15
tAA
Access Time from Column Address
-
23
-
25
-
30
ns
7, 13
16
tAR
Column Address Hold Time from RAS
23
-
25
-
30
-
ns
17
tRCS
Read Command Setup Time
0
-
0
-
0
-
ns
18
tRCH
Read Command Hold Time
0
-
0
-
0
-
ns
9
19
tRRH
Read Command Hold Time Reference
to RAS
0
-
0
-
0
-
ns
9
Min.
Max.
Min.
Max.
Min.
Max.
Transition Time (Rise and Fall)
1
50
1
50
1
tREF
Refresh Period
-
16
-
16
1
tRC
Random Read or Write Cycle Time
79
-
84
2
tRP
RAS Precharge Time
30
-
3
tRAS
RAS Pulse Width
45
4
tCAS
CAS Pulse Width
5
tRCD
6
tT
PRELIMINARY
(June, 2001, Version 0.0)
6
AMIC Technology, Inc.
A42L0616 Series
AC Characteristics (continued) (VCC = 3.3V ± 0.3%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
#
Std
Symbol
-45
-50
-60
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
23
-
25
-
30
-
ns
Notes
20
tRAL
Column Address to RAS Lead Time
21
tCOH
Output Hold After CAS Low
4
-
5
-
5
-
ns
22
tODS
Output Disable Setup Time
0
-
0
-
0
-
ns
23
tOFF
Output Buffer Turn-Off Delay Time
3
13
3
13
3
15
ns
24
tASC
Column Address Setup Time
0
-
0
-
0
-
ns
25
tCAH
Column Address Hold Time
7
-
8
-
10
-
ns
26
tOES
OE Low to CAS High Set Up
3
-
3
-
3
-
ns
27
tWCS
Write Command Setup Time
0
-
0
-
0
-
ns
11
28
tWCH
Write Command Hold Time
8
-
10
-
10
-
ns
11
29
tWCR
Write Command Hold Time to RAS
23
-
25
-
30
-
ns
30
tW P
Write Command Pulse Width
8
-
10
-
10
-
ns
31
tR W L
Write Command to RAS Lead Time
10
-
13
-
15
-
ns
32
tC W L
Write Command to CAS Lead Time
7
-
8
-
10
-
ns
33
tDS
Data-in setup Time
0
-
0
-
0
-
ns
12
34
tDH
Data-in Hold Time
7
-
8
-
10
-
ns
12
35
tDHR
Data-in Hold Time to RAS
23
-
25
-
30
-
ns
36
tR W C
Read-Modify-Write Cycle Time
105
-
115
-
140
-
ns
37
tR W D
RAS to WE Delay Time
(Read-Modify-Write)
59
-
67
-
79
-
ns
11
38
tC W D
CAS to WE Delay Time
(Read-Modify-Write)
28
-
32
-
36
-
ns
11
PRELIMINARY
(June, 2001, Version 0.0)
7
8, 10
AMIC Technology, Inc.
A42L0616 Series
AC Characteristics (continued) (VCC = 3.3V ± 0.3%, VSS = 0V, Ta = 0°C to +70°C)
Test Conditions:
Input timing reference level: VIH/VIL=2.0V/0.8V
Output reference level: VOH/VOL=2.0V/0.8V
Output Load: 2TTL gate + CL (50pF)
Assumed tT=2ns
#
Std
Symbol
39
tAWD
40
tOEH
41
-45
Parameter
-50
-60
Unit
Notes
-
ns
11
15
-
ns
-
5
-
ns
20
-
25
-
ns
14
25
-
28
-
35
ns
13
7
-
8
-
10
-
ns
EDO Page Mode RMW Cycle Time
39
-
47
-
56
-
ns
tCRW
EDO Page Mode CAS Pulse Width
(RMW)
31
-
34
-
38
-
ns
47
tRASP
RAS Pulse Width
45
200K
50
200K
60
200K
ns
48
tCSR
CAS Setup Time ( CAS -before- RAS)
5
-
5
-
5
-
ns
3
49
tCHR
CAS Hold Time
10
-
10
-
10
-
ns
3
50
tRPC
RAS to CAS Precharge Time
( CAS -before- RAS)
5
-
5
-
5
-
ns
51
tROH
RAS Hold Time Reference to OE
5
-
5
-
5
-
ns
52
tOEA
OE Access Time
-
13
-
13
-
15
ns
53
tOED
OE to Data Delay
10
-
13
-
15
-
ns
54
tOEZ
Output Buffer Turn-off Delay from OE
3
13
3
13
3
13
ns
55
tRASS
100
-
100
-
100
-
µs
56
tRPS
RAS precharge time
( C -B- R self refresh)
79
-
90
-
110
-
ns
57
tCHS
CAS hold time ( C -B- R self refresh)
-
50
-
50
-
50
ns
Min.
Max.
Min.
Max.
Min.
Max.
37
-
42
-
49
OE Hold Time from WE During
10
-
13
-
tOEP
OE High Pulse Width
5
-
5
42
tPC
Read or Write Cycle Time (EDO Page)
16
-
43
tCPA
Access Time from CAS Precharge
(EDO Page)
-
44
tCP
CAS Precharge Time (EDO Page)
45
tPCM
46
PRELIMINARY
Column Address to WE Delay Time
(Read-Modify-Write)
(EDO Page)
( CAS -before- RAS)
RAS pulse width ( C -B- R self refresh)
(June, 2001, Version 0.0)
8
8
AMIC Technology, Inc.
A42L0616 Series
Notes:
1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate.
2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open.
3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is
achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of
8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks.
4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and
50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC.
5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH and VIL.
6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference
point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC .
7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA.
8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent).
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output
voltage levels.
11. tWCS, tW CH , tR W D, tC W D and tA WD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only. If tW CS ≥ tWCS (min.) and tW CH ≥ tWCH (min.), the cycle is an early write cycle
and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tR W D ≥ tR W D (min.) , tC W D ≥
tC W D (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from
the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is
indeterminate.
12.
in
13.
14.
These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge
read-modify-write cycles.
Access time is determined by the longer of tAA or tCAC or tCPA.
tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.
PRELIMINARY
(June, 2001, Version 0.0)
9
AMIC Technology, Inc.
A42L0616 Series
Word Read Cycle
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
tCRP(9)
tCAS(4)
UCAS
LCAS
tRAD(6)
tASR(10)
Address
tRAL(20)
tRAH(11)
tASC(24)
Row Address
tCAH(25)
Column Address
tAR(16)
tRCH(18)
tRCS(17)
tRRH(19)
WE
tROH(51)
tOEA(52)
OE
tCAC(14)
tAA(15)
tRAC(13)
I/O0 ~
I/O15
tOFF(23)
tOEZ(54)
High-Z
Valid Data-out
tCLZ(12)
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
10
AMIC Technology, Inc.
A42L0616 Series
Word Write Cycle (Early Write)
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
UCAS
tCRP(9)
tCAS(4)
LCAS
tAR(16)
tRAD(6)
tASR(10)
tRAL(20)
tRAH(11)
tCAH(25)
tASC(24)
Address
Row Address
Column Address
tWCR(29)
tCWL(32)
tRWL(31)
tWP(30)
WE
tWCS(27)
tWCH(28)
OE
tDHR(35)
tDS(33)
I/O0 ~
I/O15
tDH(34)
Valid Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
11
AMIC Technology, Inc.
A42L0616 Series
Word Write Cycle (Late Write)
tRC(1)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
UCAS
tCRP(9)
tCAS(4)
LCAS
tAR(16)
t RAD(6)
tASR(10)
tRAL(20)
tRAH(11)
tCAH(25)
tASC(24)
Address
Row Address
Column Address
tCWL(32)
tRWL(31)
tWCR(29)
tWP(30)
WE
tOEH(40)
tOED(53)
OE
tDHR(35)
tDS(33)
I/O0 ~
I/O15
tDH(34)
High-Z
Vaild Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
12
AMIC Technology, Inc.
A42L0616 Series
Word Read-Modify-Write Cycle
tRWC(36)
tRAS(3)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tRCD(5)
tRSH(7)
UCAS
tCRP(9)
tCAS(4)
LCAS
tAR(16)
tRAD(6)
tASR(10)
Address
tRAH(11)
tASC(24)
Row Address
tCAH(25)
Column Address
tAWD(39)
tCWL(32)
tCWD38)
tRCS(17)
tRWD(37)
tRWL(31)
WE
tWP(30)
tOED(53)
tOEA(52)
tOEZ(54)
OE
tOEH(40)
tCAC(14)
tAA(15)
tDS(33)
tDH(34)
tRAC(13)
I/O0 ~
I/O15
High-Z
Data-out
Data-in
tCLZ(12)
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
13
AMIC Technology, Inc.
A42L0616 Series
EDO Page Mode Word Read Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8)
t CRP(9)
tPC(42)
tRSH(7)
tCRP(9)
t RCD(5)
tCP(44)
tCAS(4)
tCAS(4)
tCAS(4)
UCAS
LCAS
tCSH(8)
tAR(16)
tASR(10)
Address
tRAD(6)
tRAH(11)
tRAL(20)
tCAH(25)
tCAH(25)
tASC(24)
Row
Column
tASC(24)
Column
tCAH(25)
Column
tRCS(17)
tRCS(17)
tRCH(25)
tRCH(25)
tRCS(17)
WE
tAA(15)
tAA(15)
tRRH(19)
tCPA(43)
tOEA(52)
tOEA(52)
tOES(26)
OE
tCAC(14)
tRAC(13)
tCAC(14)
tOEP(41)
tCOH(21)
tCLZ(12)
I/O0 ~
I/O15
Data-out
tOFF(23)
tCAC(14)
tOEZ(54)
tOEZ(54)
Data-out
Data-out
tCLZ(12)
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
14
AMIC Technology, Inc.
A42L0616 Series
EDO Page Mode Early Word Write Cycle
tRASP(47)
tRP(2)
RAS
tCSH(8)
tCRP(9)
tPC(42)
tRSH(7)
tCRP(9)
tRCD(5)
tCAS(4)
tCP(44)
tCAS(4)
tCP(44)
tCAS(4)
UCAS
LCAS
tRAL(20)
tRAD(6)
tASR(10)
Address
tCAH(25)
tRAH(11)
tASC(24)
tCAH(25)
tASC(24)
Row
tCAH(25)
tASC(24)
Column
Column
tCWL(32)
tCWL(32)
Column
t CWL(32)
tRWL(31)
tWCS(27)
t WCS(27)
tWCS(27)
tWCH(28)
tWCH(28)
t WCH(28)
WE
tWP(30)
tWP(30)
tWP(30)
OE
tDH(34)
tDS(33)
I/O0 ~
I/O15
tDH(34)
tDS(33)
Data-in
tDH(34)
tDS(33)
Data-in
Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
15
AMIC Technology, Inc.
A42L0616 Series
EDO Page Mode Word Read-Modify-Write Cycle
tRP(2)
tRASP(47)
RAS
tCSH(8)
tCRP(9)
tPCM(45)
tRSH(7)
tCRP(9)
tRCD(5)
tCAS(4)
tCP(44)
tCAS(4)
tCP(44)
tCAS(4)
UCAS
LCAS
tRAL(20)
tRAD(6)
tASR(10)
tCAH(25)
tRAH(11)
tASC(24)
Address
Row
tCAH(25)
tCAH(25)
tASC(24)
Column
tASC(24)
Column
Column
tCWL(32)
tCWL(32)
tCWL(32)
tRWD(37)
tRWL(31)
tRCS(17)
tCWD(38)
tCWD(38)
tCWD(38)
WE
tWP(30)
tAWD(39)
tWP(30)
tAWD(39)
tWP(30)
tAWD(39)
tROH(51)
tOEA(52)
tOEA(52)
tOEA(52)
OE
tOEH(40)
tOED(53)
tCAC(14)
tOED(53)
tCPA(43)
tAA(15)
tAA(15)
tOEZ(54)
tOEZ(54)
tOEZ(54)
tDH(34)
tDH(34)
tDS(33)
tDS(33)
tDS(33)
I/O 0 ~
I/O 15
tAA(15)
tDH(34)
tRAC(13)
tOED(53)
tCPA(43)
High-Z
tCLZ(12)
tCLZ(12)
tCLZ(12)
Data-in
Data-out
Data-in
Data-out
Data-in
Data-out
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
16
AMIC Technology, Inc.
A42L0616 Series
RAS Only Refresh Cycle
tRC(1)
tRAS(3)
tRP(2)
RAS
tRPC(50)
tCRP(9)
UCAS
LCAS
tASR(10)
tRAH(11)
Address
Row
Note: WE, OE = Don't care.
: High or Low
CAS Before RAS Refresh Cycle
tRC(1)
t RP(2)
tRAS(3)
tRP(2)
RAS
tRPC(50)
tCHR(49)
tCSR(48)
tPC(42)
UCAS
LCAS
t OFF(23)
High-Z
I/O0 ~
I/O15
Note: WE, OE, Address = Don't care.
PRELIMINARY
(June, 2001, Version 0.0)
: High or Low
17
AMIC Technology, Inc.
A42L0616 Series
Hidden Refresh Cycle (Word Read)
tRC(1)
tRC(1)
tRAS(3)
tRP(2)
tRAS(3)
tRP(2)
RAS
tAR(16)
tCRP(9)
tRCD(5)
t RSH(7)
tCHR(49)
tCRP(9)
UCAS
LCAS
tRAD(6)
tASR(10)
tRAL(20)
tCAH(25)
tRAH(11)
tASC(24)
Address
Row
Column
tRCS(17)
tRRH(19)
WE
tAA(15)
OE
tCAC(14)
tOFF(23)
tCLZ(12)
tRAC(13)
I/O0 ~
I/O15
High-Z
Valid Data-out
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
18
AMIC Technology, Inc.
A42L0616 Series
Hidden Refresh Cycle (Early Word Write)
tRC(1)
tRC(1)
tRAS(3)
tRP(2)
tRAS(3)
tRP(2)
RAS
tAR(16)
tCRP(9)
tRCD(5)
tRSH(7)
tCHR(49)
tCRP(9)
UCAS
LCAS
tRAD(6)
tASR(10)
tRAH(11)
tRAL(20)
tCAH(25)
tASC(24)
Address
Row
Column
tWCS(27)
tWCH(28)
tWP(30)
WE
OE
tDS(33)
I/O0 ~
I/O15
tDH(34)
Valid Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
19
AMIC Technology, Inc.
A42L0616 Series
EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
tRP(2)
tRASP(47)
RAS
tCSH(8)
tPC(42)
tCRP(9)
tRCD(5)
tCAS(4)
tPC(42)
tCP(44)
tCAS(4)
tRSH(7)
tCP(44)
tCAS(4)
tCPR(9)
UCAS
LCAS
tRAD(6)
tRAL(20)
tRAD(6)
tASR(10)
Address
tASC(24)
tRAH(11) tASC(24)
Row
tCAH(25)
tASC(24)
tCAH(25)
Column
Column
tCAH(25)
Column
tRCH(18)
tRCS(17)
tWCS(27)
WE
tWCH(28)
tAA(15)
tAA(15)
tCAP(43)
tDS(33)
tDH(34)
tRAC(13)
tCAC(14)
tCAC(14)
tOEA(52)
OE
tCOH(21)
I/O0 ~
I/O15
Data-out
Data-out
Data-in
: High or Low
PRELIMINARY
(June, 2001, Version 0.0)
20
AMIC Technology, Inc.
A42L0616 Series
Self Refresh Mode (A42L06161-L Only)
tRP(2)
tRASS(55)
tRPS(56)
RAS
tCHS(57)
tCSR(48)
tRPC(50)
tCRP(9)
UCAS
LCAS
tCPN(42)
tASR(10)
ROW
A0 ~ A7
COL
tOFF(23)
High-Z
I/O0 ~
I/O15
: High or Low
Note: WE, OE = Don't care.
n Self Refresh Mode.
a. Entering the Self Refresh Mode:
The A42L06161-L Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal
“low” longer than 100µs.
b. Continuing the Self Refresh Mode:
The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode.
It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode.
c. Exiting the Self Refresh Mode:
The A42L06161 exits the Self Refresh Mode when the RAS signal is brought “high”.
PRELIMINARY
(June, 2001, Version 0.0)
21
AMIC Technology, Inc.
A42L0616 Series
Capacitance (f = 1MHz, Ta = Room Temperature, VCC = 3.3V ± 0.3%)
Symbol
Signals
CIN1
A0 – A9
CIN2
RAS , UCAS ,
Parameter
Max.
Unit
Test Conditions
5
pF
Vin = 0V
Input Capacitance
7
pF
Vin = 0V
I/O Capacitance
7
pF
Vin = Vout = 0V
LCAS , WE ,
OE
CI/O
I/O0 - I/O15
Ordering Codes
Package\ RAS Access Time
45ns
50ns
60ns
Refresh
Cycle
SelfRefresh
42L SOJ (400mil)
A42L0616S-45
A42L0616S-50
A42L0616S-60
1K
No
50(44)L TSOP type II (400mil)
A42L0616V-45
A42L0616V-50
A42L0616V-60
1K
No
42L SOJ (400mil)
A42L0616S-45L
A42L0616S-50L
A42L0616S-60L
1K
Yes
50(44)L TSOP type II (400mil)
A42L0616V-45L
A42L0616V-50L
A42L0616V-60L
1K
Yes
PRELIMINARY
(June, 2001, Version 0.0)
22
AMIC Technology, Inc.
A42L0616 Series
Package Information
unit: inches/mm
22
1
21
E
42
HE
SOJ 42L Outline Dimensions
L
A2
A
C
D
A1
e
D
b
b1
S
Seating Plane
Symbol
e1
y
θ
Dimensions in inches
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
0.128
0.138
0.148
3.25
3.51
3.76
A1
0.025
-
-
0.64
-
-
A2
0.105
0.110
0.115
2.67
2.79
2.92
b1
0.026
0.028
0.032
0.66
0.71
0.81
b
0.015
0.018
0.020
0.38
0.46
0.51
C
0.007
0.008
0.013
0.18
0.20
0.33
D
1.075
1.080
1.085
27.31
27.43
27.56
E
0.395
0.400
0.405
10.03
10.16
10.29
e
-
0.050
-
-
1.27
-
e1
-
0.370
-
-
9.4
-
HE
0.435
0.440
0.445
11.05
11.18
11.30
L
0.082
-
-
2.08
-
-
S
-
-
0.045
-
-
1.14
y
-
-
0.003
-
-
0.075
θ
0°
-
10°
0°
-
10°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e 1 is for PC Board surface mount pad pitch design
reference only.
4. Dimension S includes end flash.
PRELIMINARY
(June, 2001, Version 0.0)
23
AMIC Technology, Inc.
A42L0616 Series
Package Information
TSOP 50/44L (Type II) Outline Dimensions
unit: inches/mm
50
26
Detail "A"
E
HE
RAD R
θ
RAD R1
L
L1
1
25
D
B
e
D
S
A
A1
A2
c
Detail "A"
y
Seating Plane
Dimensions in inches
Symbol
Dimensions in mm
Min
Nom
Max
Min
Nom
Max
A
-
-
0.048
-
-
1.20
A1
0.002
-
0.006
0.05
-
0.15
A2
0.037
0.039
0.042
0.95
1.00
1.05
B
0.012
-
0.018
0.30
-
0.45
c
0.005
-
0.008
0.12
-
0.21
D
0.820
0.825
0.830
20.82
20.95
21.08
E
0.395
0.400
0.405
10.03
10.16
10.29
e
0.0315 BSC
0.80 BSC
HE
0.455
0.463
0.471
11.56
11.76
11.96
L
0.016
0.020
0.024
0.40
0.50
0.60
R
0.005
-
0.010
0.12
-
0.25
R1
0.005
-
-
0.12
-
-
S
0.0435 REF
0.875 BSC
θ
0°
-
5°
0°
-
5°
y
-
-
0.004
-
-
0.1
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
PRELIMINARY
(June, 2001, Version 0.0)
24
AMIC Technology, Inc.