ETC AT49F080-15CI

Features
• Single Voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 90 ns
Internal Program Control and Timer
16K Bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte-By-Byte Programming - 10 µs/Byte Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 50 mA Active Current
– 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
Description
The AT49F080(T) is a 5-volt only in-system Flash Memory device. Its 8-megabits of
memory is organized as 1,024,576 words by 8-bits. Manufactured with Atmel’s
advanced nonvolatile CMOS technology, the device offers access times to 90 ns with
power dissipation of just 275 mW over the commercial temperature range. When the
device is deselected, the CMOS standby current is less than 100 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49F080 locates the boot block at lowest order
addresses (“bottom boot”); the AT49F080T locates it at highest order addresses (“top
(continued)
boot”).
Pin Name
Function
A0 - A19
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
RDY/BUSY
Ready/Busy Output
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O3
GND
GND
TSOP Top VIew
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AT49F080
AT49F080T
SOIC
Pin Configurations
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
8-Megabit
(1M x 8)
5-volt Only
Flash Memory
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
NC
NC
WE
OE
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
CBGA Top View
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE
OE
RDY/BUSY
I/O7
I/O6
I/O5
I/O4
VCC
GND
GND
I/O3
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
A5
A8 A11 NC A12 A15 A17
A4
A7 A10 VCC A13 NC A18
A6
A9 RST CE A14 A16 A19
A
B
C
D
A3 I/O1 NC VCC I/O4 I/O7 NC
E
A2
A0 I/O3 GND I/O6 OE NC
F
A1 I/O0 I/O2 GND I/O5 RY/BY WE
Rev. 0584C–10/98
1
To allow for simple in-system reprogrammability, the
AT49F080(T) does not require high input voltages for programming. 5-volt-only commands determine the read and
programming operation of the device. Reading data out of
the device is similar to reading from an EPROM. Reprogramming the AT49F080(T) is performed by erasing the
entire 8 megabits of memory and then programming on a
byte-by-byte basis. The typical byte programming time is a
fast 10 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles
The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
AT49F080
AT49F080T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
OE
WE
CE
OE, CE, AND WE
LOGIC
8
DATA LATCH
DATA LATCH
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
Y-GATING
Y DECODER
Y-GATING
FFFFFH
ADDRESS
INPUTS
X DECODER
MAIN MEMORY
(1008K BYTES)
OPTIONAL BOOT
BLOCK (16K BYTES)
04000H
03FFFH
00000H
FFFFFH
OPTIONAL BOOT
BLOCK (16K BYTES)
MAIN MEMORY
(1008K BYTES)
FC000H
FBFFFH
00000H
Device Operation
READ: The AT49F080(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention.
ERASURE: Before a byte can be reprogrammed, the
1024K bytes memory array (or 1008K bytes if the boot
block featured is used) must be erased. The erased state
of the memory bits is a logical “1”. The entire device can be
erased at one time by using a 6-byte software code. The
software chip erase code consists of 6-byte load commands to specific address locations with a specific data
pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
2
AT49F080(T)
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is
AT49F080(T)
optional to the user. The address range of the AT49F080
boot block is 00000H to 03FFFH while the address range
of the AT49F080T boot block is FC000H to FFFFFH.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out for the AT49F080, and a read from address
location F3002H will show if programming the boot block is
locked out for the AT49F080T. If the data on I/O0 is low,
the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been activated and
the block cannot be programmed. The software product
identification exit code should be used to return to standard
operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming
lockout by taking the RESET pin to 12V ± 0.5V. By doing
this, protected boot block data can be altered through a
chip erase, or byte programming. When the RESET pin is
brought back to TTL levels, the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F080(T) features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling, the
AT49F080(T) provides another method for determining the
end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
RDY/BUSY: An open drain READY/BUSY output pin provides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection
allows for OR - tying of several devices to the same
RDY/BUSY line.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program
or erase operation, the operation may not be successfully
completed and the operation will have to be repeated after
a high level is applied to the RESET pin. When a high level
is reasserted on the RESET pin, the device returns to the
read or standby mode, depending upon the state of the
control inputs. By applying a 12V ± 0.5V input signal to the
RESET pin, the boot block array can be reprogrammed
even if the boot block lockout feature has been enabled
(see Boot Block Programming Lockout Override section).
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F080(T)
in the following ways: (a) VCC sense: if VCC is below 3.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
3
Command Definition (in Hex)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
4
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
5555
AA
2AAA
55
5555
A0
Addr
DIN
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID Entry
3
5555
AA
2AAA
55
5555
90
Product ID Exit(2)
3
5555
AA
2AAA
55
5555
F0
(2)
1
XXXX
F0
Byte Program
Boot Block Lockout
Product ID Exit
Notes:
(1)
1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F080 and FC000H to FFFFFH for the
AT49F080T.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
4
AT49F080(T)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT49F080(T)
DC and AC Operating Range
AT49F080(T)-90
AT49F080(T)-12
AT49F080(T)-15
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
RESET
Ai
I/O
RDY/BUSY
VIL
VIL
VIH
VIH
Ai
DOUT
VOH
VIL
VIH
VIL
VIH
Ai
DIN
VOL
Standby/Write
Inhibit
VIH
X(1)
X
VIH
X
High Z
VOH
Program Inhibit
X
X
VIH
VIH
VOH
Program Inhibit
X
VIL
X
VIH
VOH
Output Disable
X
VIH
X
VIH
RESET
X
X
X
VIL
X
High Z
VIL
VIL
VIH
VIH
A1 - A19 = VIL, A9 = VH,(3) A0 = VIL
Manufacturer Code(4)
A1 - A19 = VIL, A9 = VH,(3) A0 = VIH
Device Code(4)
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A19 = VIL
Device Code(4)
Read
Program
(2)
High Z
VOH
Product Identification
Hardware
Software(5)
Notes:
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V
4. Manufacturer Code: 1FH
Device Code: 23H (AT49F080), 27H (AT49F080T)
5. See details under Software Product Identification Entry/Exit..
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
Com.
100
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
Ind.
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
Note:
Min
2.0
V
0.45
V
1. ICC in the erase mode is 90 mA.
5
AC Read Characteristics
AT49F080(T)-90
Symbol
Parameter
tACC
Min
Max
AT49F080(T)-12
Min
Max
AT49F080(T)-15
Min
Max
Units
Address to Output Delay
90
120
150
ns
(1)
CE to Output Delay
90
120
150
ns
(2)
OE to Output Delay
0
40
0
50
0
70
ns
tDF(3)(4)
CE or OE to Output Float
0
25
0
30
0
40
ns
tOH
Output Hold from OE, CE or Address,
whichever occurred first
0
tCE
tOE
0
0
ns
AC Read Waveforms
ADDRESS
ADDRESS VALID
CE
tCE
tOE
OE
tDF
tOH
tACC
HIGH Z
OUTPUT
Notes:
OUTPUT
VALID
1.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2.
OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3.
tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement level
Output Test Load
5.0V
3.0V
AC
DRIVING
LEVELS
1.5V
0.0V
AC
MEASUREMENT
LEVEL
1.8K
OUTPUT
PIN
1.3K
100 pF
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
6
1. This parameter is characterized and is not 100% tested.
AT49F080(T)
AT49F080(T)
AC Byte Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
90
ns
AC Byte Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
CE
tCS
WE
tWP
tDS
tWPH
tDH
DATA IN
CE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
WE
tCS
CE
tWP
tDS
tWPH
tDH
DATA IN
7
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte Programming Time
10
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tWPH
Write Pulse Width High
90
ns
tEC
Erase Cycle Time
10
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
tWP
tWPH
tBP
WE
tAS
A0-A19
tAH
5555
tDH
2AAA
5555
ADDRESS
tDS
AA
DATA
55
INPUT
DATA
A0
Chip Erase Cycle Waveforms
OE
CE
tWP
tWPH
WE
tAS
A0-A19
tAH
5555
tDH
2AAA
5555
5555
2AAA
5555
tDS
DATA
Note:
8
tEC
AA
55
80
AA
55
10
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
OE must be high only when WE and CE are both low.
AT49F080(T)
seconds
AT49F080(T)
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
tWR
HIGH Z
I/O7
A0-A19
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
OE to Output Delay
tOEHP
OE High Pulse
tWR
Max
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
Write Recovery Time
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tOEHP
OE
tDH
I/O6
Notes:
tOE
tWR
HIGH Z
1.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2.
Beginning and ending state of I/O6 will vary.
3.
Any address location may be used but the address should not vary.
9
Software Product
Identification Entry(1)
Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Software Product
Identification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
EXIT PRODUCT
IDENTIFICATION
MODE(4)
EXIT PRODUCT
IDENTIFICATION
MODE(4)
10
PAUSE 1 second(2)
Notes:
LOAD DATA F0
TO
ADDRESS 5555
Notes:
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA F0
TO
ANY ADDRESS
1.
Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2.
A1 - A19 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3.
The device does not remain in identification mode if
powered down.
4.
The device returns to standard operation mode.
5.
Manufacturers Code: 1FH
Device Code: 23H (AT49F080), 27H (AT49F080T)
AT49F080(T)
1.
Data Format: I/07 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2.
Boot block lockout feature enabled.
AT49F080(T)
AT49F080 Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
90
50
0.1
AT49F080-90CC
AT49F080-90RC
AT49F080-90TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
0.3
AT49F080-90CI
AT49F080-90RI
AT49F080-90TI
42C2
44R
40T
Industrial
(-40° to 85°C)
50
0.1
AT49F080-12CC
AT49F080-12RC
AT49F080-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
0.3
AT49F080-12CI
AT49F080-12RI
AT49F080-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
50
0.1
AT49F080-15CC
AT49F080-15RC
AT49F080-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
0.3
AT49F080-15TI
AT49F080-15TI
AT49F080-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
120
150
Operation Range
(continued)
Package Type
42C2
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44R
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40T
40-Lead, Thin Small Outline Package (TSOP)
11
AT49F080T Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
90
50
120
150
Ordering Code
Package
0.1
AT49F080T-90CC
AT49F080T-90RC
AT49F080T-90TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
0.3
AT49F080T-90CI
AT49F080T-90RI
AT49F080T-90TI
42C2
44R
40T
Industrial
(-40° to 85°C)
50
0.1
AT49F080T-12CC
AT49F080T-12RC
AT49F080T-12TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
0.3
AT49F080T-12CI
AT49F080T-12RI
AT49F080T-12TI
42C2
44R
40T
Industrial
(-40° to 85°C)
50
0.1
AT49F080T-15CC
AT49F080T-15RC
AT49F080T-15TC
42C2
44R
40T
Commercial
(0° to 70°C)
50
0.3
AT49F080T-15CI
AT49F080T-15RI
AT49F080T-15TI
42C2
44R
40T
Industrial
(-40° to 85°C)
Package Type
42C2
42-Ball, Plastic Chip-Size Ball Grid Array Package (CBGA) 8 x 14 mm
44R
44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC/SOP)
40T
40-Lead, Thin Small Outline Package (TSOP)
12
AT49F080(T)
Operation Range
AT49F080(T)
Packaging Information
44R, 44-Lead, 0.525" Wide,
Plastic Gull Wing Small Outline (SOIC)
Dimensions in Inches and (Millimeters)
40T, 40-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches) *
*Controlling dimension: millimeters
42C2, 42-Ball, Plastic Chip-Size Ball Grid Array
Package (CBGA)
Dimensions in Millimeters and (Inches) *
8.2 (0.323)
7.8 (0.307)
14.2 (0.559)
13.8 (0.543)
0.30 (0.012)
1.40 (0.055) MAX
1.12 (0.044)
0.86 (0.034)
6.0 (0.236)
7
6
5
4
3
2
1
4.6 (0.181)
4.3 (0.169)
A
B
C
5.0 (0.197)
D
E
F
0.46 (0.018)
DIA BALL TYP
1.00 (0,039) BSC
NON-ACCUMULATIVE
13
14
AT49F080(T)
AT49F080(T)
15
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© Atmel Corporation 1998.
Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s website. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
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®
and/or
™
are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
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0584C–10/98/xM