ETC AT49LV1024-70VC

Features
• Single-voltage Operation
•
•
•
•
•
•
•
•
•
– 3V Read
– 3.1V Programming
Fast Read Access Time – 55 ns
Internal Program Control and Timer
8K Word Boot Block with Lockout
Fast Erase Cycle Time – 10 seconds
Word-by-Word Programming – 20 µs/Word Typical
Hardware Data Protection
Data Polling for End of Program Detection
Small 10 x 14 mm VSOP Package
Typical 10,000 Write Cycles
Description
The AT49LV1024 and the AT49LV1025 are 3-volt only in-system Flash memories.
Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 55 ns with power dissipation of just 90 mW over the commercial temperature range.
The only difference between the AT49LV1024 and the AT49LV1025 is the package.
To allow for simple in-system reprogrammability, the AT49LV1024/1025 does not
require high input voltages for programming. Three-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49LV1024/1025 is performed
1-megabit
(64K x 16)
3-volt Only
Flash Memory
AT49LV1024
AT49LV1025
(continued)
Pin Configurations
Pin Name
Function
A0 - A15
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O15
Data Inputs/Outputs
NC
No Connect
AT49LV1024 VSOP Top View
Type 1
10 x 14 mm
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
I/O3
I/O2
I/O1
I/O0
OE
NC
A0
A1
A2
A3
A4
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
I/O4
6
5
4
3
2
1
44
43
42
41
40
I/O13
I/O14
I/O15
CE
NC
NC
VCC
WE
NC
A15
A14
AT49LV1025 PLCC Top View
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
NC
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
Rev. 1278D–07/01
1
by erasing a block of data (entire chip or main memory block) and then programming on
a word by word basis. The typical word programming time is a fast 20 µs. The end of a
program cycle can be optionally detected by the Data Polling feature. Once the end of a
byte program cycle has been detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 8K word boot block section includes a reprogramming write lock out feature
to provide data integrity. The boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is permanently protected from being erased
or reprogrammed.
Block Diagram
DATA INPUTS/OUTPUTS
I/O15 - I/O0
VCC
GND
OE
WE
CE
ADDRESS
INPUTS
16
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y DECODER
Y-GATING
X DECODER
MAIN MEMORY
(56K WORDS)
FFFFH
OPTIONAL BOOT
BLOCK (8K WORDS)
2000H
1FFFH
0000H
Device Operation
READ: The AT49LV1024/1025 is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
CHIP ERASE: When the boot block programming lockout feature is not enabled, the
boot block and the main memory block will erase together from the same Chip Erase
command (See Command Definitions table). If the boot block lockout function has been
enabled, data in the boot section will not be erased. However, data in the main memory
section will be erased. After a chip erase, the device will return to the read mode.
MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block
erase can be performed, which will erase all words not located in the boot block region
to an FFFFH. Data located in the boot region will not be changed during a main memory
block erase. The Main Memory Erase command is a six-bus cycle operation. The
address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input
is latched on the rising edge of WE. The main memory erase starts after the rising edge
of WE of the sixth cycle. Please see Main Memory Erase cycle waveforms. The main
memory erase operation is internally controlled; it will automatically time to completion.
WORD PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is
accomplished via the internal device command register and is a four-bus cycle operation (please refer to the Command Definitions table). The device will automatically
generate the required internal program pulses.
2
AT49LV1024/1025
1278D–07/01
AT49LV1024/1025
The program cycle has addresses latched on the falling edge of WE or CE, whichever
occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first.
Programming is completed after the specified tBP cycle time. The Data Polling feature
may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block
that has a programming lockout feature. This feature prevents programming of data in
the designated block once the feature has been enabled. The size of the block is 8K
words. This block, referred to as the boot block, can contain secure code that is used to
bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be
activated; the boot block’s usage as a write-protected region is optional to the user. The
address range of the boot block is 0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular
programming method and can be erased using either the Chip Erase or the Main Memory Block Erase command. To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be performed. Please refer to
the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if
programming of the boot block section is locked out. When the device is in the software
product identification mode (see Software Product Identification Entry and Exit sections)
a read from address location 0002H will show if programming the boot block is locked
out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is
high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to
standard operation.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see “Operating Modes” (for hardware operation) or “Software Product Identification Entry/Exit” on page 11. The manufacturer and device code is the same for both
modes.
DATA POLLING: The AT49LV1024/1025 features Data Polling to indicate the end of a
program or erase cycle. During a program cycle an attempted read of the last byte
loaded will result in the complement of the loaded data on I/O7. Once the program cycle
has been completed, true data is valid on all outputs and the next cycle may begin. Data
Polling may begin at any time during the program cycle.
TOGGLE BIT: In addition to Data Polling, the AT49LV1024/1025 provides another
method for determining the end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent
writes to the AT49LV1024/1025 in the following ways: (a) VCC sense: if VCC is below
1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of
OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
3
1278D–07/01
Command Definition (in Hex)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
Main Memory Erase
6
Word Program
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
30
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID Entry
3
5555
AA
2AAA
55
5555
90
(3)
3
5555
AA
2AAA
55
5555
F0
Boot Block Lockout
Product ID Exit
(2)
Product ID Exit(3)
1
xxxx
F0
Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex); A15 (Don’t Care).
2. The 8K word boot sector has the address range 00000H to 1FFFH.
3. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
4
AT49LV1024/1025
1278D–07/01
AT49LV1024/1025
DC and AC Operating Range
Operating
Temperature (Case)
AT49LV1024/1025-55
AT49LV1024/1025-70
AT49LV1024/1025-90
0°C - 70°C
0°C - 70°C
0°C - 70°C
Com.
Ind.
-40°C - 85°C
VCC Power Supply
3.0V to 3.6V
Note:
1. Minimum programming voltage is 3.1V.
(1)
3.0V to 3.6V
(1)
3.0V to 3.6V(1)
Operating Modes
Mode
CE
OE
WE
Ai
I/O
VIL
VIL
VIH
Ai
DOUT
VIL
VIH
VIL
Ai
DIN
VIH
X(1)
X
X
High-Z
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
VIL
VIL
VIH
Read
Program
(2)
Standby/Write Inhibit
High-Z
Product Identification
Hardware
A1 - A15 = VIL, A9 = VH(3), A0 = VIL
Manufacturer Code(4)
A1 - A15 = VIL, A9 = VH(3), A0 = VIH
Device Code(4)
Software(5)
Notes:
1.
2.
3.
4.
5.
A0 = VIL, A1 - A15 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A15 = VIL
Device Code(4)
X can be VIL or VIH.
Refer to AC Programming Waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 001FH; Device Code: 0087H.
See details under “Software Product Identification Entry/Exit” on page 11.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10.0
µA
Output Leakage Current
VI/O = 0V to VCC
10.0
µA
Com.
40.0
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
Ind.
130.0
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
0.5
mA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
25.0
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
Note:
Min
2.0
V
0.45
2.4
V
V
1. In the erase mode, ICC is 40 mA.
5
1278D–07/01
AC Read Characteristics
AT49LV1024/1025-55
Symbo
l
Parameter
tACC
Min
Max
AT49LV1024/1025-70
Min
Max
AT49LV1024/1025-90
Min
Max
Units
Address to Output Delay
55
70
90
ns
(1)
CE to Output Delay
55
70
90
ns
tOE(2)
OE to Output Delay
30
35
0
40
ns
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
ns
tOH
Output Hold from OE, CE or
Address, whichever occurred first
0
tCE
25
0
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
6
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AT49LV1024/1025
1278D–07/01
AT49LV1024/1025
Input Test Waveforms and Measurement Level
2.4V
0.4V
tR, tF < 5 ns
Output Test Load
3.0V
1.8K
OUTPUT
PIN
1.3K
30 pF
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
1278D–07/01
AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Setup Time
0
ns
tAH
Address Hold Time
70
ns
tCS
Chip Select Setup Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
70
ns
tDS
Data Setup Time
70
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
50
ns
AC Word Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
CE
WE
tAS
tAH
tCH
tCS
tWPH
tWP
tDH
tDS
DATA
IN
CE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
WE
tCS
CE
tWPH
tWP
tDS
DATA
8
tDH
IN
AT49LV1024/1025
1278D–07/01
AT49LV1024/1025
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Word Programming Time
20
50
µs
tAS
Address Setup Time
0
ns
tAH
Address Hold Time
70
ns
tDS
Data Setup Time
70
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
70
ns
tWPH
Write Pulse Width High
50
ns
tEC
Erase Cycle Time
1.5
5
seconds
Program Cycle Waveforms
A0-A15
Main Memory or Chip Erase Cycle Waveforms
OE
CE
t WP
t WPH
WE
t AS
A0-A15
t AH
t DH
5555
5555
5555
2AAA
5555
2AAA
t EC
t DS
DATA
AA
WORD 0
Notes:
55
WORD 1
80
WORD 2
AA
55
NOTE 2
WORD 3
WORD 4
WORD 5
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 10H. For a main memory erase, the data should be 30H.
9
1278D–07/01
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Notes:
Typ
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 6.
Toggle Bit Waveforms(1)(2)(3)
Notes:
10
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49LV1024/1025
1278D–07/01
AT49LV1024/1025
Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
Software Product Identification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
OR
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex); Address Format: A15 - A0 (Hex); A15 (Don’t Care).
2. A1 - A15 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH
Device Code: 0087H
11
1278D–07/01
Boot Block Lockout Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
PAUSE 1 second(2)
Notes:
12
1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex); Address Format: A15 - A0 (Hex); A15 (Don’t Care).
2. Boot Block Lockout feature enabled.
AT49LV1024/1025
1278D–07/01
AT49LV1024/1025
AT49LV1024 Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
55
25
70
90
Ordering Code
Package
Operation Range
0.04
AT49LV1024-55VC
40V
Commercial
(0° to 70°C)
25
0.04
AT49LV1024-70VC
40V
Commercial
(0° to 70°C)
25
0.04
AT49LV1024-90VC
40V
Commercial
(0° to 70°C)
25
0.13
AT49LV1024-90VI
40V
Industrial
(-40° to 85°C)
AT49LV1025 Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
25
0.04
AT49LV1025-55JC
44J
Commercial
(0° to 70°C)
70
25
0.04
AT49LV1025-70JC
44J
Commercial
(0° to 70°C)
90
25
0.04
AT49LV1025-90JC
44J
Commercial
(0° to 70°C)
25
0.13
AT49LV1025-90JI
44J
Industrial
(-40° to 85°C)
Operation Range
Package Type
40V
40-lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm)
44J
44-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
13
1278D–07/01
Packaging Information
40V, 40-lead, Plastic Thin Small Outline
Package (VSOP)
Dimensions in Millimeters and (Inches)*
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
*Controlling dimension: millimeters
14
AT49LV1024/1025
1278D–07/01
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Atmel Product Operations
Corporate Headquarters
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TEL (408) 441-0311
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