19-1822; Rev 1; 2/02 Single-Supply, Low-Power, Serial 8-Bit ADCs The MAX1115/MAX1116 low-power, 8-bit, analog-todigital converters (ADCs) feature an internal track/hold (T/H), voltage reference, VDD monitor, clock, and serial interface. The MAX1115 is specified from +2.7V to +5.5V, and the MAX1116 is specified from +4.5V to +5.5V. Both parts consume only 175µA at 100ksps. The full-scale analog input range is determined by the internal reference of +2.048V (MAX1115) or +4.096V (MAX1116). The MAX1115/MAX1116 also feature AutoShutdown™ power-down mode which reduces power consumption to <1µA when the device is not in use. The 3-wire serial interface directly connects to SPI™, QSPI™, and MICROWIRE™ devices without external logic. Conversions up to 100ksps are performed using an internal clock. The MAX1115/MAX1116 are available in an 8-pin SOT23 package with a footprint that is just 30% of an 8-pin SO. Features ♦ Single Supply +2.7V to +3.6V (MAX1115) +4.5V to +5.5V (MAX1116) ♦ Input Voltage Range: 0 to VREF ♦ Internal Track/Hold; 100kHz Sampling Rate ♦ Internal Reference +2.048V (MAX1115) +4.096V (MAX1116) ♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface ♦ Small 8-Pin SOT23 Package ♦ Automatic Power-Down ♦ Low Power 175µA at 100ksps 18µA at +3V and 10ksps 1µA in Power-Down Mode Ordering Information ________________________Applications Low-Power, Hand-Held Portable Devices PART TEMP RANGE PINPACKAGE TOP MARK Battery-Powered Test Equipment MAX1115EKA -40°C to +85°C 8 SOT23 AADU Receive-Signal-Strength Indicators MAX1116EKA -40°C to +85°C 8 SOT23 AADV System Diagnostics 4mA to 20mA Powered Remote Data-Acquisition Systems Pin Configuration TOP VIEW AutoShutdown is a trademark of Maxim Integrated Products. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor, Corp. VDD 1 8 SCLK CH0 7 DOUT 6 CONVST 5 I.C. 2 I.C. 3 GND 4 MAX1115 MAX1116 SOT23 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1115/MAX1116 General Description MAX1115/MAX1116 Single-Supply, Low-Power, Serial 8-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +6.0V CH0 to GND ...............................................-0.3V to (VDD + 0.3V) Digital Output to GND ................................-0.3V to (VDD + 0.3V) Digital Input to GND ..............................................-0.3V to +6.0V Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW Operating Temperature Range MAX111_EKA ..................................................-40°C to + 85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V (MAX1115), VDD = +4.5V to +5.5V (MAX1116), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 8 Relative Accuracy INL Differential Nonlinearity DNL Bits ±1 (Note 1) Offset Error LSB 0.5 LSB ±5 Gain Error Gain Temperature Coefficient 90 VDD/2 Sampling Error ±2 LSB ±1 %FSR ppm/°C ±7 % DYNAMIC PERFORMANCE (25kHz sine-wave input, VIN = VREF (P-P), fSCLK = 5MHz, fSAMPLE = 100ksps, RIN = 100Ω) Signal-to-Noise Plus Distortion SINAD 48 dB Total Harmonic Distortion (up to the 5th Harmonic) THD -69 dB Spurious-Free Dynamic Range SFDR 66 dB Small-Signal Bandwidth f-3dB 4 MHz ANALOG INPUT Input Voltage Range 0 Input Leakage Current Input Capacitance ±0.7 VCH = 0 or VDD CIN VREF V ±10 µA 18 pF INTERNAL REFERENCE Voltage VREF MAX1115 2.048 MAX1116 4.096 V POWER REQUIREMENTS Supply Voltage VDD MAX1115 2.7 5.5 MAX1116 4.5 5.5 MAX1115 Supply Current (Note 2) IDD MAX1116 Shutdown 2 fSAMPLE = 10ksps 14 21 fSAMPLE = 100ksps 135 190 fSAMPLE = 10ksps 19 25 fSAMPLE = 100ksps 182 230 0.8 10 _______________________________________________________________________________________ V µA Single-Supply, Low-Power, Serial 8-Bit ADCs (VDD = +2.7V to +3.6V (MAX1115), VDD = +4.5V to +5.5V (MAX1116), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Supply Rejection Ratio SYMBOL PSRR CONDITIONS MIN Full-scale or zero input TYP MAX UNITS ±0.5 ±1 LSB/V 0.8 V DIGITAL INPUTS (CNVST AND SCLK) Input High Voltage VIH Input Low Voltage VIL Input Hystersis 2 VHYST V 0.2 V Input Current High IIH ±10 µA Input Current Low IIL ±10 µA Input Capacitance CIN 2 pF DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage VOH VOL Three-State Leakage Current Three-State Output Capacitance ISOURCE = 2mA VDD - 0.5 V ISINK = 2mA 0.4 ISINK = 4mA 0.8 IL ±0.01 COUT 4 ±10 V µA pF TIMING CHARACTERISTICS (Figures 6a–6d) CNVST High Time tcsh 100 ns CNVST Low Time tcsl 100 ns Conversion Time tconv 7.5 µs Serial Clock High Time tch 75 ns Serial Clock Low Time tcl 75 ns Serial Clock Period tcp 200 ns Falling of CNVST to DOUT Active tcsd CLOAD = 100pF, Figure 1 Serial Clock Falling Edge to DOUT tcd CLOAD = 100pF Serial Clock Rising Edge To DOUT High-Z tchz CLOAD = 100pF, Figure 2 Last Serial Clock to Next CNVST (successive conversions on CH0) tccs 100 ns 10 100 ns 100 500 ns 50 ns Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offset have been calibrated. Note 2: Input = 0, with logic input levels of 0 and VDD. _______________________________________________________________________________________ 3 MAX1115/MAX1116 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = +3V (MAX1115), VDD = +5V (MAX1116), fscu = 5MHz, fsample = 100ksps, CLOAD = 100pF, TA = +25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 0.8 0.6 0.4 0.2 0.2 DNL (LSB) 0.4 0 -0.2 -0.4 -0.6 -0.8 -0.8 100 150 200 250 50 100 150 200 250 300 3.5 2.5 4.5 5.5 SUPPLY VOLTAGE (V) SUPPLY CURRENT vs. CONVERSION RATE SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 150 MAX1116 100 MAX1115 50 0 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 1.0 200 1 10 100 150 MAX1116 VDD = +5V 100 MAX1115 VDD = +3V 50 DOUT = 00000000 VDD = VDIGITAL INPUTS DOUT = 00000000 VDD = VREF = VDIGITAL INPUTS 0 0 0.1 MAX1115 toc06 200 MAX1115 toc04 MAX1115 VDD = +3V 2.5 3.5 4.5 -40 5.5 -15 10 35 60 CONVERSION (ksps) SUPPLY VOLTAGE (V) TEMPERATURE (°C) CONVERSION TIME vs. SUPPLY VOLTAGE CONVERSION TIME vs. TEMPERATURE GAIN ERROR vs. SUPPLY VOLTAGE 5.2 5.1 5.3 5.2 5.1 5.0 VDD = +5V 4.5 SUPPLY VOLTAGE (V) 5.5 1.0 MAX1115 VDD = +3V 0.8 MAX1116 VDD = +5V 0.6 0.4 0.2 5.0 3.5 1.2 GAIN ERROR (%FSR) 5.3 VDD = +3V 85 MAX1115 toc09 5.4 CONVERSION TIME (µs) 5.4 1.4 MAX1115 toc08 5.5 MAX1115 toc07 5.5 2.5 0.2 OUTPUT CODE MAX1116 VDD = +5V 0.01 0.3 OUTPUT CODE 100.0 10.0 0.4 0 0 300 MAX1115 toc05 50 0.5 0.1 -1.0 0 SUPPLY CURRENT (µA) -0.2 -0.6 -1.0 4 0 -0.4 0.6 SHUTDOWN CURRENT (µA) 0.6 0.7 MAX1115 toc02 0.8 INL (LSB) 1.0 MAX1115 toc01 1.0 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1115 toc03 INTEGRAL NONLINEARITY vs. OUTPUT CODE CONVERSION TIME (µs) MAX1115/MAX1116 Single-Supply, Low-Power, Serial 8-Bit ADCs 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 2.5 3.5 4.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5.5 Single-Supply, Low-Power, Serial 8-Bit ADCs GAIN ERROR vs. TEMPERATURE MAX1115 toc10 1.5 fSAMPLE = 100kHz fIN = 25.1kHz AIN = 0.9xVREF p-p -20 1.0 0.5 0 MAX1116 VDD = +5V -0.5 -40 AMPLITUDE (dB) GAIN ERROR (%FSR) 0 MAX1115 toc11 FFT PLOT 2.0 MAX1115 VDD = +3V -60 -80 -1.0 -100 -1.5 -120 -2.0 -15 10 35 60 40k 30k ANALOG INPUT FREQUENCY (Hz) OFFSET ERROR vs. SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE 0.5 MAX1115 toc12 0.4 0.3 0.1 0 -0.1 -0.2 MAX1115 VDD = +3V -0.3 0.4 0.3 OFFSET ERROR (LSB) MAX1116 VDD = +3V 0.2 20k 10k TEMPERATURE (°C) 0.5 50k MAX1116 VDD = +3V 0.2 0.1 0 -0.1 -0.2 MAX1115 VDD = +5V -0.3 -0.4 -0.4 -0.5 -0.5 2.5 3.0 3.5 4.0 4.5 5.0 -40 5.5 10 35 60 TEMPERATURE (°C) MAX1115 REFERENCE VOLTAGE vs. NUMBER OF PIECES MAX1116 REFERENCE VOLTAGE vs. NUMBER OF PIECES MAX1115 toc14 21.0% 17.5% 21.0% 17.5% 14.0% 14.0% 10.5% 10.5% 7.0% 7.0% 3.5% 3.5% 0 1.982 -15 SUPPLY VOLTAGE (V) 2.008 2.034 2.060 2.086 REFERENCE VOLTAGE (V) 2.112 0 3.980 85 MAX1115 toc15 OFFSET ERROR (LSB) 0 85 MAX1115 toc13 -40 4.020 4.060 4.100 4.140 4.180 REFERENCE VOLTAGE (V) _______________________________________________________________________________________ 5 MAX1115/MAX1116 Typical Operating Characteristics (continued) (VDD = +3V (MAX1115), VDD = +5V (MAX1116), fscu = 5MHz, fsample = 100ksps, CLOAD = 100pF, TA = +25°C, unless otherwise noted.) Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1115/MAX1116 Pin Description PIN NAME FUNCTION 1 VDD 2 CH0 Positive Supply Voltage Analog Voltage Input 3, 5 I.C. Internally Connected. Connect to ground. 4 GND 6 CNVST Ground Convert/Start Input. CNVST initiates a power-up and starts a conversion on its falling edge. 7 DOUT Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT goes low at the start of a conversion and presents the MSB at the completion of a conversion. DOUT goes high impedance once data has been fully clocked out. 8 SCLK Serial Clock. Used for clocking out data on DOUT. VDD VDD 3kΩ 3kΩ DOUT DOUT 3kΩ CLOAD CLOAD GND a) VOL TO VOH DOUT GND b) HIGH-Z TO VOL AND VOH TO VOL 3kΩ CLOAD CLOAD GND GND a) VOH TO HIGH-Z b) VOL TO HIGH-Z Figure 2. Load Circuits for Disable Time Figure 1. Load Circuits for Enable Time Detailed Description The MAX1115/MAX1116 ADCs use a successiveapproximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to an 8-bit digital output. The SPI/QSPI/MICROWIREcompatible interface directly connects to microprocessors (µPs) without additional circuitry (Figure 3). Track/Hold The input architecture of the ADC is illustrated in the equivalent-input circuit shown in Figure 4 and is composed of the T/H, input multiplexer, input comparator, switched capacitor DAC, and auto-zero rail. The acquisition interval begins with the falling edge of CNVST. During the acquisition interval, the analog input (CH0) is connected to the hold capacitor (C HOLD). Once the acquisition is complete, the T/H switch opens and CHOLD is connected to GND, which retains the charge on CHOLD as a sample of the signal at the analog input. 6 DOUT Sufficiently low source impedance is required to ensure an accurate sample. A source impedance of <1.5kΩ is recommended for accurate sample settling. A 100pF capacitor at the ADC inputs also improves the accuracy of an input sample. Conversion Process The MAX1115/MAX1116 conversion process is internally timed. The total acquisition and conversion process takes <7.5µs. Once an input sample has been acquired, the comparator’s negative input is then connected to an auto-zero supply. Since the device requires only a single supply, the negative input of the comparator is set to equal VDD/2. The capacitive DAC restores the positive input to VDD/2 within the limits of 8bit resolution. This action is equivalent to transferring a charge QIN = 16pF ✕ VIN from CHOLD to the binaryweighted capacitive DAC, which forms a digital representation of the analog-input signal. _______________________________________________________________________________________ Single-Supply, Low-Power, Serial 8-Bit ADCs 0.1µF ANALOG INPUTS CAPACITIVE DAC VDD VDD CH0 MAX1115/MAX1116 GND VDD 1µF GND CPU MAX1115 MAX1116 CHOLD 16pF CH0 COMPARATOR VDD 2 RIN 6.5kΩ I/O CONVST SCLK SCK (SK) DOUT MISO (SI) HOLD TRACK GND AUTO-ZERO RAIL Figure 3. Typical Operating Circuit Figure 4. Equivalent Input Circuit Input Voltage Range I/O CONVST Internal protection diodes that clamp the analog input to VDD and GND allow the input pin (CH0) to swing from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions, the inputs must not exceed (VDD + 50mV) or be less than (GND - 50mV). SCK SCLK MISO DOUT Input Bandwidth SS The ADC’s input tracking circuitry has a 4MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias filtering is recommended to avoid high-frequency signals being aliased into the frequency band of interest. +3V a) SPI CS CONVST SCK SCLK MISO DOUT +3V Serial Interface The MAX1115/MAX1116 have a 3-wire serial interface. The CNVST and SCLK inputs are used to control the device, while the three-state DOUT pin is used to access the conversion results. The serial interface provides connection to microcontrollers (µCs) with SPI, QSPI, and MICROWIRE serial interfaces at clock rates up to 5MHz. The interface supports either an idle high or low SCLK format. For SPI and QSPI, set CPOL = CPHA = 0 or CPOL = CPHA = 1 in the SPI control registers of the µC. Figure 5 shows the MAX1115/MAX1116 common serial-interface connections. See Figures 6a–6d for details on the serialinterface timing and protocol. MAX1115 MAX1116 MAX1115 MAX1116 SS b) QSPI I/O CONVST SK SCLK SI DOUT MAX1115 MAX1116 c) MICROWIRE Figure 5. Common Serial-Interface Connections _______________________________________________________________________________________ 7 MAX1115/MAX1116 Single-Supply, Low-Power, Serial 8-Bit ADCs ACTIVE POWER-DOWN MODE tCSH CNVST CH0 CH0 tCONV SCLK tch tcp tccs IDLE LOW IDLE LOW tcd tcsd DOUT D7 (MSB) tcl D6 D5 tchz D4 D3 D2 D1 D0 Figure 6a. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle Low ACTIVE POWER-DOWN MODE tCSH CNVST CH0 CH0 tCONV tch tcp tccs SCLK IDLE HIGH IDLE HIGH tcsd DOUT tcd D7 (MSB) tcl D6 D5 tchz D4 D3 D2 D1 D0 Figure 6b. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle High Digital Inputs and Outputs The MAX1115/MAX1116 perform conversions by using an internal clock. This frees the µP from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the µP’s convenience at any clock rate up to 5MHz. 8 The acquisition interval begins with the falling edge of CNVST. CNVST can idle between conversions in either a high or low state. If idled in a low state, CNVST must be brought high for at least 50ns, then brought low to initiate a conversion. To select VDD/2 for conversion, the CNVST pin must be brought high and low for a second time (Figures 6c and 6d). _______________________________________________________________________________________ Single-Supply, Low-Power, Serial 8-Bit ADCs POWER-DOWN MODE tCSL VDD 2 CH0 MAX1115/MAX1116 ACTIVE tCSH CH0 VDD 2 CNVST tch tCONV tcp tccs IDLE LOW SCLK IDLE LOW tcd tcsd DOUT D7 (MSB) tcl D6 D5 tchz D4 D3 D2 D1 D0 Figure 6c. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle Low ACTIVE POWER-DOWN MODE tcsl tCSH VDD 2 CH0 CH0 VDD 2 CNVST tch tCONV SCLK tccs IDLE HIGH tcsd DOUT tcp IDLE HIGH tcd D7 (MSB) tcl D6 D5 tchz D4 D3 D2 D1 D0 Figure 6d. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle High After CNVST is brought low, allow 7.5µs for the conversion to be completed. While the internal conversion is in progress, DOUT is low. The MSB is present at the DOUT pin immediately after conversion is completed. The conversion result is clocked out at the DOUT pin and is coded in straight binary (Figure 7). Data is clocked out at SCLK’s falling edge in MSB-first format at rates up to 5MHz. Once all data bits are clocked out, DOUT goes high impedance (100ns to 500ns after the rising edge) of the eighth SCLK pulse. SCLK is ignored during the conversion process. Only after a conversion is complete will SCLK cause serial data to be output. Falling edges on CNVST during an _______________________________________________________________________________________ 9 MAX1115/MAX1116 Single-Supply, Low-Power, Serial 8-Bit ADCs OUTPUT CODE FULL-SCALE TRANSITION 11111111 SYSTEM POWER SUPPLIES 11111110 GND 11111101 +3V/+5V FS = VREFIN + VIN1LSB = VREFIN 256 1µF 10Ω 0.1µF 00000011 GND 00000010 IN- VDD DGND VDD 00000001 00000000 0 1 2 3 FS INPUT VOLTAGE (LSB) DIGITAL CIRCUITRY MAX1115 MAX1116 FS - 1/2 LSB Figure 7. Input/Output Transfer Function Figure 8. Power-Supply Connections active conversion process interrupt the current conversion and cause the input multiplexer to switch to VDD/2. To reinitiate a conversion on CH0, it is necessary to allow for a conversion to be complete and all of the data to be read out. Once a conversion has been completed, the MAX1115/MAX1116 goes into Autoshutdown mode (typically <1µA) until the next conversion is initiated. The power consumption consequence of this architecture is dramatic when relatively slow conversion rates are needed. For example, at a conversion rate of 10ksps, the average supply current for the MAX1115 is 15µA, while at 1ksps it drops to 15µA. At 0.1ksps it is just 0.3µA, or a miniscule 1µW of power consumption (see Average Supply Current vs. Conversion Rate plot in the Typical Operating Characteristics sections). Applications Information Power-On Reset When power is first applied, the MAX1115/MAX1116 are in AutoShutdown (typically <1µA). A conversion can be started by toggling CNVST high to low. Powering up the MAX1115/MAX1116 with CNVST low does not start a conversion. AutoShutdown and Supply Current Requirements The MAX1115/MAX1116 are designed to automatically shutdown once a conversion is complete, without any external control. An input sample and conversion process typically takes 5µs to complete, during which time the supply current to the analog sections of the device are fully on. All analog circuitry is shutdown after a conversion completes, which results in a supply current of <1µA (see Shutdown Current vs. Supply Voltage plot in the Typical Operating Characteristics section). The digital conversion result is maintained in a static register and is available for access through the serial interface at any time. 10 Transfer Function Figure 7 depicts the input/output transfer function. Output coding is binary with a +2.048V reference, 1LSB = 8mV(VREF/256). Layout, Grounding, and Bypassing For best performance, board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or run digital lines underneath the ADC package. Figure 8 shows the recommended system-ground connections. A single-point analog ground (star-ground point) should be established at the ADC ground. Connect all analog grounds to the star-ground. The ground-return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the V DD power supply can affect the comparator in the ADC. Bypass the supply to the star ground with a 0.1µF capacitor close to the VDD pin of the MAX1115/MAX1116. Minimize capacitor lead ______________________________________________________________________________________ Single-Supply, Low-Power, Serial 8-Bit ADCs SCLK CNVST CONTROL LOGIC AND INTERNAL OCSILLATOR CH0 INPUT MULTIPLEXER INPUT TRACK AND HOLD SPLIT VDD/2 INTERNAL REFERENCE 2.096V OR 4.096V 8-BIT SAR ADC OUTPUT SHIFT REGISTER DOUT MAX1115 MAX1116 lengths for best supply-noise rejection. If the power supply is noisy, a 0.1µF capacitor in conjunction with a 10Ω series resistor can be connected to form a lowpass filter. Chip Information TRANSISTOR COUNT: 2000 PROCESS: BiCMOS ______________________________________________________________________________________ 11 MAX1115/MAX1116 Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SOT23, 8L.EPS MAX1115/MAX1116 Single-Supply, Low-Power, Serial 8-Bit ADCs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.