19-1258; Rev 2; 11/98 L MANUA ION KIT T A U L EVA BLE AVAILA 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier ____________________________Features The MAX3675 is a complete clock-recovery and dataretiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply. The MAX3675 has two differential input amplifiers: one accepts PECL levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signalstrength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A lossof-lock (LOL) monitor is also incorporated as part of the fully integrated PLL. ♦ Single +3.3V or +5.0V Power Supply ________________________Applications _________________Ordering Information ♦ Complies with ANSI, ITU, and Bellcore SDH/SONET Specifications ♦ Low Power: 215mW at +3.3V ♦ Selectable Data Inputs, Differential PECL or Analog ♦ Received-Signal-Strength Indicator (RSSI) ♦ Loss-of-Power and Loss-of-Lock Monitors ♦ Differential PECL Clock and Data Outputs ♦ No External Reference Clock Required SDH/SONET Transmission Systems SDH/SONET Access Nodes Add/Drop Multiplexers ATM Switches PART TEMP. RANGE PIN-PACKAGE MAX3675ECJ MAX3675EHJ MAX3675E/D -40°C to +85°C -40°C to +85°C -40°C to +85°C 32 TQFP 5mm 32 TQFP Dice* *Contact factory for availability. Dice are designed to operate from -40°C to +85°C, but are tested and guaranteed only at Tj = +45°C. Digital Cross-Connects Pin Configuration appears at end of data sheet. ___________________________________________________ Typical Operating Circuit CLOL 0.01µF +3.3V +3.3V +3.3V 52.3Ω 2.2µF 1% 130Ω INSEL LOL FILT PHADJ+ PHADJ- FIL+ FIL- DDI+ VCC SDO+ PHOTODIODE CIN 0.01µF MAX3664 INREF ZO = 50Ω ZO = 50Ω DDISDO- 100pF OUT+ ZO = 50Ω ADI+ IN OUTCOMP ZO = 50Ω +3.3V 82Ω 82Ω MAX3675 +3.3V 100Ω GND 130Ω 0.1µF 0.01µF SCLKO+ ADI- 130Ω CIN 0.01µF 130Ω SCLKOZO = 50Ω VCC 220pF CFILT OLC+ OLC- GND RSSI INV VTH LOP CF 47nF COLC 33nF ZO = 50Ω 82Ω 82Ω R2 R1 100k ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3675 _____________________ General Description MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +6.5V Input Voltage Levels, DDI+, DDI-, ADI+, ADI- ...........................-0.5V to (VCC + 0.5V) Input Differential Voltage (ADI+) - (ADI-)...............................±3V PECL Output Currents, SDO+, SDO-, SCLKO+, SCLKO-...100mA LOL, LOP, INSEL, PHADJ+, PHADJ- .........-0.5V to (VCC + 0.5V) FIL+, FIL-, OLC+, OLC-, RSSI, VTH ...........-0.5V to (VCC + 0.5V) (OLC+) - (OLC-).....................................................................±3V (FIL+) - (FIL-) ..................................................................±700mV CFILT ...............................................(VCC - 2.5V) to (VCC + 0.5V) INV.........................................................................-0.5V to +2.0V Continuous Power Dissipation (TA = +85°C) TQFP (derate 11.1mW/°C above +85°C) .....................721mW Operating Junction Temperature Range ...........-40°C to +150°C Storage Temperature Range .............................-65°C to +160°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 2) PARAMETER Supply Current SYMBOL ICC CONDITIONS MAX3675ECJ, PECL outputs unterminated TYP MAX INSEL = VCC MIN 65 90 INSEL = GND 47 65 UNITS mA PECL Input High Voltage VIH VCC - 1.16 VCC - 0.88 PECL Input Low Voltage VIL VCC - 1.81 VCC - 1.48 V PECL Input High Current IIH -10 10 µA PECL Input Low Current IIL -10 10 µA PECL Output High Voltage VOH VCC - 1.03 VCC - 0.88 V PECL Output Low Voltage VOL VCC - 1.81 VCC - 1.620 V LOP, LOL High Voltage VOH 2.4 LOP Low Voltage VOL LOL Low Voltage VOL ADI+, ADI- Input Bias Voltage 0.4 0.44 VCC - 0.7 ADI+, ADI- open RSSI Output Voltage V 0.1 CLOL = 0.01µF VCC - 0.6 V V VCC - 0.5 V V 1.22 (ADI+) - (ADI-) = 20mVp-p 2.00 2.12 2.30 (ADI+) - (ADI-) = 80mVp-p 2.38 2.51 2.70 Op-Amp Input Bias Current 1MΩ between INV and VTH -100 INV Input Bias Voltage 1MΩ between INV and VTH 1.10 1.18 Note 1: Dice are tested at Tj = +45°C, VCC = +4.25V Note 2: At TA = -40°C, DC characteristics are guaranteed by design and characterization. 2 V _______________________________________________________________________________________ +100 nA 1.30 V 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier (VCC = +3.0V to +5.5V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = +3.3V and TA = +25°C.) (Notes 3, 4) SYMBOL CONDITIONS MIN Differential Input Voltage Range PARAMETER VID BER < 10-10, ADI inputs (Note 5) 0.003 Input Referred Noise VN ADI inputs Power-Detect Hysteresis Limiting Amplifier Small-Signal Bandwidth RSSI Output Voltage Threshold Voltage VTH MAX UNITS 1.2000 Vp-p 100 VRELEASE = 3.6mVp-p (Note 6) BW TYP 2 3 (Note 7) 800 (ADI+) - (ADI-) = 2mVp-p 1.36 (ADI+) - (ADI-) = 20mVp-p 1.93 µV 5 dB MHz V VRELEASE = 3.6mVp-p 1.40 V RSSI Linearity (ADI+) - (ADI-) = 2mVp-p to 50mVp-p ±0.7 % RSSI Slope (ADI+) - (ADI-) = 2mVp-p to 50mVp-p (Note 8) 29 mV/dB CF = 2.2µF, RF = 52.3Ω 350 kHz CF = 0.022µF, RF = 523Ω 3.5 MHz CF = 2.2µF, RF = 52.3Ω 13 CF = 0.022µF,CRFF==0.022µF 523Ω 6 Loop Bandwidth Jitter Generation (Note 9) Jitter-Transfer Peaking RF = 52.3Ω, CF = 2.2µF Jitter Tolerance (Note 9) RF = 52.3Ω, CF = 2.2µF 0.08 f = 10kHz 1.50 3.35 f = 250kHz 0.25 0.60 f = 1MHz 0.20 0.50 UI 1000 Serial Clock-to-Q Delay tCLK-Q Serial Clock Frequency fSCLK dB 8 f = 25kHz Maximum Consecutive Input Run Length (1 or 0) Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: mUI 195 275 622.08 Bits 370 ps MHz AC parameters are guaranteed by design and characterization. The MAX3675 is characterized with a PRBS of 223 - 1 maintaining a BER of ≤ 10-10 having a confidence level of 99.9%. A lower minimum input voltage of 2mVp-p is achievable; however, the LOP hysteresis is not guaranteed below 3.6mVp-p. Hysteresis = 20log(VRELEASE / VASSERT) Small-signal bandwidth cannot be measured directly. RSSI slope = [VRSSI2 - VRSSI1] / [20log (VID2 / VID1)] 1UI = 1 unit interval = (622.08MHz)-1 = 1.608ns _______________________________________________________________________________________ 3 MAX3675 AC ELECTRICAL CHARACTERISTICS __________________________________________Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 223 -1 PATTERN 223 -1 PATTERN VCC = +3.3V 10-3 10-4 BIT ERROR RATE VCC = +3.3V RF = 520Ω CF = 0.022µF DATA 10-2 MAX3675 TOC02 RF = 520Ω CF = 0.022µF MAX3675 TOC01 223 -1 PATTERN VCC = +3.3V BIT ERROR RATE vs. INPUT VOLTAGE RECOVERED CLOCK JITTER MAX3675 TOC03 RECOVERED DATA AND CLOCK (SINGLE ENDED) 10-5 10-6 10-7 10-8 CLOCK RMS∆ = 12.8ps 10-9 10-10 600µ 700µ 800µ 900µ 380ps/div 20ps/div JITTER FREQUENCY (Hz) JITTER FREQUENCY (Hz) JITTER TRANSFER (dB) 1 BELLCORE MASK 0.1 10k 100k JITTER FREQUENCY (Hz) 4 1M 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 BELLCORE MASK MAX3675 TOC05 JITTER TRANSFER MAX3675 TOC04 223 -1 PATTERN VCC = +3.3V RF = 52.3Ω CF = 2.2µF 1m 1.1m 1.2m 1.3m INPUT VOLTAGE (Vp-p) JITTER TOLERANCE 10 INPUT JITTER (UIp-p) MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier 223 -1 PATTERN VCC = +3.3V RF = 52.3Ω CF = 2.2µF 2k 10k 100k 700k JITTER FREQUENCY (Hz) _______________________________________________________________________________________ 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier 2.6 223 -1 PATTERN 2.4 RSSI (V) 3.2 3.0 2.8 ANALOG INPUT VOLTAGE (Vp-p) VCC = +3.3V 3.4 100m MAX3675 TOC07 223 -1 PATTERN VCC = +3.3V OR +5.0V 3.6 2.2 2.0 1.8 1010 PATTERN 2.6 1.6 2.4 223 -1 PATTERN VCC = +3.3V LOP ASSERT LOP RELEASE 10m 1.4 2.2 1m 1.2 2.0 0 20 40 60 100µ 80 1m 10m 100m 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 1 DETECTOR THRESHOLD VOLTAGE, VTH (V) INPUT VOLTAGE (Vp-p) AMBIENT TEMPERATURE (°C) RECEIVED-SIGNAL-STRENGTH INDICATOR vs. INPUT VOLTAGE 223 -1 PATTERN 2.6 VCC = 5.0V 2.4 90 2.2 2.0 1.8 VCC = 3.3V 1.6 MAX3675 TOC10 2.8 SUPPLY CURRENT vs. TEMPERATURE 80 SUPPLY CURRENT (mA) -20 MAX3675 TOC09 -40 RSSI (V) HYSTERESIS (dB) 2.8 MAS3675 TOC06 4.0 3.8 LOSS-OF-POWER ASSERT AND RELEASE LEVEL vs. THRESHOLD VOLTAGE RECEIVED-SIGNAL-STRENTH INDICATOR vs. INPUT VOLTAGE MAX4108/9-08 LOSS-OF-POWER HYSTERESIS vs. TEMPERATURE VCC = 5.0V 70 60 VCC = 3.3V 50 40 1.4 1.2 30 100µ 1m 10m 100m INPUT VOLTAGE (Vp-p) 1 -40 -20 0 20 40 60 80 AMBIENT TEMPERATURE (°C) _______________________________________________________________________________________ 5 MAX3675 ____________________________Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier ______________________________________________________________Pin Description 6 PIN NAME FUNCTION 1 OLC+ Positive Offset-Correction Loop Capacitor Input 2 OLC- Negative Offset-Correction Loop Capacitor Input 3 RSSI Received-Signal-Strength Indicator Output 4, 8, 16, 24, 25 GND Supply Ground 5 INV Op-Amp Inverting Input. Attach to ground if op amp is not used. 6 VTH Voltage Threshold Input. Threshold voltage for loss-of-power monitor. Attach to VCC if LOP function is not used. 7 LOP Loss-of-Power Output, TTL. Limiting amplifier loss-of-power monitor. Asserts high when input signal is below threshold set by VTH. 9, 12, 15, 18, 21, 31 VCC Positive Supply Voltage 10 SCLKO- Negative Serial Clock Output, PECL, 622.08MHz. SDO- is clocked out on the falling edge of SCLKO-. 11 SCLKO+ Positive Serial Clock Output, PECL, 622.08MHz. SDO+ is clocked out on the rising edge of SCLKO+. 13 SDO- Negative Serial Data Output, PECL, 622.08Mbps 14 SDO+ Positive Serial Data Output, PECL, 622.08Mbps 17 LOL 19 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used. 20 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Attach to VCC if not used. 22 FIL- Negative Filter Input. PLL loop filter connection. 23 FIL+ Positive Filter Input. PLL loop filter connection. 26 DDI+ Positive Digital Data Input, PECL, 622.08Mbps serial-data stream 27 DDI- Negative Digital Data Input, PECL, 622.08Mbps serial-data stream 28 INSEL 29 ADI- Negative Analog Data Input, 622.08Mbps serial-data stream 30 ADI+ Positive Analog Data Input, 622.08Mbps serial-data stream 32 CFILT RSSI Filter Capacitor Input Loss-of-Lock Output, TTL. PLL loss-of-lock monitor, active low (see Design Procedure). Input Select. Connect to GND to select digital data inputs or VCC for analog data inputs. _______________________________________________________________________________________ 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier MAX3675 PHADJ+ PHADJ- LOL FIL+ FIL- VCC 6k SDO+ D Q SDOPECL DDI+ SCLKO+ I DDI- Σ PHASE/FREQ DETECTOR PECL VCO FILTER PECL SCLKO- Q INSEL 622.08MHz VCC ADIADI+ LIMITER 42dB BIAS 1.18V 6k POWER DETECT OFFSET CORRECTION OLC+ OLC- MAX3675 CFILT RSSI INV VTH LOP Figure 1. Functional Diagram _______________Detailed Description The block diagram in Figure 1 shows the MAX3675’s architecture. It consists of a limiting amplifier input stage followed by a fully integrated clock/data-recovery (CDR) block implemented with a phase-locked loop (PLL). The input stage is selectable between a limiting amplifier or a simple PECL input buffer. The limiting amplifier provides a loss-of-power (LOP) monitor and a received-signal-strength indicator (RSSI). The PLL consists of a phase/frequency detector (PFD), a loop filter amplifier, and a voltage-controlled oscillator (VCO). Limiting Amplifier The MAX3675’s on-chip limiting amplifier accepts an input signal level from 3.0mVp-p to 1.2Vp-p. The amplifier consists of a cascade of gain stages that include full-wave logarithmic detectors. The combined smallsignal gain is approximately 42dB, and the -3dB bandwidth is 800MHz. Input-referred noise is less than 100µV RMS, providing excellent sensitivity for smallamplitude data streams. In addition to driving the CDR, the limiting amplifier provides both an RSSI output and an LOP monitor that allow the user to program the threshold voltage. The RSSI circuitry provides an output voltage that is linearly proportional to the input power (in decibels) detected between the ADI+ and ADI- input pins and is sensitive enough to reliably detect signals as small as 2mVp-p. Input DC offset reduces the accuracy of the power detector; therefore, an integrated feedback loop is included that automatically nulls the input offset of the gain stage. The addition of this offset-correction loop requires that the input signal be AC coupled when using the ADI+ and ADI- inputs. Finally, for applications that do not require the limiting amplifier, selecting the digital inputs conserves power by turning off the post-amplifier block. _______________________________________________________________________________________ 7 MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Phase Detector The phase detector produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the incoming data. The external phase adjustment pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment. Frequency Detector A frequency detector incorporated into the PLL aids frequency acquisition during start-up conditions. The input data stream is sampled by quadrature components of the VCO clock, generating a difference frequency. Depending on the polarity of the difference frequency, the PFD drives the VCO so that the difference frequency is reduced to zero. Once frequency acquisition is obtained, the frequency detector returns to a neutral state. Loop Filter and VCO The VCO is fully integrated, while the loop filter requires an external R-C network. This filter network determines the bandwidth and peaking of the second-order PLL. __________________Design Procedure Received-Signal-Strength Indicator (RSSI) The RSSI output voltage is insensitive to temperature and supply fluctuations. The power detector functions as a broadband power meter that detects the total RMS power of all signals within the detector bandwidth (including input signal noise). The RSSI voltage varies linearly (in decibels) for inputs of 2mVp-p to 50mVp-p. The slope over this input range is approximately 29mV/dB. The high-speed RSSI signal is filtered to an RMS level with one external capacitor tied from CFILT to VCC. The impedance looking into CFILT is about 500Ω to VCC. As a result, the lower -3dB cutoff frequency is set by the following simple relationship: [ ( ) ] fFILT = 1 / 2π 500 CF For 622Mbps applications, Maxim recommends a cutoff frequency of 6.8kHz, which requires CF = 47nF. The RSSI output is designed to drive a minimum load resistance of 10kΩ to ground and a maximum of 20pF. Loads greater than 20pF must be buffered by a series resistance of 10kΩ (i.e., voltmeter). into the MAX3675 to remove the input offset. DC coupling to the ADI+ and ADI- inputs is not allowed, as this would prevent the proper functioning of the DC offsetcorrection circuitry. The differential input impedance (ZIN) is approximately 2.5kΩ. The impedance between OLC+ and OLC- (ZOLC) is approximately 120kΩ. Take care when setting the combined low-frequency cutoff (fCUTOFF), due to the input DC-blocking capacitor (CIN) and the offset correction loop capacitor (COLC). Refer to Table 1 for selecting the values of CIN and COLC. These values ensure that the poles associated with CIN and COLC work together to provide a flat response at the lower -3dB corner frequency (no gain peaking). CIN must be a low-TC, high-quality capacitor of type X7R or better in order to minimize fCUTOFF deviations. COLC must be a capacitor of type Z5U or better. Loss-of-Power (LOP) Monitor A LOP monitor with a user-programmable threshold and a hysteresis comparator is also included with the limiting amplifier circuitry. Internally, one comparator input is tied to the RSSI output signal, and the other is tied to the threshold voltage (VTH), which is set externally and provides a trip point for the LOP indication. A low-voltage, low-drift op amp, referenced to an internal bandgap voltage (1.18V), is supplied for programming a supply-independent threshold voltage. This op amp requires two external resistors to program the LOP trip point. VTH is programmable from 1.18V to 2.4V using the equation: ( ) VTH = 1.18 1 + R2 / R1 The op amp can source only 20µA of current. Therefore, an R1 value greater than or equal to 100kΩ is recommended for proper operation. The input bias Table 1. Setting the Low-Frequency Cutoff CIN COLC COMBINED LOW fCUTOFF (kHz) 0.022µF 0.047µF 3.0 0.010µF 0.033µF 6.8 6800pF 0.022µF 10 4700pF 0.010µF 13.5 2200pF 4700pF 29 1000pF 3300pF 68 Input Offset Correction 470pF 1000pF 135 The on-chip limiting amplifier provides more than 42dB of gain. A low-frequency feedback loop is integrated 330pF 680pF 190 220pF 470pF 290 8 _______________________________________________________________________________________ 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Setting the Loop Filter The loop filter within the PLL consists of a transconductance amplifier and external filter elements RF and CF (Figure 2). The closed-loop bandwidth of a PLL is approximated by: KD KO Gm RF where KD is the gain of the phase detector, KO is the gain of the VCO, and Gm is the transconductance of F(S) GM ) where the recommended external value of CF is 2.2µF. Increasing the value of RF increases the PLL bandwidth (fLOOP). Increasing this bandwidth improves jitter tolerance and jitter-generation performance, but also reduces jitter-transfer performance. (Decreasing the bandwidth has the opposite effect.) This type of PLL is a classical second-order system. Therefore, as fz (the frequency of the zero) approaches fLOOP, the jitter-transfer peaking increases. For an overdamped system (fz/fLOOP) < 0.25, the jitter peaking of a second-order system can be approximated by: FIL- RF MAX3675-B CF ( Mp = 1 - (fz / fLOOP) where Mp is the magnitude of the peaking. For (fz/fLOOP) < 0.1, this equation holds to within 10%. CF can be made smaller if meeting the jitter-transfer specifications is not a requirement. For example, setting RF to 300Ω and CF to 3.3nF increases the loop bandwidth to approximately 2.2MHz (Figure 3). Loop stability is ensured by maintaining a separation of 10x between fLOOP and fz. Be careful when changing the value of RF. Lower values of RF are limited by the internal resistance of the IC, and upper values are limited by the internal high-frequency pole. MAX3675 FIL+ the filter amplifier. For the MAX3675, an estimated value of KDKOGm is 7k. Because the PLL is a second-order system, a zero in the open-loop gain is required for stability. This zero is set by the following equation: ω z = 1 / RFCF [( ) ] s CF s/ω P + 1 fZ = 161kHz f = 2.2MHz CF = 3.3nF RLOOP F = 300Ω 1 R FC F ωz = RF = 52.3Ω CF = 2.2µF ωP = internal higher - order pole Figure 2. Loop Filter HIGHERORDER POLE >10x GAIN F(s) = s + 1 Gm ω z fZ = 1.38kHz CF = 2.2µF fLOOP = 375kHz RF = 52.3Ω fLOOP = KSKOGmRF 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 3. Loop-Filter Response _______________________________________________________________________________________ 9 MAX3675 current of the op amp at the INV pin is guaranteed to be less than ±100nA. To set the threshold voltage externally (i.e., via a DAC control), completely disable the op amp by grounding the inverting terminal (INV). VTH then becomes high impedance and must be driven externally. The comparator is configured with an active-high LOP output. An on-chip, 6kΩ pull-up resistor is provided to reduce external part count. The MAX3675 is optimally designed to acquire lock and to provide a bit-error rate (BER) of less than 10-10 for long strings of consecutive zeros and ones. Using the recommended external component values of RF = 52.3Ω ±1% and CF = 2.2µF ±20%, measured results show that the MAX3675 can tolerate 1000 consecutive ones or zeros. It is important to select a type of capacitor for CF that has a temperature stability of ±10% or better. This ensures performance over the -40°C to +85°C temperature range. Lock Detect The MAX3675’s loss-of-lock (LOL) monitor indicates when the PLL is locked. Under normal operation, the loop is locked and the LOL output signal is high. When the MAX3675 loses lock, a fast negative-edge transition occurs on LOL. The output level remains at a low level (held by C LOL ) until the loop reacquires lock (Figure 4). Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3675. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal. See the Loss-of-Power (LOP) Monitor section for this type of indicator. Input and Output Terminations The MAX3675 digital data and clock I/Os (DDI+, DDI-, SDO+, SDO-, SCLK+, and SCLK-) are designed to interface with PECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50Ω to VCC - 2V should be used with fixed-impedance transmission lines for proper termination. Make sure that the differential outputs have balanced loads. The digital data input signals (DDI+ and DDI-) are differential inputs to an emitter-coupled pair. As a result, the MAX3675 can accept differential input signals as low as 250mV. These inputs can also be driven singleended by externally biasing DDI- to the center of the voltage swing. The MAX3675’s performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to V CC as possible. Take care to isolate the input from the output signals to reduce feedthrough. __________Applications Information Driving the Limiting Amplifier Single-Ended There are three important requirements for driving the limiting amplifier from a single-ended source (Figure 5): 1) There must be no DC coupling to the ADI+ and ADIinputs. DC levels at these inputs disrupt the offset-correction loop. 2) The terminating resistor RT (50Ω) must be referenced to the ADI- input to minimize common-mode coupling problems. 3) The low-frequency cutoff for the limiting amplifier is determined by either C IN and the 2.5kΩ input impedance or Cb/2 together with RT. With Cb = 0.22µF and RT = 50Ω, the low-frequency cutoff is 29kHz. LOP OUTPUT LEVEL MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Cb 0.22µF CIN 5.6nF MAX3675 ADI+ RT 50Ω LOL 2.5k ADI- NO DATA ACQUIRE LOCKED Cb 0.22µF TIME Figure 4. Loss-of-Lock Output 10 Figure 5. Single-Ended Input Termination ______________________________________________________________________________________ 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier The limiting amplifier is biased independently from the clock recovery circuitry. Grounding INSEL turns off the limiting amplifier and selects the PECL DDI inputs. Converting Average Optical Power to Signal Amplitude Many of the MAX3675’s specifications relate to inputsignal amplitude. When working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. The relations given in Table 2 and Figure 6 are helpful for converting optical power to input signal when designing with the MAX3675. In an optical receiver, the input voltage to the limiting amplifier can be found by multiplying the relationship in Table 2 by the photodiode responsivity and transimpedance amplifier gain. In an optical receiver, the dB change at the MAX3675 always equals 2x the optical dB change. The MAX3675’s typical voltage hysteresis is 3.0dB. This provides an optical hysteresis of 1.5dB. Jitter in Optical Receivers Timing jitter, edge speeds, aberrations, optical dispersion, and attenuation all impact the performance of high-speed clock recovery for SDH/SONET receivers (Figure 7). These effects decrease the time available for error-free data recovery by reducing the received “eye opening” of non-return-to-zero (NRZ) transmitted signals. P1 Optical Hysteresis Power and hysteresis are often expressed in decibels. By definition, decibels are always 10log (power). At the inputs to the MAX3675 limiting amplifier, the power is VIN2/R. If a receiver’s optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage at the input to the MAX3675 also increases by a factor of two. The optical power increase is 10log(2x / x) = 10log(2) = +3dB. At the MAX3675, the voltage increase is: 10log (2VIN ) 2 /R 2 VIN / R P0 TIME Figure 6. Optical Power Relations = 10log(22 ) = 20log(2) = + 6dB SYMBOL AMPLITUDE Table 2. Optical-Power Relations* RELATION MIDPOINT PAVE = (P0 + P1) / 2 Average Power PAVE Extinction Ratio re re = P1 / P0 Optical Power of a “1” P1 P1 = 2PAVE Optical Power of a “0” P0 P0 = 2PAVE / re + 1 Signal Amplitude PIN PIN = P1 − P0 = 2PAVE EYE DIAGRAM WITH NO TIMING JITTER re re + 1 ( *Assuming a 50% average input data duty cycle. AMPLITUDE PARAMETER PAVE ) (re − 1) re + 1 TIME MIDPOINT EFFECTS OF TIMING JITTER ON EYE DIAGRAM TIME Figure 7. Eye Diagram With and Without Timing Jitter ______________________________________________________________________________________ 11 MAX3675 Reduced Power Consumption Without the Limiting Amplifier Optical receivers, incorporating transimpedance preamplifiers and limiting postamplifiers, can significantly clean up the effects of dispersion and attenuation. In addition, these amplifiers can provide fast transitions with minimal aberrations to the subsequent clock and data-recovery (CDR) blocks. However, these stages also add distortions to the midpoint crossing, contributing to timing jitter. Timing jitter is one of the most critical technical issues to consider when developing optical receivers and CDR circuits. A better understanding of the different sources of jitter helps in the design and application of optical receiver modules and integrated CDR solutions. SDH/SONET specifications are well defined regarding the amount of jitter tolerance allowed at the inputs of optical receivers, as well as jitter peaking requirements, but they do little to define the different sources of jitter. The jitter that must be tolerated at an optical receiver input involves three significant sources, all of which are present in varying degrees in typical receiver systems: 1) Random jitter (RJ) 2) Pattern-dependent jitter (PDJ) 3) Pulse-width distortion (PWD) Random Jitter (RJ) RJ is caused by random noise present during edge transitions (Figure 8). This random noise results in random midpoint crossings. All electrical systems generate some random noise; however, the faster the speed of the transitions, the lower the effect of noise on random jitter. The following equation is a simple worstcase estimation of random jitter: RJ (rms) = (rms noise) / (slew rate) Pattern-Dependent Jitter (PDJ) PDJ results from wide variations in the number of consecutive bits contained in NRZ data streams working against the bandwidth requirements of the receiver (Figure 9). The location of the lower -3dB cutoff frequency is important, and must be set to pass the low frequencies associated with long consecutive bit streams. AC coupling is common in optical receiver design. When using a limiting preamplifier with a highpass frequency response, select the input AC-coupling capacitor, C IN, to provide a low-frequency cutoff (fC) one decade lower than the preamplifier low-frequency cutoff. As a result, the PDJ is dominated by the lowfrequency cutoff of the preamplifier. When using a preamplifier without a highpass response with the MAX3675, the following equation provides a good starting point for choosing CIN: -tL CIN ≥ PDJ BW 1.25kΩ In 1− 0.5 ( ) ( )( ) where tL = duration of the longest run of consecutive bits of the same value (seconds); PDJ = maximum DESIRED MIDPOINT CROSSING LF DROOP 0-1-0 BIT STREAM MIDPOINT 0–1 TRANSITION WITH RANDOM NOISE RANDOM JITTER MIDPOINT LONG CONSECUTIVE BIT STREAM AMPLITUDE ACTUAL MIDPOINT CROSSING MIDPOINT AMPLITUDE MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier LF PDJ TIME TIME Figure 8. Random Jitter on Edge Transition 12 Figure 9. Pattern-Dependent Jitter Due to Low-Frequency Cutoff ______________________________________________________________________________________ 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier Pulse-Width Distortion (PWD) same level (Figure 11). DC offsets and nonsymmetrical rising and falling edge speeds both contribute to PWD. For a 1–0 bit stream, calculate PWD as follows: PWD = [(width of wider pulse) (width of narrower pulse)] / 2 Phase Adjust The internal clock and data alignment in the MAX3675 is well maintained close to the center of the data eye. Although not required, this sampling point can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input signals to approximately ±1V. A simple resistor divider with a bypass capacitor is sufficient to set up these levels. When the PHADJ inputs are not used, they should be tied directly to VCC. Finally, PWD occurs when the midpoint crossing of a 0–1 transition and a 1–0 transition do not occur at the AMPLITUDE 0-1-0 BIT STREAM MIDPOINT AMPLITUDE LONG CONSECUTIVE BIT STREAM PWD RESULTS WHEN THE WIDTH OF A ZERO DOES NOT EQUAL THE WIDTH OF A ONE MIDPOINT tFALL ≠ tRISE WIDTH OF A ZERO HF PDJ TIME Figure 10. Pattern-Dependent Jitter Due to High-Frequency Rolloff WIDTH OF A ONE TIME Figure 11. Pulse-Width Distortion ______________________________________________________________________________________ 13 MAX3675 allowable pattern-dependent jitter, peak-to-peak (seconds); and BW = typical system bandwidth, normally 0.6 to 1.0 times the data rate (Hertz). If the PDJ is still larger than desired, continue increasing the value of C IN . Note that to maintain stability when using the MAX3675 analog inputs (ADI+, ADI-), it is important to keep the low-frequency cutoff associated with COLC below the corner frequency associated with C IN (fC) (Table 1). PDJ can also be present due to insufficient high-frequency bandwidth (Figure 10). If the amplifiers are not fast enough to allow for complete transitions during single-bit patterns, or if the amplifier does not allow adequate settling time, high-frequency PDJ can result. __________________Pin Configuration 17 LOL 18 VCC 19 PHADJ- 20 PHADJ+ 21 VCC 22 FIL- 23 FIL+ 24 GND GND 25 16 GND DDI+ 26 15 VCC DDI- 27 14 SDO+ MAX3675 INSEL 28 13 SDO- ADI- 29 GND DDI+ VCC LOL PHADJ- GND FIL- PHADJ+ VCC GND FIL- PHADJ+ VCC VCC FIL+ PHADJ- GND LOL VCC DDI- SDO+ INSEL SDO- 0.069" (1.753mm) 12 VCC ADI- VCC 30 11 SCLKO+ ADI+ VCC 31 10 SCLKO- SCLKO+ SCLKO- ADI+ CFILT 32 VCC VCC VCC CFILT GND 8 7 LOP 6 VTH 4 5 INV GND 3 RSSI 2 OLC- 1 9 TQFP 14 ___________________Chip Topography FIL+ TOP VIEW OLC+ MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier OLC+ RSSI OLC- INV GND VTH LOP GND 0.068" (1.727mm) ______________________________________________________________________________________ 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier 32TQFP.EPS ______________________________________________________________________________________ 15 MAX3675 ________________________________________________________Package Information MAX3675 622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.