fax id: 1072 CY62128 128K x 8 Static RAM Features • 4.5V − 5.5V operation • CMOS for optimum speed/power • Low active power (70 ns, LL version) — 330 mW (max.) (60 mA) • Low standby power (70 ns, LL version) — 110 µW (max.) (20 µA) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1, CE2, and OE options Functional Description The CY62128 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE 1), an active HIGH chip enable (CE2), an active LOW output enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking chip enable one (CE1) and write enable (WE) inputs LOW and chip enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking chip enable one (CE1) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE 2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY62128 is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages. Logic Block Diagram Pin Configurations Top View SOIC NC A16 A14 A12 I/O0 INPUTBUFFER I/O1 512x 256x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 COLUMN DECODER CE1 CE2 WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O6 POWER DOWN A9 A10 A11 A12 A13 A14 A15 A16 I/O7 OE A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CE2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 62128-1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TSOP I Reverse Pinout Top View (not to scale) A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE1 A10 OE A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I/ STSOP Top View (not to scale) 62128-2 Cypress Semiconductor Corporation • 3901 North First Street 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 62128-2 • San Jose • CA 95134 • 408-943-2600 July 1996 - Revised June 18, 1998 CY62128 Selection Guide CY62128-55 CY62128-70 55 70 L 50 40 LL 50 40 L 80 80 LL 15 15 Maximum Access Time (ns) Maximum Operating Current Commercial Maximum CMOS Standby Current Commercial Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State ....................................–0.5V to VCC + 0.5V Commercial Industrial DC Input Voltage.................................–0.5V to VCC + 0.5V Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 2 Ambient Temperature VCC 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% CY62128 Electrical Characteristics Over the Operating Range 62128–55 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current IOZ Output Leakage Current IOS Output Short Circuit Current VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Min. ISB2 Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs Min. Typ Max. 2.4 Unit V 0.4 V 2.2 VCC + 0.3 2.2 VCC + 0.3 V –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 µA +1 +1 +1 +1 µA –300 mA –300 Com’l Max. VCC, CE1 ≥ VCC – 0.3V, or CE2 ≤ 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f=0 Max. 0.4 GND ≤ VI ≤ VCC GND ≤ VI ≤ VCC, Output Disabled Max. VCC, CE1 ≥ VIH or CE2 < VIL, VIN ≥ VIH or VIN ≤ VIL, f = fMAX 62128–70 2.4 40 115 40 110 mA L 30 70 30 60 mA LL 30 70 30 60 mA 40 115 40 110 mA L 30 70 30 70 mA LL 30 70 30 70 mA 0.3 25 0.3 1 mA L 0.15 3 0.15 1 mA LL 0.1 2 0.1 1 mA 0.3 25 0.3 1 mA L 0.15 3 0.15 1 mA LL 0.1 2 0.1 1 mA 500 µA 100 µA 20 µA 500 µA Ind.’l ISB1 Typ Com’l Ind.’l Com’l 500 L 0.4 LL 0.4 100 20 Ind 500 L LL 0.4 0.4 100 40 100 µA 40 µA Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 9 pF 9 pF Notes: 3. Typical values are included for reference only and are not tested or guaranteed. Typical values are an average of the distribution across normal production variations as measured at VCC = 5.0V, TA = 25°C, and tAA=70ns 4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. 3 CY62128 AC Test Loads and Waveforms R1 1800 Ω R1 1800 Ω 5V ALL INPUT PULSES 3.0V 5V OUTPUT 90% OUTPUT R2 990 Ω 100 pF R2 990 Ω 5 pF INCLUDING JIG AND SCOPE (a) INCLUDING JIG AND SCOPE (b) 90% 10% GND 10% ≤ 5ns ≤ 5 ns 62128-3 62128-4 Equivalent to: THÉVENIN EQUIVALENT 639 Ω 1.77V OUTPUT Switching Characteristics Over the Operating Range 62128–55 Parameter Description Min. Max. 62128–70 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW to Data Valid, CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 20 35 ns tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[7,8] tLZCE 55 55 5 CE1 LOW to Low Z, CE2 HIGH to Low Z 70 5 [7,8] CE1 HIGH to High Z, CE2 LOW to High Z tPU CE1 LOW to Power-Up, CE2 HIGH to Power-Up tPD CE1 HIGH to Power-Down, CE2 LOW to Power-Down ns 25 5 20 0 ns ns 25 0 55 ns ns 0 20  ns 5 0 tHZCE WRITE CYCLE 70 ns ns 70 ns  tWC Write Cycle Time 55 70 ns tSCE CE1 LOW to Write End, CE2 HIGH to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns 5 5 ns tLZWE tHZWE  WE HIGH to Low Z WE LOW to High Z [7, 8] 20 25 ns Notes: 6. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100pF load capacitance. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 4 CY62128 Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only) Parameter Conditions Description VDR VCC for Data Retention ICCDR Data Retention Current Coml. Min. Typ. L Indl. L Unit V VCC=VDR=3.0V, CE ≥VCC – 0.3V, VIN ≥ VCC – 0.3V or, VIN ≤ 0.3V LL 0.4 LL tCDR tR Max. 2.0 100 µA 20 µA 100 µA 20 µA Chip Deselect to Data Retention Time 0 ns Operation Recovery Time tRC ns Switching Waveforms Read Cycle No.1[11,12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 62128-5 [12,13] Read Cycle No. 2 (OE Controlled) ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE DATA OUT tHZCE tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB 62128-6 Notes: 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 5 CY62128 Switching Waveforms (continued) Write Cycle No. 1 (CE1 or CE2 Controlled)[14,15] tWC ADDRESS tSCE CE1 tSA CE2 tSCE tHA tAW tPWE WE tSD DATA I/O tHD DATA VALID 62128-7 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14,15] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE 62128-8 Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. 6 CY62128 Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW)[14,15] tWC ADDRESS tSCE CE1 CE2 tSCE tAW tSA tHA tPWE WE tSD NOTE 16 DATAI/O tHD DATA VALID tLZWE tHZWE 62128-9 Truth Table CE1 CE2 OE WE I/O 0 – I/O7 Mode Power H X X X High Z Power-Down Standby (ISB) X L X X High Z Power-Down Standby (ISB) L H L H Data Out Read Active (ICC) L H X L Data In Write Active (ICC) L H H H High Z Selected, Outputs Disabled Active (ICC) 7 CY62128 Ordering Information Speed (ns) 55 70 Ordering Code Package Name Package Type CY62128–55SC S34 32-Lead 450-Mil SOIC CY62128-55ZC Z32 32-Lead TSOP Type I CY62128−55ZAC ZA32 32-Lead STSOP Type I CY62128–70SC S34 32-Lead 450-Mil SOIC 32-Lead TSOP Type I CY62128−70ZC Z32 CY62128-70ZAC ZA32 CY62128-70ZRC ZR32 CY62128–70SI Commercial Commercial 32-Lead STSOP Type I 32-Lead Reverse TSOP Type I S34 32-Lead 450-Mil SOIC 32-Lead TSOP Type I CY62128−70ZI Z32 CY62128-70ZAI ZA32 CY62128-70ZRI ZR32 CY62128L−70SC S34 32-Lead 450-Mil SOIC CY62128L−70ZC Z32 32-Lead TSOP Type I CY62128L-70ZAC ZA32 CY62128L-70ZRC ZR32 CY62128L−70SI Operating Range Industrial 32-Lead STSOP Type I 32-Lead Reverse TSOP Type I Commercial 32-Lead STSOP Type I 32-Lead Reverse TSOP Type I S34 32-Lead 450-Mil SOIC CY62128L−70ZI Z32 32-Lead TSOP Type I CY62128L-70ZAI ZA32 CY62128L-70ZRI ZR32 CY62128LL−70SC S34 32-Lead 450-Mil SOIC CY62128LL−70ZC Z32 32-Lead TSOP Type I CY62128LL-70ZAC ZA32 CY62128LL-70ZRC ZR32 Industrial 32-Lead STSOP Type I 32-Lead Reverse TSOP Type I Commercial 32-Lead STSOP Type I 32-Lead Reverse TSOP Type I CY62128LL−70SI Z32 32-Lead 450-Mil Type I CY62128LL-70ZI Z32 32-Lead TSOP Type I CY62128LL-70ZAI Z32 32-Lead STSOP Type I CY62128LL-70ZRI ZR32 32-Lead Reverse TSOP Type I Document #: 38–00524–B 8 Industrial CY62128 Package Diagrams 32-Lead (450 MIL) Molded SOIC S34 51-85081-A 32-Lead Thin Small Outline Package Z32 51-85056-B 9 CY62128 Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package ZA32 51-85094 32-Lead Reverse Thin Small Outline Package ZR32 51-85089-A © Cypress Semiconductor Corporation, 1998. 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