19-1627; Rev 2; 6/03 DBS Direct Downconverter Advantages Over MAX2104 ♦ Improved Front End Achieves 10.2dB NF at 1550MHz The IC includes a low-noise amplifier (LNA) with gain control, I and Q downconverting mixers, lowpass filters with gain and frequency control, a local oscillator (LO) buffer with a 90° quadrature network, and a chargepump-based phase-locked loop (PLL) for frequency control. The MAX2106 has an on-chip LO, requiring only an external varactor-tuned LC tank for operation. The LO’s output drives the internal quadrature generator and has a buffer amplifier to drive off-chip circuitry. The MAX2106 comes in a 48-pin thin quad flat-pack package with exposed paddle (EP). Applications ♦ Higher Input IIP3: 11.5dBm at 1550MHz ♦ Reduced Spurious Downconversion Products ♦ Capable of Using an External Synthesizer Features ♦ Drop-In Replacement for MAX2104 Designs: Requires Only Minor Software Upgrade and Two External Resistor Value Changes ♦ Complete Low-Cost Solution for DBS Direct Downconversion ♦ High Level of Integration Minimizes Component Count ♦ 1MBaud to 45MBaud Operation ♦ Selectable LO Buffer ♦ +5V Single-Supply Operation ♦ 925MHz to 2175MHz Input Frequency Range U.S. DSS Set-Top Receivers Broadband Systems European DVB-Compliant Systems LMDS Professional Receivers ♦ On-Chip Quadrature Generator, Dual-Modulus Prescaler (/32, /33) Cellular Base Stations VSAT Wireless Local Loop ♦ On-Chip Crystal Oscillator Amplifier Microwave Links ♦ PLL Phase Detector with Gain-Controlled Charge Pump Pin Configuration ♦ Input Levels: -25dBm to -68dBm per Carrier ♦ Over 50dB Gain Control Range ♦ Noise Figure = 10.2dB; IIP3 = +11.5dBm (at 1550MHz) 37 38 39 40 41 42 43 44 45 46 CP FB GND VCC TANK+ VRLO TANKGND GND VCC LOBUF-/TPSOUTLOBUF+/FPSOUT+ 47 48 TOP VIEW ♦ Automatic Baseband Offset Correction VCC 1 36 CFLT 2 35 XTLXTL+ GND 3 34 4 33 VCC 6 RFINRFIN+ GND 7 5 32 31 MAX2106 30 PLLINPLLIN+ MODMOD+ LODIVSEL IOUT+ IOUTVCC QOUT+ PART MAX2106UCM TEMP RANGE 0°C to +85°C PIN-PACKAGE 48 TQFP-EP* *Exposed paddle. Functional Diagram appears at end of data sheet. IDCIDC+ LOBUFSEL GND RFOUT CPG1 VCC XTLOUT CPG2 GC1 GC2 INSEL 24 FLCLK 23 25 22 12 21 QDC+ 20 QOUTRFBAND 19 26 18 27 11 17 10 16 GND QDC- 15 28 14 29 9 13 8 Ordering Information TQFP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2106 General Description The MAX2106 low-cost, direct-conversion tuner IC is designed for use in digital direct-broadcast satellite (DBS) television set-top box units and is a pin-for-pin upgrade for the MAX2104. Its direct-conversion architecture reduces system cost compared to devices with IF-based architectures. The MAX2106 directly tunes Lband signals to baseband using a broadband I/Q downconverter. The operating frequency range spans 925MHz to 2175MHz. MAX2106 DBS Direct Downconverter ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP-EP (derate 27mW/°C above +70°C) ..........1.5W Operating Temperature ..........................................0°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C VCC to GND ..............................................................-0.3V to +7V All Other Pins to GND................................-0.3V to (VCC + 0.3V) RFIN+ to RFIN-, TANK+ to TANK-, IDC+ to IDC-, QDC+ to QDC- .........................................±2V IOUT_, QOUT_ to GND Short-Circuit Duration .......................10s LOBUF+/PSOUT+, LOBUF-/PSOUT- Short-Circuit Duration..10s Continuous Current (any pin other than VCC or GND)........20mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +4.75V to +5.25V, VFB = +2.4V, CIOUT_ = CQOUT_ = 10pF, ƒFLCLK = 2MHz, RFIN_ = unconnected, RIOUT_ = RQOUT_ = 10kΩ, VLOBUFSEL = 0.5V, VRFBAND = VINSEL = VCPG1 = VCPG2 = +2.4V, VPLLIN+ = VMOD+ = +1.3V, VPLLIN- = VMOD- = +1.1V, TA = +25°C, unless otherwise noted. Typical values are at VCC = +5V, unless otherwise noted.) PARAMETER SYMBOL Operating Supply Voltage VCC Operating Supply Current ICC CONDITIONS MIN TYP 4.75 195 MAX UNITS 5.25 V 275 mA STANDARD DIGITAL INPUTS (INSEL, CPG1, CPG2, LOBUFSEL, LODIVSEL) Input Voltage High VIH Input Voltage Low VIL Input Current IIN 2.4 RFBAND Input Current V 0.5 V -15 10 µA -200 200 µA SLEW-RATE-LIMITED DIGITAL INPUT (fLCLK) FLCLK Input Voltage High 1.85 V FLCLK Input Voltage Low FLCLK Input Current (Note 1) RSOURCE = 50kΩ, VFLCLK = 1.65V -1 1.45 V 1 µA DIFFERENTIAL DIGITAL INPUTS (MOD+, MOD-, PLLIN+, PLLIN-) Common-Mode Input Voltage VCMI 1.08 Input Voltage Low Referenced to VCMI Input Voltage High Referenced to VCMI 1.2 V mV 100 mV -5 Input Current (Note 1) 1.32 -100 5 µA DIFFERENTIAL DIGITAL OUTPUTS (LOBUF+/PSOUT+, LOBUF-/PSOUT-) Common-Mode Output Voltage VCMO 2.16 2.4 2.64 V -150 mV Output Voltage Low (Note 2) Referenced to VCMO, LOBUFSEL ≤ 0.5V Output Voltage High (Note 2) Referenced to VCMO, LOBUFSEL ≤ 0.5V 150 (VMOD+ - VMOD-) ≥ 200mV, LOBUFSEL ≤ 0.5V 32 32 (VMOD+ - VMOD-) ≤ -200mV, LOBUFSEL ≤ 0.5V 33 33 LOBUFSEL ≥ 2.4V, LODIVSEL ≤ 0.5V 2 2 LOBUFSEL ≥ 2.4V, LODIVSEL ≥ 2.4V 1 1 8 8 mV FREQUENCY SYNTHESIZER/LO BUFFER Prescaler Ratio Reference Divider Ratio XTLOUT Output DC Voltage Charge-Pump Output High Measured at FB 2 1.9 V VCPG1 ≤ 0.5V, VCPG2 ≤ 0.5V 0.08 0.1 0.12 VCPG1 ≤ 0.5V, VCPG2 ≥ 2.4V 0.24 0.3 0.36 VCPG1 ≥ 2.4V, VCPG2 ≤ 0.5V 0.48 0.6 0.72 VCPG1 ≥ 2.4V, VCPG2 ≥ 2.4V 1.44 1.8 2.16 _______________________________________________________________________________________ mA DBS Direct Downconverter (VCC = +4.75V to +5.25V, VFB = +2.4V, CIOUT_ = CQOUT_ = 10pF, ƒFLCLK = 2MHz, RFIN_ = unconnected, RIOUT_ = RQOUT_ = 10kΩ, VLOBUFSEL = 0.5V, VRFBAND = VINSEL = VCPG1 = VCPG2 = +2.4V, VPLLIN+ = VMOD+ = +1.3V, VPLLIN- = VMOD- = +1.1V, TA = +25°C, unless otherwise noted. Typical values are at VCC = +5V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -0.12 -0.36 -0.72 -2.16 -0.1 -0.3 -0.6 -1.8 -0.08 -0.24 -0.48 -1.44 mA Charge-Pump Output Low Measured at FB VCPG1 ≤ 0.5V, VCPG2 ≤ 0.5V VCPG1 ≤ 0.5V, VCPG2 ≥ 2.4V VCPG1 ≥ 2.4V, VCPG2 ≤ 0.5V VCPG1 ≥ 2.4V, VCPG2 ≥ 2.4V Charge-Pump Output Current Matching Positive to Negative Measured at FB -5 5 % Charge-Pump Output Leakage Measured at FB -25 25 nA Charge-Pump Output Current Drive (Note 1) Measured at CP 100 VGC_ = 1V to 4V -50 µA ANALOG CONTROL INPUTS (GC1, GC2) Input Current IGC_ 50 µA BASEBAND OUTPUTS (IOUT+, IOUT-, QOUT+, QOUT-) Differential Output Voltage Swing RL = 2kΩ differential 1 Vp-p Common-Mode Output Voltage (Note 1) 0.65 0.85 V Offset Voltage (Note 1) -50 50 mV AC ELECTRICAL CHARACTERISTICS (IC driven single-ended with RFIN- AC-terminated in 75Ω to GND, VCC = +4.75V to +5.25V, VIOUT_ = VQOUT_ = 0.59Vp-p, CIOUT_ = CQOUT_ = 10pF, ƒLCLK = 2MHz, RIOUT_ = RQOUT_ = 10kΩ, VLOBUFSEL = 0.5V, VRFBAND = VINSEL = VCPG1 = VCPG2 = +2.4V, VPLLIN+ = VMOD+ = +1.3V, VPLLIN- = VMOD- = +1.1V, TA = +25°C, unless otherwise noted. Typical values are at VCC = +5V.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2175 MHz -68 dBm dBm RF FRONT END RFIN_ Input Frequency Range fRFIN_ RFIN_ Input Power for 0.59Vp-p Baseband Levels RFIN_ Input Third-Order Intercept Point (Note 3) Inferred by quadrature gain and phase-error test VGC1 = VGC2 = +4V (min gain) VGC1 = VGC2 = +1V (max gain) fLO = 2175MHz PRFIN_ = -25dBm fLO = 1550MHz per tone fLO = 950MHz fLO = 2175MHz PRFIN_ = -65dBm fLO = 1550MHz per tone fLO = 950MHz Single carrier IP3RFIN_ 925 -25 10.5 11.5 10.5 -29 -26 -30 dBm dBm RFIN_ Input Second-Order Intercept (Note 4) IP2RFIN_ PRFIN_ = -25dBm per tone, fLO = 951MHz 17 dBm Output-Referred 1dB Compression Point (Note 5) P1dBOUT PRFIN_ = -40dBm, signals within filter bandwidth 2 dBV PRFIN_ = -65dBm 10.2 dB PRFIN_ = -25dBm 44.8 dB Noise Figure NF fRFIN_ = 1550MHz, VGC1 = 1V, VGC2 adjusted 0.59Vp-p baseband level _______________________________________________________________________________________ 3 MAX2106 DC ELECTRICAL CHARACTERISTICS (continued) MAX2106 DBS Direct Downconverter AC ELECTRICAL CHARACTERISTICS (continued) (RFIN+ IC driven single-ended with RFIN- AC-terminated in 75Ω to GND, VCC = +4.75V to +5.25V, VIOUT_ = VQOUT_ = 0.59Vp-p, CIOUT_ = CQOUT_ = 10pF, fLCLK = 2MHz, RIOUT_ = RQOUT_ = 10kΩ, VLOBUFSEL = 0.5V, VRFBAND = VINSEL = VCPG1 = VCPG2 = +2.4V, VPLLIN+ = VMOD+ = +1.3V, VPLLIN- = VMOD- = +1.1V, TA = +25°C, unless otherwise noted. Typical values are at VCC = +5V.) PARAMETER RFIN+ Return Loss (Note 6) SYMBOL CONDITIONS MIN TYP fRFIN_ = 925MHz, ZSOURCE = 75Ω +13 fRFIN_ = 2175MHz, ZSOURCE = 75Ω +14 MAX UNITS dB LO 2nd Harmonic Rejection (Note 7) Average level of VIOUT_, VQOUT_ 32 dB LO Half Harmonic Rejection (Note 8) Average level of VIOUT_, VQOUT_ 41.5 dB LO Leakage Power (Notes 6, 9) Measured at RFIN+ -66 dBm f = 925MHz 0.5 f = 1550MHz 1.0 f = 2175MHz 2.0 RFOUT PORT (LOOPTHROUGH) RFIN+ to RFOUT Gain (Note 10) RFOUT Output Third-Order Intercept Point (Note 10) RFOUT Noise Figure (Note 10) RFOUT Return Loss (Notes 6, 10) f = 925MHz 9 f = 1550MHz 7 f = 2175MHz 5 f = 925MHz 12.5 f = 1550MHz 11 f = 2175MHz 11 925MHz < f < 2175MHz, ZLOAD = 75Ω 12 dB dBm dB dB BASEBAND CIRCUITS Output Real Impedance (Note 1) IOUT_, QOUT_ 50 Ω Baseband Highpass -3dB Frequency (Note 1) CIDC_ = CQDC_ = 0.22µF 750 Hz LPF -3dB Cutoff-Frequency Range (Note 1) Controlled by FLCLK signal 8 33 MHz Baseband Frequency Response (Note 1) Deviation from ideal 7th order, Butterworth, up to 0.7 × fC -0.5 0.5 dB fFLCLK = 0.5MHz, fC = 8MHz -5.5 5.5 LPF -3dB Cutoff-Frequency Accuracy (Note 1) fFLCLK = 1.25MHz, fC = 19.3MHz -10 10 fFLCLK = 2.0625MHz, fC = 31.4MHz 10 10 % Ratio of In-Filter-Band to Out-of-FilterBand Noise fIN_BAND = 100Hz to 22.5MHz, fOUT_BAND = 67.5MHz to 112.5MHz Quadrature Gain Error Includes effects from baseband filters, measured at 125kHz baseband 1.2 dB Quadrature Phase Error Includes effects from baseband filters, measured at 125kHz baseband 4 degrees 4 23 _______________________________________________________________________________________ dB DBS Direct Downconverter (IC driven single-ended with RFIN- AC-terminated in 75Ω to GND, VCC = +4.75V to +5.25V, VIOUT_ = VQOUT_ = 0.59Vp-p, CIOUT_ = CQOUT_ = 10pF, ƒLCLK = 2MHz, RIOUT_ = RQOUT_ = 10kΩ, VLOBUFSEL = 0.5V, VRFBAND = VINSEL = VCPG1 = VCPG2 = +2.4V, VPLLIN+ = VMOD+ = +1.3V, VPLLIN- = VMOD- = +1.1V, TA = +25°C, unless otherwise noted. Typical values are at VCC = +5V.) PARAMETER SYMBOL CONDITIONS MIN TYP 0.75 1 MAX UNITS 1.5 Vp-p 7.26 MHz SYNTHESIZER SYNTHESIZER XTLOUT Output Voltage Swing Load = 10pF | | 10kΩ, fXTLOUT = 6MHz Crystal Frequency Range (Note 1) 4 MOD+, MOD- Setup Time (Note 1) tSUM Figure 1 7 ns MOD+, MOD- Hold Time (Note 1) tHM Figure 1 0 ns LOCAL OSCILLATOR OSCILLATOR LOCAL LO Tuning Range (Note 11) 590 1180 LO Buffer Output Voltage (Note 1) VLOBUFSEL ≥ 2.4V, fLO = 925 MHz + 2175MHz At 1kHz offset, fLO = 2175MHz -60 LO Phase Noise (Notes 6, 12) At 10kHz offset, fLO = 2175MHz -75 At 100kHz offset, fLO = 2175MHz -96 fRFIN = 2175MHz 58 RFIN+ to LO Input Isolation (Note 9) 70 MHz VRMS dBc/Hz dB Minimum and maximum values are guaranteed by design and characterization over supply voltage. Driving differential load of 10kΩ || 15pF. Two signals are applied to RFIN_ at fLO - 100MHz and fLO - 199MHz. VGC2 = 1V, VGC1 is set so that the baseband outputs are at 590mVp-p. IM products are measured at baseband outputs but are referred to RF inputs. Note 4: Two signals are applied to RFIN_ at 1200MHz and 2150MHz. VGC2 = 1V, VGC1 is set so that the baseband outputs are at 590mVp-p. IM products are measured at baseband outputs but are referred to RF inputs. Note 5: PRFIN_ = -40dBm so that front-end IM contributions are minimized. Note 6: Using L64733/L64734 demo board from LSI Logic. Note 7: Downconverted level, in dBc, of carrier present at fLO × 2, fLO = 1180MHz, fVCO = 590MHz, VRFBAND = unconnected (see histogram plots). Note 8: Downconverted level, in dBc, of carrier present at fO / 2, fLO = 2175MHz, fVCO = 1087.5MHz, VRFBAND = 2.4V. Note 9: Leakage is dominated by board parasitics. Note 10: VCPG1 = VCPG2 = VRFBAND = VINSEL = 0.5V, ƒLCLK = 0.5MHz. Note 11: Guaranteed by design and characterization over supply and temperature. Note 12: Measured at tuned frequency with PLL locked. PLL loop bandwidth = 3kHz. All phase noise measurements assume tank components have a Q > 50. Note 1: Note 2 Note 3: _______________________________________________________________________________________ 5 MAX2106 AC ELECTRICAL CHARACTERISTICS (continued) DBS Direct Downconverter MAX2106 Pin Description PIN NAME FUNCTION 1, 6, 19, 29, 39, 45 VCC VCC Power-Supply Input. Connect each pin to a +5V ±5% low-noise supply. Bypass each VCC pin to the nearest GND with a ceramic chip capacitor. 2 CFLT External Bypass for Internal Bias. Bypass this pin with a 0.1µF ceramic chip capacitor to GND. 3 XTL- Inverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements. 4 XTL+ Noninverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements. 5, 9, 10, 16, 40, 41, 46 GND Ground. Connect each of these pins to a solid ground plane. Use multiple vias to reduce inductance where possible. 7 RFIN- RF Inverting Input. Bypass RFIN- with 47pF capacitor in series with a 75Ω resistor to GND. 8 RFIN+ RF Noninverting Input. Connect to 75Ω source with a 47pF ceramic chip capacitor. 11 QDC- Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC- to QDC+ (pin 12). 12 QDC+ Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from QDC+ to QDC- (pin 11). 6 13 IDC- Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC- to IDC+ (pin 14). 14 IDC+ Baseband Offset Correction. Connect a 0.22µF ceramic chip capacitor from IDC+ to IDC- (pin 13). 15 LOBUFSEL Local Oscillator Buffer Select. Connect to GND to select DIV32/33 prescaler output; connect VCC to DIV1 to select DIV2 LO buffer output. 17 RFOUT 18 CPG1 20 XTLOUT 21 CPG2 22 GC1 Gain Control Input for RF Front End. High-impedance analog input, with an input range of +1V to +4V. See AC Electrical Characteristics for transfer function. 23 GC2 Gain Control Input for Baseband Signals. High-impedance analog input, with an input range of +1V to +4V. See AC Electrical Characteristics for transfer function. 24 INSEL Loopthrough Mode Enable. High-impedance digital input. Drive low to enable the RFOUT buffer and disable the LO converters. Drive high for normal tuner operation. 25 FLCLK Baseband Filter Cutoff Adjust. Connect to a slew-rate-limited clock source. See AC Electrical Characteristics for transfer function. 26 RFBAND Buffered RF Output. Enabled when INSEL is low. Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See DC Electrical Characteristics for available gain settings. Buffered Crystal Oscillator Output Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See DC Electrical Characteristics for available gain settings. RF Input Band Select Input. Drive high to enable 1680 MHz to 2175 MHz band. Leave unconnected to enable 1180 MHz to 1680 MHz band. Connect to GND to enable 925 MHz to 1180 MHz band. 27 QOUT- Baseband Quadrature Output. Connect to inverting input of high-speed ADC. 28 QOUT+ Baseband Quadrature Output. Connect to noninverting input of high-speed ADC. 30 IOUT- Baseband In-Phase Output. Connect to inverting input of high-speed ADC. 31 IOUT+ Baseband In-Phase Output. Connect to noninverting input of high-speed ADC. 32 LODIVSEL LO Buffer Divider Ratio Input. Drive high to enable divide-by-one LO buffer output. Connect to GND to enable divide-by-two buffer output. 33 MOD+ PECL Modulus Control. A PECL high on MOD+ sets the dual-modulus prescaler to divide by 32. A PECL logic low sets the divide ratio to 33. Drive with a differential PECL signal in conjunction with MOD- (pin 34). _______________________________________________________________________________________ DBS Direct Downconverter PIN NAME FUNCTION 34 MOD- 35 PLLIN+ PECL Phase-Locked Loop Input. Drive with a differential PECL signal in conjunction with PLLIN- (pin 36). 36 PLLIN- PECL Phase-Locked Loop Input. Drive with a differential PECL signal in conjunction with PLLIN+ (pin 35) 37 LOBUF+/ PSOUT+ LOBUFSEL = GND: PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used in conjunction with PSOUT-. Requires PECL-compatible termination. LOBUFSEL=VCC: 50Ω LO buffer noninverting output. 38 LOBUF-/ PSOUT- LOBUFSEL = GND: PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used in conjunction with PSOUT+. Requires PECL-compatible termination. LOBUFSEL = VCC: 50Ω LO buffer inverting output. 42 TANK- LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning. 43 VRLO LO Internal Regulator. Bypass with a 1000pF ceramic chip capacitor to GND. 44 TANK+ LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning. PECL Modulus Control. A PECL low on MOD- sets the dual-modulus prescaler to divide by 32. A PECL logic high sets the divide ratio to 33. Drive with a differential PECL signal in conjunction with MOD+ (pin 33). 47 FB Feedback Input for Loop Filter 48 CP Voltage Drive Output. Control of external charge-pump transistor. MOD+, MOD- 50% tSUM 50% tHM PSOUT+ 50% PSOUT- 50% Figure 1. Modulus Control Timing Diagram _______________________________________________________________________________________ 7 MAX2106 Pin Description (continued) DBS Direct Downconverter MAX2106 Functional Diagram CPG1 CPG2 PLLIN+ MAX2106 CHARGE PUMP PLLIN- CP FB /8 XTL+ XTLOUT XTLLODIVSEL MOD+ MODRFBAND TANK+ x2 TANKVCC VRLO VOLTAGE REGULATOR RFINGC1 LOBUF-/PSOUTBASEBAND OFFSET CORRECTION IDC+ IDCQDC+ QDCIOUT+ CFLT GND RFIN+ LOBUFSEL LOBUF+/PSOUT+ /32, 33 1, 2 IOUT90° QOUT+ QOUT- GC2 FLCLK RFOUT INSEL 8 _______________________________________________________________________________________ DBS Direct Downconverter 48L,TQFP.EPS _______________________________________________________________________________________ 9 MAX2106 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX2106 DBS Direct Downconverter Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.