ETC L64733C/L64734

®
L64733C/L64734 Tuner and
Satellite Receiver Chipset
Datasheet
The L64733C/734 chipset is designed for satellite broadcast digital TV. It
is compliant with the European digital video broadcast (DVB-S) standard,
as well as the technical specifications for DSS systems. The
L64733C/734 chipset forms a complete “L-band-to-bits” system.
A typical application of the L64733C/734 chipset is satellite digital TV
reception in accordance with the ETS 300 421 standard. Figure 1 shows
the L64733C/734 chipset satellite receiver implemented in a typical
satellite receiver set-top decoder.
Figure 1
Set-Top Box Block Diagram
FLASH
SDRAM-B
SDRAM-A
27 MHz
VCXO
Expansion
Bus
Satellite
RF Signal
L64734
Demodulator
L64733C
Tuner
SC2000
Single-Chip
Source Decoder
Smart
Cards
RS232-C
Interface
CODEC
Audio
Analog CVBS
Analog Y/C
Analog RGB
Digital Video
Serial Bus
IEEE
1284
Analog
OP
AMPs
I/R
Rx & Tx
GPIO
Pins
The L64733C Tuner IC directly down-converts the satellite signal from
L-band to baseband; it includes an on-chip synthesizer. Using frequency
information programmed into its configuration registers, the L64734
Satellite Receiver generates control signals for the L64733C synthesizer.
The L64734 also controls the programming of the low-pass filters on the
February 2001
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
1
L64733C and generates dual automatic gain control (AGC) voltages for
the two-stage automatic gain control on the L64733C. A simplified
chipset block diagram is shown in Figure 2.
Figure 2
L64733C/734 Simplified Block Diagram
Select
RF Input
RF Output
L64733C
RF
Switch
Mixer,
Down
Conversion
Control Signals
Control
Modules for
Synthesizer
and Filter
Baseband
Filter
IOUT QOUT
L64734
Dual ADC
Demodulator
Host
Microcontroller
Microcontroller
Interface
Error
Correction
Descrambler
MPEG Output
Figure 3 shows a more detailed chipset block diagram.
The L64733C accepts the RF In L-Band signal input from the satellite
low noise block (LNB) feed. The L64733C handles a fully loaded raster
of transponder signals from 925 MHz to 2175 MHz. RF In is internally
matched to 75 Ω; it requires no matching network between the cable
connector and the L64733C input pins, except for a DC-blocking
capacitor. The L64733C uses the L64734 INSEL signal to select the
appropriate RF function (Normal or Loop-Through Mode).
2
L64733C/L64734 Tuner and Satellite Receiver Chipset
Figure 3
Detailed Chipset Block Diagram
L64733C
÷
by 8
Xtal
Osc
Phase
Detect.
Charge
Pump
4–7.26 MHz
RF In
RF
Switch
RF Out
Quadrature
Down-Converter
Amp
X2
VCO
Fc
90°
IOUT
FLCLK
QOUT
AGC2
AGC1
2
2
CPG
2
2
PSOUT
PLLIN
FDOUB
INSEL
LOBUF
LODIV
2
÷32/33
or
÷1/2
MOD
Tank
Circuit
To external
Loop Filter
L64734
AGC
Control
Synthesizer Control Module
Filter
Control
Module
Carrier
Loop Control
BPSK/QPSK
Demodulator
Timing Loop
Control
I
Interpolator/Decimation
Filter
Dual
ADC
Matched
Filter
Output
Control
1/T
Q
Microcontroller Data and Address Bus
Clk
(from L64734
on-chip PLL) FEC Decoder Pipeline
External Microcontroller Interface
Microcontroller Data and Address Bus
Channel
Output
(MPEG-2
Transport
Stream)
Descrambler
ReedSolomon
Decoder
Convolutional
Deinterleaver
ReedSolomon
Synchronizer
Viterbi
Decoder
Viterbi
Synchronizer
L64733C/L64734 Tuner and Satellite Receiver Chipset
3
The RF signal is sent to a variable gain stage controlled by the L64734
AGC1 signal. The L64734 adjusts AGC1 in conjunction with AGC2 to
maximize the SNR of the RF In signal while maintaining proper levels at
the baseband outputs (IOUT and QOUT). The signal then is fed to two
mixers in the quadrature demodulator. The mixers are fed with local
oscillator signals that are offset by 90 degrees from one another. The
quadrature demodulator converts the frequency of the RF In signal
directly to baseband while splitting the signal into quadrature I and Q
signal paths.
The baseband signals pass through a pair of variable gain amplifiers,
controlled through the AGC2 pin by the L64734. The signals then pass
through a pair of seventh-order filters for antialiasing. The filter shape is
seventh-order Butterworth, followed by a single-pole delay equalizer. The
L64734 FLCLK signal controls the filter cutoff frequency, which is related
to the baud rate. The filtered baseband output signals are fed to
differential output stages at IOUTp, IOUTn, QOUTp, and QOUTn.
The baseband outputs of the L64733C are sent to the L64734 to be
digitized by the analog-to-digital converter (ADC). Then, they are sent to
a BPSK/QPSK demodulator, filtered, and sent to the L64734 forward
error correction (FEC) decoder pipeline, which outputs an MPEG-2
transport stream.
The frequency synthesizer functionality is split between the L64733C and
L64734. The Synthesizer Control Module resides on the L64734 and
generates control signals for the L64733C Tuner IC frequency
synthesizer. The Synthesizer Control Module also contains
programmable counters for the synthesizer feedback loop.
The L64733C provides analog functions for the frequency synthesizer,
the RF local oscillator, and the crystal reference oscillator. Tuning
oscillator signals are generated for the mixers in the 925–2175 MHz
range, with a 0.625 MHz step size when using a 5 MHz crystal reference.
The on-chip VCO tuning frequency is 543–1088 MHz. To tune channels
from 925–1086 MHz, the L64734 disables the frequency doubler (X2
block) on the L64733C. To tune channels from 1086–2175 MHz, the
L64734 enables the frequency doubler.
The L64733C can improve half-harmonic rejection. It requires special
programming of the frequency doubler control pin (FDOUB), which now
4
L64733C/L64734 Tuner and Satellite Receiver Chipset
has 3-state operation (see the “Synthesizer Control Interface” section on
page 20).
The VCO requires an external resonant tank circuit, which includes
varactor diodes to vary the frequency of oscillation.
The VCO signal is fed to the Prescaler block before being passed
deferentially through the PSOUTp and PSOUTn pins to the L64734. The
L64734 MODp and MODn differential signals control the divider ratio for
the Prescaler block. The L64734 dynamically changes the divide ratio to
ensure that the tuning step size is not affected by the divider. The
L64734 contains programmable counters to further divide the signal
frequency before it is fed back to the L64733C through the PLLINp and
PLLINn pins. The crystal reference oscillator frequency is divided by
eight and fed to the phase detector. The phase detector generates a
current signal proportional to the difference in phase between PLLINp,
PLLINn, and the divided crystal frequency. A charge pump circuit
generates current that controls pins CP and FB, and an external
transistor to buffer the L64733C against the tuning voltage (28 V). The
current is passed through a discrete loop filter and is converted to a
tuning voltage that drives the external varactor diodes for the VCO tank
circuit. A frequency controlled loop is formed. Changing the frequency
divider ratios in the L64734 registers varies the VCO frequency. See
Figure 7, on page 23, for more details regarding the external circuitry for
the VCO, crystal oscillator, charge pump, tank circuitry, and
frequency-controlled loop.
The chipset provides maximum integration and flexibility for system
designers at a minimum cost. The number of external components
required to build a system is minimal because the synthesizer, variable
rate filters, and clock and carrier loops are integrated into the two
devices.
L64733C/L64734 Tuner and Satellite Receiver Chipset
5
Features and Benefits
The following subsections provide a list of system and chipset features.
System Features
•
Direct down-conversion
•
Integrated programmable cut-off low-pass filters for variable-rate
operation
•
Dual AGC for optimizing performance with respect to intermodulation
and noise
•
Integrated synthesizer
•
Integrated quadrature amplitude and phase imbalance compensation
•
RF Loop-Through
Chipset Features
6
•
DVB and DSS system specifications support
•
BPSK/QPSK demodulation rates from 1 to 45 Mbaud
•
Matched filter (square root raised cosine filter with roll off factor of
20% or 35%)
•
Antialiasing filters for operation from 1 to 45 MBaud without switching
external SAW filters or the need for low-pass filters
•
On-chip digital clock synchronization
•
On-chip digital carrier synchronization, featuring a frequency sweep
capability for signal acquisition
•
Autoacquisition demodulator mode and tuner control through an
on-chip microcontroller
•
Integrated Phase-Locked Loop (PLL) for clock synthesis, allowing the
use of a fundamental mode crystal
•
Fast channel switching mode
•
Power estimation for AGC
•
Programmable Viterbi decoder module for rates 1/2, 2/3, 3/4, 5/6, 6/7,
and 7/8
L64733C/L64734 Tuner and Satellite Receiver Chipset
•
(204/188), (146/130) Reed-Solomon decoder
•
Autosynchronization for Viterbi decoder
•
Programmable synchronization for deinterleaver, Reed-Solomon
decoder, and descrambler
•
Bit error monitoring for channel performance measurements
•
Deinterleaver (DVB and DSS)
•
Serial host interface compatible with the LSI Logic Serial Control bus
interface
•
Power-down mode
•
On-chip dual differential 6-bit ADCs
•
Supports Synchronous Parallel Interface protocol for FEC data output
Chipset Interconnections
Figure 4 illustrates the signals between the L64733C and L64734.
L64733C/L64734 Tuner and Satellite Receiver Chipset
7
Figure 4
Chipset Interconnection Diagram
L64734
L64733C
AGC1
AGC2
CPG1
CPG2
FDOUB
FLCLK
INSEL
AGC1
AGC2
XCTR[0]
XCTR[1]
FDOUB
FLCLK
INSEL
MODp
MODn
PLLINp
PLLINn
XTLOUT
MODp
MODn
PLLINp
PLLINn
XOIN
Prescaler
Signals
PSOUTp
PSOUTn
PSOUTp
PSOUTn
Prescaler
Signals
Channel Data
Signals
IOUTp
IOUTn
QOUTp
QOUTn
IVINp
IVINn
QVINp
QVINn
Channel Data
Signals
Control
Signals
Control
Signals
L64733C Signal Descriptions
This section describes the L64733C signals. Figure 5 shows the interface
diagram of the L64733C. An “n” suffix (for example, ERROROUTn)
designates an active LOW signal. Names of differential signals are
designated with a “p” suffix for the noninverting side (for example,
QOUTp), and with an “n” suffix for the inverting side (for example,
QOUTn).
8
L64733C/L64734 Tuner and Satellite Receiver Chipset
Figure 5
L64733C Interface Diagram
RFINn
RF
Signals
RFINp
RFOUT
Oscillator
Signals
Channel Data
Signals
Prescaler
Signals
XTLn
XTLp
XTLOUT
CFLT
TANKn
TANKp
VRLO
IOUTn
IOUTp
QOUTn
QOUTp
PSOUTn
PSOUTp
AGC1
AGC2
CPG1
CPG2
FDOUB
FLCLK
IDCp
IDCn
INSEL
LOBUF
LODIV
MODp
MODn
PLLINp
PLLINn
QDCp
QDCn
CP
FB
Control
Signals
Charge Pump
Signals
As shown in Figure 5, the L64733C has the following major interfaces:
•
RF
•
Oscillator
•
Channel Data
•
Prescaler
•
Control
•
Charge Pump
The following signal descriptions are listed according to the major
interface groups.
RF Signals
The L64733C can accept an RF input signal and loop it to RFOUT, as
determined by an on-chip RF switch.
L64733C/L64734 Tuner and Satellite Receiver Chipset
9
RFINp, RFINn RF Input
Input
The RFIN differential signals form the 75 Ω input.
Connect the RFINp signal through a series 100 pF
capacitor to a 75 Ω F video connector and the RFINn
signal through a series 75 Ω resistor and 100 pF
capacitor to ground.
RFOUT
RF Output
Output
The RFOUT signal is a 75 Ω output that is active when
the INSEL input is deasserted. When active, the signal at
RFOUT is a copy of the RFIN signal.
Oscillator Signals
The L64733C has two internal oscillators, a crystal oscillator and a tank
oscillator.
CFLT
Bias Voltage Bypass
Bidirectional
Connect the CFLT pin as shown in Figure 7 on page 23.
TANKp, TANKn
Oscillator Tank Port
Input
Connect the TANKp and TANKn pins as shown in
Figure 7 on page 23.
VRLO
Local Oscillator Regulator Bypass
Bidirectional
Connect the VRLO pin as shown in Figure 7 on page 23.
XTLp, XTLn
Crystal Oscillator Port
Input
Connect the XTLp and XTLn pins as shown in Figure 7
on page 23.
XTLOUT
Crystal Out
Output
This signal provides a buffered clock reference frequency
for driving the L64734 XOIN pin.
Channel Data Signals
The following signals are the channel data signals from the L64733C to
the L64734.
IOUTp, IOUTn I Channel Baseband Data
Output
The IOUT differential signals form the in-phase data
provided to the L64734.
10
L64733C/L64734 Tuner and Satellite Receiver Chipset
QOUTp, QOUTn
Q Channel Baseband Data
Output
The QOUT differential signals form the quadrature-phase
data provided to the L64734.
Prescaler Signals
The following signals are the prescaler outputs from the L64733C to the
L64734.
PSOUTp, PSOUTn
Prescaler
Output
When the LOBUF signal is LOW, the PSOUT differential
signals are the L64733C prescaler outputs.
When LOBUF is HIGH, the Local Oscillator (LO) buffer
(50 Ω) feeds the PSOUT differential signals.
The programmable counters on the L64734 are clocked
on the rising edge of the PSOUT signal.
Control Signals
The following signals, some of which are generated by the L64734 IC,
control the mode of operation of the L64733C IC.
AGC1
Automatic Gain Control 1
Input
The AGC1 signal is a high-impedance input from the
L64734 that controls RF AGC circuitry. The AGC1 voltage
has a range of 0.5 V to 4.8 V.
AGC2
Automatic Gain Control 2
Input
The AGC2 signal is a high-impedance input from the
L64734 that controls RF AGC circuitry.
CPG[2:1]
Charge Pump Gain
The CPG[2:1] signals set the charge pump gain
according to the table below.
Input
Charge Pump Current (typ), mA
CPG1
CPG2
FB HIGH
FB LOW
0
0
0.1
−0.1
0
1
0.3
−0.3
1
0
0.6
−0.6
1
1
1.8
−1.8
L64733C/L64734 Tuner and Satellite Receiver Chipset
11
FDOUB
Frequency Doubler
Input
When FDOUB is asserted, the L64733C local oscillator
frequency is internally doubled and fed to the mixers.
When FDOUB is deasserted, the oscillator frequency is
not doubled before being fed to the mixers.
Bit 6 of register 79, group 4 (APR 79), controls the
L64734 FDOUB output pin, which enables or disables the
frequency doubler on the L64733C.
The FDOUB pin is set as shown in the table below, where
Fswitch is the frequency at which the frequency doubler is
enabled or disabled.
FDOUB
APR 79[6]
TRI
APR 79[2]
FDOUB
Pin
925 MHz–Fswitch
0
0
LOW
Fswitch–1680 MHz
1
1
3-state
1680–2175 MHz
1
0
HIGH
Frequency
This method of control preserves the compatibility with
the L64733B, which is not affected by 3-stating the
FDOUB pin.
12
FLCLK
Filter Clock
Input
The FLCLK signal is a low amplitude, self-biased clock
input. The frequency of the FLCLK signal multiplied by 16
is the baseband filter’s −3 dB frequency.
IDCp, IDCn
I-Channel DC Offset Correction
Input
Connect a 0.1 µF or larger capacitor between the IDCp
and IDCn signals.
INSEL
RF Port Input Select
Input
When the INSEL signal is asserted, the L64733C is in
normal mode. When the INSEL signal is deasserted, the
L64733C is in Loop-Through mode. In this mode, the
RFIN signal is looped through out to the RFOUT signal
and the L64733C local oscillator is shut off.
LOBUF
Local Oscillator Buffer Select
Input
Asserting LOBUF causes the external PLL mode to be in
effect, the local oscillator (LO) buffer to be enabled, and
the LO signal to be sent out to the PSOUT pins according
to the division ratio selected with the LODIV signal. When
L64733C/L64734 Tuner and Satellite Receiver Chipset
LOBUF is deasserted, the internal PLL mode is in effect,
and the PSOUT pins are driven from the 32/33 prescaler.
LODIV
Local Oscillator Buffer Division Ratio
Input
When the LODIV signal is asserted, the local oscillator
(LO) buffer division ratio is set to 1; when it is deasserted,
the ratio is set to 2.
MODp, MODn Prescaler Modulus
Input
The MOD differential signals form a Positive Emitter
Coupled Logic (PECL) input that sets the prescaler
modulus. When the MODp signal is positive with respect
to the MODn signal, the prescaler modulus is set to 32
(divide by 32). When the MODn signal is positive with
respect to the MODp signal, the prescaler modulus is set
to 33 (divide by 33).
PLLINp, PLLINn
Phase Detector
Input
The PLLIN differential signals form the phase detector
input and are connected to the L64734 PLLINp and
PLLINn output signals. See the L64734 PLLINp and
PLLINn descriptions in the “Synthesizer Control Interface”
section.
QDCp, QDCn Q-Channel DC Offset Correction
Input
Connect a 0.1 µF or larger capacitor between the QDCp
and QDCn signals.
Charge Pump Signals
The following signals are outputs from the L64733C charge pump.
CP
Charge Pump
Output
Connect the CP signal as shown in Figure 7, on page 23.
FB
Feedback
Charge Pump Transistor Drive
Output
Connect the FB signal as shown in Figure 7, on page 23.
L64734 Signal Descriptions
This section describes the L64734 signals. Figure 6 shows the interface
diagram of the L64734.
L64733C/L64734 Tuner and Satellite Receiver Chipset
13
Figure 6
L64734 Interface Diagram
IBYPASS[5:0]
IVINn
IVINp
QBYPASS[5:0]
QVINn
QVINp
Channel
Interface
CLK
XOIN
XOOUT
Channel Clock
Interface
LCLK
LP2
PCLK
PLLAGND
PLLVDD
PLLVSS
PLL
Interface
IDDTN
RESET
XCTR_IN
XCTR[3:0]
Control Signals
Interface
AGC Control
Interface
AGC1
AGC2
Tuner Control
Interface
FLCLK
INSEL
BCLKOUT
CO[7:0]
COEn
DVALIDOUT
ERROROUTn
FSTARTOUT
INTn
SADR[1:0]
SCLK
SDATA
FDOUB
MODp
MODn
PLLINp
PLLINn
PSOUTp
PSOUTn
VREF_LVDS
RESO_LVDS
FBUFVDD
FBUFVSS
IBIAS
ADCVDDI
ADCVDDQ
ADCVSSI
ADCVSSQ
Channel Data
Output Interface
Microcontroller
Interface
Synthesizer
Control
Interface
ADC
Interface
As shown in Figure 6, the L64734 has the following major interfaces:
14
•
Channel
•
Channel Clock
•
PLL
•
Control Signals
•
ADC
•
AGC Control
•
Channel Data Output
•
Microcontroller
•
Synthesizer Control
•
Tuner Control
L64733C/L64734 Tuner and Satellite Receiver Chipset
The following signal descriptions are listed according to the major
interface groups.
Channel Interface
The Channel Interface is the input path to the L64734 satellite receiver.
The two signals IVIN and QVIN are the I and Q streams from the satellite
tuner circuit. The CLK signal strobes in the data signals.
IBYPASS[5:0] I Channel Data
Input
The IBYPASS[5:0] signals form the digital received
I channel data input bus, which supplies the I Stream to
the L64734 when the ADC is bypassed. The setting of
particular register bits in the L64734 controls the bypass.
IVINp, IVINn
I Channel Data
Input
The IVINp and IVINn differential signals form the analog
received I channel data input bus, which supplies the I
stream to the L64734.
QBYPASS[5:0]
Q Channel Data
Input
The QBYPASS[5:0] signals form the digital received
Q channel data input bus, which supplies the Q Stream
to the L64734 when the ADC is bypassed. The setting of
particular register bits in the L64734 controls the bypass.
QVINp, QVINn
Q Channel Data
Input
The QVINp and QVINn differential signals form the
analog received Q channel data input bus, which supplies
the Q stream to the L64734.
Channel Clock Interface
The Channel Clock Interface consists of the clock and crystal oscillator
signals.
CLK
IVIN/QVIN Input Clock
Input
CLK is a positive, edge-triggered clock that strobes input
data to the L64734.
L64733C/L64734 Tuner and Satellite Receiver Chipset
15
XOIN
Crystal Oscillator In
Input
The XOIN pin provides a crystal oscillator or external
reference clock input. Normally, a 15 MHz crystal is
connected to the XOIN pin.
XOOUT
Crystal Oscillator Out
Output
The XOOUT pin is the crystal oscillator output pin.
Phase-Locked Loop (PLL) Interface
The internal PLL generates the signals to operate the ADC,
Demodulator, and FEC modules.
16
LCLK
Decimated Clock Output
Output
The L64734 internal clock generation module generates
the LCLK signal. LCLK is derived from CLK by dividing
by the value of the CLK_DIV2 register parameter.
LP2
Input to VCO
Input
The LP2 signal is the input to the internal
voltage-controlled oscillator. Normally, it is connected to
the output of an external RC filter circuit.
PCLK
PLL Clock Output
Output
The L64734 internal PLL clock synthesis module
generates the PCLK signal. The reference crystal
connected between the XOIN and XOOUT pins drives
the PLL. The PLL clock synthesis module can be
configured to generate a PCLK rate that is appropriate for
all data rates.
PLLAGND
PLL Analog Ground
Input
PLLAGND is the analog ground pin for the PLL module
and normally is connected to the system ground plane.
PLLVDD
PLL Power
Input
PLLVDD is the power supply pin for the PLL module and
normally is connected to the system power (VDD) plane.
PLLVSS
PLL Ground
Input
PLLVSS is the ground pin for the PLL module and
normally is connected to the system ground plane.
L64733C/L64734 Tuner and Satellite Receiver Chipset
Control Signals Interface
The Control Signals Interface controls the operation of the L64734 and
is not associated with any particular interface.
IDDTN
Test
Input
The IDDTN pin is an LSI Logic internal test pin. Tie the
IDDTN pin LOW for normal operation.
RESET
Reset
Input
This active-HIGH signal resets all internal data paths.
Reset timing is asynchronous to the device clocks. Reset
does not affect the configuration registers.
XCTR_IN
Control Input
Input
The XCTR_IN pin is an external input control pin. It is
sensed by reading the XCTR_IN register bit.
XCTR[3]
Control Output/Sync Status Flag
Output
The XCTR[3] signal indicates the synchronization status
for one of three synchronization modules in the L64734
or the XCTR[3] field in Group 4, APR 55. The three
modules are the Viterbi Decoder, Reed-Solomon
Deinterleaver (DI/RS), and Descrambler. For each of the
three synchronization outputs, the asserted XCTR[3]
signal indicates that synchronization is achieved for the
sync module chosen using the SSS[1:0] register bits.
When deasserted, the signal indicates an
out-of-synchronization condition.
XCTR[2:0]
Output Control
Output
The XCTR[2:0] pins are external output control pins.
They are set by programming particular register bits.
XCTR[2] is mapped to CPG1 and XCTR[0] is multiplexed
with CPG2 when used with the L64733C Tuner IC. When
the on-chip serializer generates a serial 2- or 3-wire
protocol on the XCTR[2:0] pins, the mapping is XCTR[2]
= EN, XCTR[1] = SCL, and XCTR[0] = SDA.
Analog-to-Digital Converter (ADC) Interface
The ADC module converts the incoming IVIN and QVIN signals into an
internal 6-bit digital representation for processing. The following pins
support the ADC module.
L64733C/L64734 Tuner and Satellite Receiver Chipset
17
ADCVDDI/Q
ADC Power
Input
ADCVDDI/Q are the analog power supply pins for the
ADC module and normally are connected to the system
power (VDD) plane.
ADCVSSI/Q
ADC Analog Ground
Input
ADCVSSI/Q are the analog ground pins for the ADC
module and normally are connected to the system
ground plane.
FBUFVDD
Analog Supply
Input
FBUFVDD is the analog supply pin for the on-chip
reference voltage generator. This pin normally is
connected to the system power (VDD) plane.
FBUFVSS
Analog Ground
Input
FBUFVSS is the analog ground pin for the on-chip
reference voltage generator. This pin normally is
connected to the system ground (VSS) plane.
IBIAS
ADC Bias Current
Output
This is the bias current for the ADC module. Connect this
output to a 39 kΩ resistor, and connect the other side of
the resistor to ground.
AGC Control Interface
The AGC Control Interface contains signals used for power control.
AGC1, AGC2 Power Control
Output
The AGC1 and AGC2 signals are the positive Σ∆
modulated output used for power control. These signals
can each drive an external passive RC filter that feeds a
gain control stage for dual-stage AGC. For a single stage
AGC, AGC1 can be used, and has the same functionality
as the PWRP pin on the L64724.
Channel Data Output Interface
The Channel Data Output Interface is the output path from the L64734.
It typically is connected to the input of the transport demultiplexer in a
set-top decoder application.
18
L64733C/L64734 Tuner and Satellite Receiver Chipset
BCLKOUT
Byte Clock Out
Output
The BCLKOUT output signal is a strobe that indicates
valid data bytes on the CO[7:0] bus when the L64734 is
in Parallel Channel Output mode. The BCLKOUT signal
cycles once every valid output data byte and is used by
the transport demultiplexer to latch output data from the
L64734 at the BCLKOUT rate. The BCLKOUT signal
must be disregarded in Serial Channel Output mode.
CO[7:0]
Channel Data Out
Output
The CO[7:0] signals form the decoded output data port.
When the OF bit is 1 (Group 4, APR17), the L64734
operates in the Parallel Channel Output mode. In this
mode, the L64734 outputs the channel data as 8-bit wide
parallel data on the CO[7:0] signals. In Serial Channel
Output mode (OF = 0), the L64734 outputs the channel
data as serial data on CO[0]. The data is latched on each
bit clock cycle. The chronological ordering in Serial
Channel output mode is MSB oldest, LSB newest.
COEn
Channel Output Enable
Input
When asserted, the COEn signal enables the
ERROROUTn, CO[7:0], DVALIDOUT, BCLKOUT, and
FSTARTOUT signals. Operation of the receiver continues
regardless of the state of the COEn signal.
DVALIDOUT
Valid Data Out
Output
The DVALIDOUT signal indicates that the CO[7:0] signals
contain the corrected channel data. New data is valid on
the CO[7:0] signals when the DVALIDOUT signal is
asserted. DVALIDOUT is not asserted during the
propagated check and GAP bytes. The DVALIDOUT
signal is deasserted after the FEC_RST register bit
(Group 4, APR 55) is set to one.
ERROROUTn Error Detection Flag
Output
The L64734 asserts the ERROROUTn signal at the
beginning of each frame that contains an uncorrectable
error, and deasserts it at the end of the frame if the error
condition is removed. The ERROROUTn signal is aligned
with the output data stream and is asserted after the
FEC_RST register bit is set.
L64733C/L64734 Tuner and Satellite Receiver Chipset
19
FSTARTOUT Frame Start Output
Output
The L64734 asserts the FSTARTOUT signal during the
first bit of every frame with valid data in Serial Channel
Output mode and during the first byte in Parallel Channel
Output mode. FSTARTOUT is valid only when the
DVALIDOUT signal is asserted. The FSTARTOUT signal
is deasserted after the FEC_RST register bit is set.
Microcontroller Interface
The Microcontroller Interface connects the L64734 to an external
microcontroller.
INTn
Interrupt
Output
The L64734 asserts INTn when an internal unmasked
interrupt flag is set. The INTn signal remains asserted
during the interrupt condition, and the interrupt flag is not
masked.
SADR[1:0]
Serial Address
Input
The SADR[1:0] signals are the two programmable bits of
the serial address for the L64734.
SCLK
Serial Clock
Bidirectional
SCLK is the serial clock pin for a two-wire serial protocol.
SDATA
Serial Data
Bidirectional
SDATA is the serial data pin for a two-wire serial protocol.
Synthesizer Control Interface
The Synthesizer Control Interface allows the L64734 to control the
L64733C frequency synthesizer.
FDOUB
20
Frequency Doubler
Output, 3-State
Bit 6 of register Group 4, APR 79 controls the L64734
FDOUB output pin, which enables or disables the
frequency doubler on the L64733C.
L64733C/L64734 Tuner and Satellite Receiver Chipset
The FDOUB pin is set as shown below; Fswitch is the
frequency that disables or enables the frequency doubler.
FDOUB
APR 79[6]
TRI
APR 79[2]
FDOUB
Pin
925 MHz–Fswitch
0
0
LOW
Fswitch–1680 MHz
1
1
3-state
1680–2175 MHz
1
0
HIGH
Frequency
MODp, MODn Modulus Selector
Output
The MODp and MODn signals are low-voltage differential
signals from the L64734 of modulus selector
programmable counter (A). PSOUT clocks these signals.
When the MODp signal is positive with respect to the
MODn signal, divide-by-32 is selected at the dual
modulus prescaler on the L64733C Tuner IC. When
MODp is negative with respect to MODn, divide-by-33 is
selected. The counter A can be programmed to count
down from a particular value by register bit programming.
PLLINp, PLLINn
PLL Differential Counter M
Output
The PLLINp and PLLINn signals are low-voltage
differential signals from the L64734 programmable
synthesizer counter (M). PSOUT clocks these signals.
PLLINp is positive with respect to PLLINn for one PSOUT
cycle. The repetition rate is 0.5 MHz for a 4 MHz
reference crystal. The counter M can be programmed to
count down from a particular value by register bit
programming.
PSOUTp, PSOUTn
Prescaler Output
Output
The PSOUTp and PSOUTn signals are differential
signals to the L64734 from the L64733C. The
programmable counters on the L64734 are clocked on
the rising edge of the PSOUT signal.
In the external PLL mode (LOBUF = HIGH), these signals
come from the LO buffer, for which the LODIV signal sets
the divider ratio.
RESO_LVDS LVDS Buffers Precision Resistor
Output
The RESO_LVDS output must be connected to a resistor
(6.8 kΩ, which controls the swing of the LVDSOUT
L64733C/L64734 Tuner and Satellite Receiver Chipset
21
buffers used to drive the differential signals MODp,
MODn, and PLLINp, PLLINn. Connect the other side of
the resistor to ground.
VREF_LVDS
LVDS Buffers Reference Voltage
Input
The VREF_LVDS input is a 1.2 V ± 10% voltage level that
controls the common mode voltage of the LVDSOUT
buffers used to drive the differential signals MODp,
MODn, and PLLINp, PLLINn.
Tuner Control Interface
The Tuner Control Interface contains signals that control the L64733C
Tuner IC.
FLCLK
Filter Control Clock
Output
This is the output of a programmable integer value divider
clocked by PCLK (the demodulator sampling clock). The
division ratio can be programmed with register bits. The
FLCLK frequency multiplied by 16 is the 3 dB cutoff of the
programmable low pass filters on the L64733C.
INSEL
RF Input Select
Output
When INSEL is asserted, the L64733C tuner selects the
normal mode. When INSEL is deasserted, the L64733C
selects the Loop-Through mode.
Typical Operating Circuit
Figure 7 is a diagram of a typical operating circuit for the chipset,
implemented with the L64733C-48 (48-pin package), including external
components. Not all external components are shown. See the L64733/34
Evaluation Board User’s Guide for complete schematic details.
22
L64733C/L64734 Tuner and Satellite Receiver Chipset
L64733C/L64734 Tuner and Satellite Receiver Chipset
0.1 µF
0.01 µF
Varactors (2)
PLLINn
PLLINp
MODn
MODp
LODIV
IOUTp
IOUTn
VCC
QOUTp
QOUTn
FDOUB
36
35
34
33
32
31
30
29
28
27
26
25
Stripline
Inductors (2)
AGC Filter
47 kΩ
1. The ground connections for the L64733C are provided via a metal plate under the IC,
rather than by direct connection of the ground pins to the PCB.
2. Not all external components are shown. Refer to the L64733/34 Evaluation Board
User’s Guide for complete details.
Notes:
L64733C-48
24
23
22
21
20
19
18
17
16
15
14
13
100 pF
VCC
CFLT
XTLn
XTLp
GND1
VCC
RFINn
RFINp
GND1
GNDSUB1
QDCn
INSEL
AGC2
AGC1
CPG2
XTLOUT
VCC
CPG1
RFOUT
GND1
LOBUF
IDCp
100 pF
75 Ω
75 Ω 100 pF
24 24
PSOUTp
PSOUTn
VCC
GND1
GND1
TANKn
VRLO
TANKp
VCC
GND1
FB
5 MHz
0.1 µF
100 pF
47 pF
1
2
3
4
5
6
7
8
9
10
11
12
1 kΩ
100 pF
6.8 kΩ
1 nF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD
VSS
ADCVDDI
IVINp
IVINn
ADCVSSI
FBUFVDD
IBIAS
FBUFVSS
ADCVDDQ
QVINp
QVINn
ADCVSSQ
VDD
VSS
FDOUB
FLCLK
INSEL
AGC2
AGC1
VDD
VSS
XCTR[1]
XCTR[0]
XCTR[2]
XCTR[3]
XCTR_IN
VDD
L64734
VSS
VDD
PLLVSS
LP2
PLLAGND
PLLVDD
PCLK
LCLK
VSS
VDD
CO[0]
CO[1]
CO[2]
CO[3]
VSS
VDD
CO[4]
CO[5]
CO[6]
CO[7]
VSS
VDD
BCLKOUT
DVALIDOUT
FSTARTOUT
ERROROUTn
VSS
SADR[1]
SADR[0]
VDD
VSS
SDATA
SCLK
INTn
RESET
VDD
VSS
PSOUTn
PSOUTp
VDD
VSS
PLLINn
PLLINp
RESO_LVD
S
100 VREF_LVD
75 Ω
BC847
0.2 µF
1 kΩ
22 nF 10 kΩ
22 kΩ
Typical Operating Circuit
37
38
39
40
41
42
43
44
45
46
47
48
180 pF
VCC
28 V
Figure 7
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
XOOUT
XOIN
VSS
CLK
VDD
QBYPASS[0
]
QBYPASS[1
]
VSS
VDD
QBYPASS[2
]
QBYPASS[3
]
QBYPASS[4
]
QBYPASS[5
]
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
23
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Specifications
This section contains the electrical, timing, and mechanical specifications
for the L64733C/734 chipset.
L64733C Electrical Specifications
Table 1 lists the absolute maximum values. Exceeding the values listed
can cause damage to the L64733C. Table 2 gives the recommended
operating supply voltage and temperature. Table 3 gives the DC
characteristics; Table 4 gives the AC characteristics; and Table 5 and
Table 6 summarize the pins for the 48- and 44-pin packages,
respectively.
Table 1
L64733C Absolute Maximum Rating (Referenced to VSS)
Symbol Parameter
VCC
DC supply voltage
Limits1
Units
−0.5 to +7.0
V
–
Continuous power dissipation up to +70 °C
1.8
W
–
Derating above +70 °C
27
mW/°C
–
Operating temperature
0 to +70
°C
–
Junction temperature
+150
°C
–
Storage Temperature
−65 to +165
°C
–
Lead temperature (soldering 10 sec)
+300
°C
1. Note that the ratings in this table are those beyond which permanent device
damage is likely to occur. Do not use these values as the limits for normal
device operation.
Table 2
Recommended Operating Conditions
Symbol Parameter
VDD
TA
DC Supply Voltage
Operating Ambient Temperature Range (Commercial)
Limits1 Units
5 ± 5%
V
70
°C
1. For normal device operation, adhere to the limits in this table. Sustained
operation of a device at conditions exceeding these values, even if they are
within the absolute maximum rating limits, can result in permanent device
damage or impaired device reliability. Device functionality to stated DC and
AC limits is not guaranteed if recommended operating conditions are
exceeded.
24
L64733C/L64734 Tuner and Satellite Receiver Chipset
Table 3
DC Characteristics of the L64733C
Parameter
Condition
Min
Typ
Max
Units
All DC specs met
4.75
5.0
5.25
V
–
195
275
mA
Power Supply
Power Supply Voltage
Power Supply Current
Digital Control Inputs - CPG1, CPG2, INSEL, FDOUB, LOBUF, LODIV
Input Logic Level High
2.4
–
–
V
Input Logic Level Low
0
–
0.5
V
−15
–
10
µA
FLCLK Input Level Low
–
–
1.45
V
FLCLK Input Level High
1.85
–
–
V
−1
–
1
µA
1.08
1.2
1.32
V
Input Bias Current
Pin at 2.4 V
Slew-Limited Digital Clock Inputs - FLCLK
FLCLK Input
Resistance/Leakage
Current
50 kΩ series resistor between
L64734 and FLCLK pin. L64734 generates normal CMOS levels
Fast Digital Clock Inputs - MODp, MODn, PLLINp, PLLINn
MODp, MODn, PLLINp,
PLLINn Common Mode Input
Range (VCM)
MODp, MODn, PLLINp,
PLLINn Input Voltage Low
MODp, MODn, or PLLINp, PLLINn
differential swing around VCM. Need
external 100-Ω termination.
–
–
−100
mV
MODp, MODn, PLLINp,
PLLINn Input Voltage High
MODp, MODn, or PLLINp, PLLINn
differential swing around VCM. Need
external 100-Ω termination
100
–
–
mV
MODp, MODn, PLLINp,
PLLINn Input Current
MODp, MODn, PLLINp, PLLINn
−5
–
+5
µA
2.16
2.4
2.64
V
–
−215
−150
mV
Digital Clock Outputs - PSOUTp, PSOUTn
PSOUTp, PSOUTn Common
Mode Output Range (VCM)
PSOUTp, PSOUTn Output
Voltage Low
PSOUTp, PSOUTn differential swing
around VCM. Driving LSI PECL Load
(±10 µA), LOBUF = 0
(Sheet 1 of 3)
L64733C/L64734 Tuner and Satellite Receiver Chipset
25
Table 3
DC Characteristics of the L64733C (Cont.)
Parameter
Condition
Min
Typ
Max
Units
PSOUTp, PSOUTn Output
Voltage High
PSOUTp, PSOUTn differential swing
around VCM. Driving LSI PECL Load
(±10 µA), LOBUF = 0
150
215
–
mV
PSOUTp, PSOUTn Output
Voltage Low
PSOUTp, PSOUTn differential swing
around VCM, driving 100 Ω
differential LOBUF = 1
–
−140
−100
mV
PSOUTp, PSOUTn Output
Voltage High
PSOUTp, PSOUTn differential swing
around VCM, driving 100 Ω
differential. LOBUF is asserted.
100
140
–
mV
MOD = High
32
–
32
–
MOD = Low
33
–
33
–
Synthesizer/Local Oscillator Buffer
Prescaler Ratio
LO Buffer Division Ratio
LOBUF = High, LODIV = Low
2
–
LOBUF = High, LODIV = High
1
–
Reference Divider Ratio
Charge Pump Output High
Current (at FB)
Charge Pump Output Low
Current (at FB)
8
–
8
–
CPG1, CPG2 = 0, 0
0.08
0.1
0.12
mA
CPG1, CPG2 = 0, 1
0.24
0.3
0.36
mA
CPG1, CPG2 = 1, 0
0.48
0.6
0.72
mA
CPG1, CPG2 = 1, 1
1.44
1.8
2.16
mA
CPG1, CPG2 = 0, 0
−0.12
-0.1
−0.08
mA
CPG1, CPG2 = 0, 1
−0.36
-0.3
−0.24
mA
CPG1, CPG2 = 1, 0
−0.72
-0.6
−0.48
mA
CPG1, CPG2 = 1, 1
−2.16
-1.8
−1.44
mA
−25
–
25
nA
−5
–
5
%
100
–
–
µA
Charge Pump Output
Leakage Current
Charge Pump
Positive-to-Negative Current
Matching
Charge Pump Output
Transistor Base Current Drive
FB self-biased.
(Sheet 2 of 3)
26
L64733C/L64734 Tuner and Satellite Receiver Chipset
Table 3
DC Characteristics of the L64733C (Cont.)
Parameter
Condition
Min
Typ
Max
Units
−50
—
50
µA
1
—
—
VPP
IOUTp, IOUTn, QOUTp,
QOUTn Common Mode
Voltage
0.65
—
0.85
V
IOUTp, IOUTn, QOUTp,
QOUTn DC Offset Voltage
−50
—
50
mV
Analog Control Inputs - AGC1, AGC2
Input Bias Current
1 V < Pin < 4 V
Baseband Outputs - IOUTp, IOUTn, QOUTp, QOUTn
Output Swing
Loaded with 2 kΩ differential across
IOUTp, IOUTn, and QOUTp, QOUTn
(Sheet 3 of 3)
Table 4
AC Characteristics of the L64733C
Parameter
Condition
Min
Typ
Max
Units
RFIN Input Freq. Range
Meets all following AC specs
925
–
2175
MHz
RFIN Single-Carrier
Input Power1
RF level needed to produce 0.59 VPP.
−68
–
−25
dBm
AGC1 Range
1 V < AGC1 < 4 V
50
–
–
dB
AGC2 Range
1 V < AGC2 < 4 V
19
–
–
dB
RFIN referred IP3
(front-end contributions)
AGC1 gain set for
−25 dBm input level
(0.59 VPP output), and
AGC2 set to maximum
gain (VAGC2 = 1 V). Two
signals at FLO
+ 32 MHz, FLO +
72 MHz
–
–
–
10.5
11.5
10.5
–
–
–
dBm
dBm
dBm
Baseband 1 dB
Compression Point
IOUTp, IOUTn, QOUTp, QOUTn have
one signal within filter bandwidth
2
–
–
VPP
RFIN Referred IP2
PRFIN = -25 dBm, FLO = 951 MHz
–
15.5
–
dBm
RF Front End
@2175 MHz
@1550MHz
@925 MHz
(Sheet 1 of 3)
L64733C/L64734 Tuner and Satellite Receiver Chipset
27
Table 4
AC Characteristics of the L64733C (Cont.)
Parameter
Condition
Min
Typ
Max
Units
Noise Figure
At maximum gain AGC1, AGC2,
2150 MHz
–
10.8
–
dB
RFIN Return Loss
Complex “75 Ω source” subject to
board, connector parasitics.
–
11
–
dB
LO Leakage Power at
RFIN
950 MHz to 2150 MHz, subject to
board layout
–
-65
–
dBm
Second Harmonic
Rejection
Due to LO-generated 2nd harmonic
–
44
–
dB
Half-Harmonic Rejection
and x 1.5 Harmonic
Rejection2
Due to RFIN-generated 2nd harmonic
–
40
–
dB
@2175 MHz
@1550MHz
@925 MHz
–
2.0
1.0
0.5
–
dB
@2175 MHz
@1550MHz
@925 MHz
–
5.4
7.7
9.5
–
dBm
–
12.0
–
dB
–
8
–
dB
IOUTp, IOUTn, QOUTp,
2 kΩ differential load, IOUTp, IOUTn,
QOUTn Differential Output QOUTp, QOUTn. Expect 20 pF from
Voltage Swing
each pin to GND
1
–
–
VPP
IOUTp, IOUTn, QOUTp,
Per side, IOUTp, IOUTn, QOUTp,
QOUTn Output Impedance QOUTn. To 200 MHz
–
–
50
Ω
Baseband Highpass −3 dB 0.22 µF caps connected from IDCp to
Point
IDCn, and QDCp to QDCn.
–
–
750
Hz
8
–
33
MHz
–
14.5 ·
FFLCLK + 1
–
–
Loop Through
Gain
RFIN referred IP3 (when
Loop-Through enabled)
At PRFIN = −25 dBm
Noise Figure
Return Loss
Subject to board and connector
parasitics
Baseband
LPF Nominal Cutoff
Frequency Range
LPF Nominal Fc
Fc is −3 dB point of filter
(Sheet 2 of 3)
28
L64733C/L64734 Tuner and Satellite Receiver Chipset
Table 4
AC Characteristics of the L64733C (Cont.)
Parameter
Condition
Min
Typ
Max
Units
Baseband Frequency
Response
Deviation from ideal 7th-order
Butterworth, measure to F − 3 dB x 0.7.
Include front-end tilt effects
−0.5
–
0.5
dB
LPF Cutoff Frequency
Accuracy
Measured −3 dB point.
−5.5
−10
–
–
5.5
10
%
%
Quadrature Gain Error
Includes effects from baseband filters
–
–
1.2
dB
Quadrature Phase Error
Measure at 125 kHz
–
–
4
Deg
4
–
7.26
MHz
0.75
1.0
1.5
Vpp
–
2.0
–
V
@8 MHz
@31.4 MHz
Synthesizer
Crystal Frequency Range
XTLOUT Voltage Levels
Measured on 10 pF in parallel with
1 MΩ
XTLOUT DC Level
MODp, MODn Delay
Must assert MOD level within this time
period to ensure that the next PSOUT
period gives correct count. Delay is
with respect to rising edge of PSOUT
(previous count).
–
–
7
nsec
PLLINp, PLLINn and
MODp, MODn Hold Time
With respect to rising edge of PSOUT.
This means that PSOUT need not continue to be asserted after MOD has
given correct count.
0
–
–
nsec
543
–
1180
MHz
–
−55
–
dBc/Hz
–
−75
–
dBc/Hz
–
−95
–
dBc/Hz
925
–
2175
MHz
Local Oscillator
LO Tuning Range
LO Phase Noise, Including 1 kHz offset. Depends on PLL loop
Doubler. Subject to LC tank gain.
implementation.
10 kHz offset. Depends on PLL loop
gain.
100 kHz offset
LO Buffer Frequency
FDOUB = low
Range when overdriven by
external LO
(Sheet 3 of 3)
1.
For symbol rates below 15 MS/s, the maximum input power might be subject to shifting down by
roughly 10 * log(15/Rs[MS/s]) dB due to channel bandwidth reduction.
2. x 1.5 harmonic rejection for FLO = 725 MHz.
L64733C/L64734 Tuner and Satellite Receiver Chipset
29
Table 5
L64733C-48 Pin Description Summary
Mnemonic
Description
Type
AGC1
Automatic Gain Control 1
Input
AGC2
Automatic Gain Control 2
Input
CFLT
Bias Voltage Bypass
CP
Charge Pump
CPG[2:1]
Charge Pump Gain
FB
Feedback Charge Pump Transistor Drive
FDOUB
Frequency Doubler
Input
FLCLK
Filter Clock
Input
GND
Ground (seven pins total)
Input
IDCp
I-Channel DC Offset Correction
(noninverting)
Input
IDCn
I-Channel DC Offset Correction (inverting)
Input
INSEL
RF Port Input Select
Input
IOUTp
I-Channel Baseband Data (noninverting)
Output
IOUTn
I-Channel Baseband Data (inverting)
Output
LOBUF
Local Oscillator Buffer Select
Input
LODIV
Local Oscillator Buffer Division Ratio Select
Input
MODp
Prescaler Modulus (noninverting)
Input
MODn
Prescaler Modulus (inverting)
Input
PLLINp
Phase Detector (noninverting)
Input
PLLINn
Phase Detector (inverting)
Input
PSOUTp
Prescaler (noninverting)
Output
PSOUTn
Prescaler (inverting)
Output
QDCp
Q-Channel DC Offset Correction
(noninverting)
(Sheet 1 of 2)
30
L64733C/L64734 Tuner and Satellite Receiver Chipset
Bidirectional
Output
Input
Output
Input
Table 5
L64733C-48 Pin Description Summary (Cont.)
Mnemonic
Description
Type
QDCn
Q-Channel DC Offset Correction (inverting)
Input
QOUTp
Q-Channel Baseband Data (noninverting)
Output
QOUTn
Q-Channel Baseband Data (inverting)
Output
RFINp
RF Input (noninverting)
Input
RFINn
RF Input (inverting)
Input
RFOUT
RF Output (Loop-Through)
TANKp
Oscillator Tank Port (noninverting)
Input
TANKn
Oscillator Tank Port (inverting)
Input
VCC
Power (six pins total)
Input
VRLO
Local Oscillator Regulator Bypass
XTLp
Crystal Oscillator Port (noninverting)
Input
XTLn
Crystal Oscillator Port (inverting)
Input
XTLOUT
Crystal Out
Output
Bidirectional
Output
(Sheet 2 of 2)
L64733C/L64734 Tuner and Satellite Receiver Chipset
31
Table 6
L64733C-44 Pin Description Summary
Mnemonic
Description
Type
AGC1
Automatic Gain Control 1
Input
AGC2
Automatic Gain Control 2
Input
CFLT
Bias Voltage Bypass
CP
Charge Pump
CPG[2:1]
Charge Pump Gain
FB
Feedback Charge Pump Transistor Drive
FDOUB
Frequency Doubler
Input
FLCLK
Filter Clock
Input
GND
Ground (three pins total)
Input
IDCp
I-Channel DC Offset Correction
(noninverting)
Input
IDCn
I-Channel DC Offset Correction (inverting)
Input
INSEL
RF Port Input Select
Input
IOUTp
I-Channel Baseband Data (noninverting)
Output
IOUTn
I-Channel Baseband Data (inverting)
Output
LOBUF
Local Oscillator Buffer Select
Input
LODIV
Local Oscillator Buffer Division Ratio Select
Input
MODp
Prescaler Modulus (noninverting)
Input
MODn
Prescaler Modulus (inverting)
Input
PLLINp
Phase Detector (noninverting)
Input
PLLINn
Phase Detector (inverting)
Input
PSOUTp
Prescaler (noninverting)
Output
PSOUTn
Prescaler (inverting)
Output
QDCp
Q-Channel DC Offset Correction
(noninverting)
(Sheet 1 of 2)
32
L64733C/L64734 Tuner and Satellite Receiver Chipset
Bidirectional
Output
Input
Output
Input
Table 6
L64733C-44 Pin Description Summary (Cont.)
Mnemonic
Description
Type
QDCn
Q-Channel DC Offset Correction (inverting)
Input
QOUTp
Q-Channel Baseband Data (noninverting)
Output
QOUTn
Q-Channel Baseband Data (inverting)
Output
RFINp
RF Input (noninverting)
Input
RFINn
RF Input (inverting)
Input
RFOUT
RF Output (Loop-Through)
TANKp
Oscillator Tank Port (noninverting)
Input
TANKn
Oscillator Tank Port (inverting)
Input
VCC
Power (six pins total)
Input
VRLO
Local Oscillator Regulator Bypass
XTLp
Crystal Oscillator Port (noninverting)
Input
XTLn
Crystal Oscillator Port (inverting)
Input
XTLOUT
Crystal Out
Output
Bidirectional
Output
(Sheet 2 of 2)
L64734 Electrical Specifications
This section contains the electrical parameters for the L64734. Table 7
lists the absolute maximum values. Exceeding the values listed can
cause damage to the L64734. Table 8 gives the recommended operating
supply voltage and temperature conditions. Table 9 shows the pin
capacitance, Table 10 gives the DC characteristics, and Table 11
summarizes the pins.
L64733C/L64734 Tuner and Satellite Receiver Chipset
33
Table 7
L64734 Absolute Maximum Rating (Referenced to VSS)
Limits1
Units
−0.3 to + 3.9
V
−1.0 to VDD + 0.3
V
−1.0 to 6.5
V
±10
mA
−40 to +125
°C
Symbol Parameter
VDD
DC Supply Voltage
VIN
LVTTL Input Voltage
VIN
5 V Compatible Input Voltage
IIN
DC Input Current
TSTG
Storage Temperature Range (Plastic)
1. Note that the ratings in this table are those beyond which permanent device
damage is likely to occur. Do not use these values as the limits for normal
device operation.
Table 8
L64734 Recommended Operating Conditions
Symbol Parameter
VDD
DC Supply Voltage
TA
Operating Ambient Temperature Range
(Commercial)
Tj
Junction Temperature
Θjc
Junction to Case Thermal Resistance2
Limits1
Units
+3.14 to 3.47
V
0 to +70
°C
+125
°C
7
°C/watt
1. For normal device operation, adhere to the limits in this table. Sustained
operation of a device at conditions exceeding these values, even if they are
within the absolute maximum rating limits, can result in permanent device
damage or impaired device reliability. Device functionality to stated DC and
AC limits is not guaranteed if recommended operating conditions are
exceeded.
2. The junction to case thermal resistance is valid for measurements in an
isothermal environment including the board and package.
Table 9
Symbol
CIN
COUT
L64734 Capacitance
Parameter1
Max
Units
Input Capacitance
5
pF
Output Capacitance
5
pF
1. Measurement conditions are VIN = 3.3 V, TA = 25 ˚C, and
clock frequency = 1 MHz.
34
L64733C/L64734 Tuner and Satellite Receiver Chipset
Table 10
DC Characteristics of the L64734
Symbol
Parameter
VDD
Supply Voltage
VIL
Input Voltage LOW
VIH
Input Voltage HIGH
Condition1
Min
Typ
Max
Units
3.0
3.3
3.6
V
VSS
− 0.5
–
0.8
V
LVTTL Com/Ind/Mil
Temp Range
2.0
–
VDD
+ 0.3
V
5 V compatible
2.0
–
5.5
V
–
1.4
2.0
V
VT
Switching Threshold
IIL
Input Current Leakage
VDD = Max,
VIN = VDD or VSS
−10
±1
10
µA
IIPU
Input Current Leakage
with Pull-up
VIN = VSS
−62
−215
−384
µA
IIPD
Input Current Leakage
with Pull-down
VIN = VDD
−62
−215
−384
µA
VOH
Output Voltage HIGH
IOH = −1.0, −2.0, −4.0,
−6.0, −8.0, −12.0 mA
2.4
–
VDD
V
VOL
Output Voltage LOW
IOH = 1.0, 2.0, 4.0, 6.0,
8.0, 12.0 mA
—
0.2
0.4
V
IOZ
3-State Output Leakage
Current
VDD = Max,
VOUT = VSS or 3.5 V
-10
±1
10
µA
IDD
Quiescent Supply
Current
VIN = VDD or VSS
2
mA
ICC
Dynamic Supply Current f = MHz, VDD = Max
–
290
–
mA
VCM
Midpoint of PSOUTp,
PSOUTn inputs
–
2.4
–
V
VIH_PECL
Input Voltage High Level
(DC)
VCM
+ 50 mV
–
–
V
PSOUTp − PSOUTn =
50 mV
–
(Sheet 1 of 2)
L64733C/L64734 Tuner and Satellite Receiver Chipset
35
Table 10
DC Characteristics of the L64734 (Cont.)
Symbol
Parameter
Condition1
VIL_PECL
Input Voltage Low Level
(DC)
PSOUTp − PSOUTn =
50 mV
IIL_PECL
Input Low Current
IIH_PECL
Input High Current
Min
Typ
Max
Units
–
–
VCM −
50 mV
V
VIN = VSS
−10
–
–
µA
VIN = VDD
–
–
+10
µA
–
1.2
–
V
VRESO_LVDS Output Voltage on pin
RESO_LVDS
VOH_LVDS
Output Voltage High
Level (DC)
On PLLINp/PLLINn,
MODp/MODn signals
1.253
1.373
1.437
V
VOL_LVDS
Output Voltage Low
Level (DC)
On PLLINp/PLLINn,
MODp/MODn signals
1.030
1.032
1.059
V
(Sheet 2 of 2)
1. Specified at VDD = 3.3 V ± 5% at ambient temperature over the specified range.
Table 11
L64734 Pin Description Summary
Mnemonic
Description
Type
ADCVDDI/Q
ADC Power
Input
ADCVSSI/Q
ADC Analog Ground
Input
AGC1, AGC2
Power Control
Outputs
BCLKOUT
Byte Clock Out
Output
CLK
IVIN/QVIN Input Clock
CO[7:0]
Channel Data Out
COEn
Channel Output Enable
DVALIDOUT
Valid Data Out
Output
ERROROUTn
Error Detection Flag
Output
FBUFVDD
Analog Supply
Input
FBUFVSS
Analog Ground
Input
(Sheet 1 of 3)
36
L64733C/L64734 Tuner and Satellite Receiver Chipset
Input
Output
Input
Table 11
L64734 Pin Description Summary (Cont.)
Mnemonic
Description
FDOUB
Frequency Doubler
Output, 3-State
FLCLK
Filter Control Clock
Output
FSTARTOUT
Frame Start Output
Output
IBIAS
ADC Bias Current
Output
IBYPASS[5:0]
I Channel Data (ADC bypassed)
Inputs
IDDTN
Test
Input
INSEL
RF Input Select
Output
INTn
Interrupt
Output
IVINn, IVINp
I Channel Data
LCLK
Decimated Clock Output
LP2
Input to VCO
MODp, MODn
Modulus Selector
Outputs
PCLK
PLL Clock Output
Output
PLLAGND
PLL Analog Ground
PLLINn, PLLINp
PLL Differential Counter M
PLLVDD
PLL Power
Input
PLLVSS
PLL Ground
Input
PSOUTp, PSOUTn Prescaler Output
Type
Input
Output
Input
Input
Outputs
Outputs
QBYPASS[5:0]
Q Channel Data (ADC bypassed)
Input
QVINn, QVINp
Q Channel Data
Input
RESET
Reset
Input
RESO_LVDS
LVDS Buffers Precision Resistor
SADR[1:0]
Serial Address
SCLK
Serial Clock
Output
Input
Bidirectional
(Sheet 2 of 3)
L64733C/L64734 Tuner and Satellite Receiver Chipset
37
Table 11
L64734 Pin Description Summary (Cont.)
Mnemonic
Description
Type
SDATA
Serial Data
Bidirectional
VREF_LVDS
LVDS Buffers Reference Voltage
Input
XCTR_IN
Control Input
Input
XCTR[3:0]
Control Output/Sync Status Flag
XOIN
Crystal Oscillator In
XOOUT
Crystal Oscillator Out
Output
Input
Output
(Sheet 3 of 3)
This section includes AC timing information for the L64734. During AC
testing, HIGH inputs are driven to 3.0 V and LOW inputs are driven to
0 V. For transitions between HIGH, LOW, and invalid states, timing
measurements are made at 1.5 V, as shown in Figure 8.
Figure 8
AC Test Load and Waveform for Standard Outputs
Test
Point
Output
1.5 V
CL = 15 pF
For 3-state outputs, timing measurements are made from the point at
which the output turns ON or OFF. An output is ON when its voltage is
greater than 2.5 V or less than 0.5 V. An output is OFF when its voltage
is less than VDD − 0.5 V or greater than 0.5 V, as shown in Figure 9.
38
L64733C/L64734 Tuner and Satellite Receiver Chipset
Figure 9
Test
Point
AC Test Load and Waveforms for 3-State Outputs
Iref = 20 mA
Output
Vref = 1.5 V
Vref
VDD −0.5 V
0.5 V
2.5 V
0.5 V
55 pF
Iref = −20 mA
Synchronous timing is shown in Figure 10. Synchronous inputs must
have a setup and hold relationship with respect to the clock signal that
samples them. Synchronous outputs have a delay from the clock edge
that asserts them.
Figure 10
L64734 Synchronous AC Timing
1
2
3
PCLK
CLK
4
5
INPUTS
6
OUTPUTS
The reset pulse requirements are shown in Figure 11.
Figure 11
L64734 RESET Timing Diagram
7
8
RESET
Figure 12 shows the relationship of the L64734 3-state signals to the
COEn signal.
L64733C/L64734 Tuner and Satellite Receiver Chipset
39
Figure 12
L64734 Bus 3-State Delay Timing
COEn
9
9
CO
FSTARTOUT
ERROROUTn
DVALIDOUT
BCLKOUT
Figure 13 shows the relationship of the L64733C PSOUTp and PSOUTn
prescaler signals to the signals fed back to the L64733C from the L64734
to control the synthesizer.
Figure 13
L64734 Synchronous AC Timing - Synthesizer Control
10
11
12
PSOUTp
PSOUTn
13
PLLINp, MODp
PLLINn, MODn
The numbers in the first column of Table 12 refer to the timing
parameters shown in the preceding figures. All parameters in the timing
tables apply for TA = 0 °C to 70 °C and a capacitive load of 15 pF.
40
L64733C/L64734 Tuner and Satellite Receiver Chipset
Table 12
L64734 AC Timing Parameters
90 MHz
Parameter
Description
Min
Max
11.1 33.31
Units
1
tCYCLE
Clock Cycle for PCLK
ns
2
tPWH
Clock Pulse Width HIGH
6
–
ns
3
tPWL
Clock Pulse Width LOW
5
–
ns
4
tS
Input Setup Time to CLK
4
–
ns
5
tH
Input Hold to CLK
4
–
ns
6
tODS
Output Delay from PCLK, serial
mode
3
8
ns
6
tODP
Output Delay from BCLKOUT,
parallel mode
3
–
PCLK
cycles
7
tRWH
Reset Pulse Width HIGH
3
–
CLK cycles
8
tWK
Wake-Up Time
280
–
CLK cycles
9
TDLY
Delay from COEn
–
6
ns
10
tCYCLE_PS
Clock Cycle for PSOUTp,
PSOUTn clock
14
35
ns
11
tPWH_PS
PSOUT Clock Pulse Width HIGH
6
–
ns
12
tPWL_PS
PSOUT Clock Pulse Width LOW
6
–
ns
1. Minimum Fs (sampling clock = 30 MHz).
L64733C/L64734 Tuner and Satellite Receiver Chipset
41
L64733C/734 Chipset Ordering Information
The L64733C-48 is available in a 48-pin TQFP package, the
L64733C-44 is available in a 44-pin MLF2 package, and the L64734 is
available in a 100-pin PQFP package. They are ordered as a set.
Table 13 gives ordering information for the chipset.
Table 13
L64733C/734 Chipset Ordering Information
Order Number
Package Type
Kit 733x 734y
x = 733 version 48-pin TQFP (L64733C-48)
44-pin MLF2 (L64733C-44)
y = 734 version 100-pin PQFP (L64734)
Operating Range
Commercial
The tables and figures that follow provide pinouts and mechanical
drawings for each package in the chipset.
42
L64733C/L64734 Tuner and Satellite Receiver Chipset
L64733C-48 Pinout and Packaging Information
The following subsections provide pinout and packaging information for
the 48-pin L64733C chip.
L64733C-48 Pinouts
Figure 14 gives the pinout for the 48-pin TQFP L64733C-48 package.
Figure 14
L64733C 48-Pin TQFP Pinout
PSOUTp
PSOUTn
VCC
GND
GND
TANKn
VRLO
TANKp
VCC
GND
FB
CP
37
38
39
40
41
42
43
44
45
46
47
48
VCC
CFLT
XTLn
XTLp
GND
VCC
RFINn
RFINp
GND
GNDSUB
QDCn
QDCp
1
2
3
4
5
6
7
8
9
10
11
12
Top View
24
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
PLLINn
PLLINp
MODn
MODp
LODIV
IOUTp
IOUTn
VCC
QOUTp
QOUTn
FDOUB
FLCLK
INSEL
AGC2
AGC1
CPG2
XTLOUT
VCC
CPG1
RFOUT
GND
LOBUF
IDCp
IDCn
L64733C/L64734 Tuner and Satellite Receiver Chipset
43
L64733C-48 Mechanical Drawing
Figure 15 is a mechanical drawing for the 48-pin TQFP L64733C-48
package.
Figure 15
L64733C-48 48-pin TQFP Mechanical Drawing
BOTTOM VIEW
TOP VIEW
D
D/2
D1
.15 MIN.
D1/2
E1/2
.50 MAX.
EXPOSED PAD
CORNER TAB DETAIL
A
e
E1
E
EVEN LEAD SIDES
E/2
e/2
SEE DETAIL “A”
8 PLACES
A
11–13°
0° MIN.
M
SEE DETAIL “B”
b
WITH LEAD FINISH
A2
A1
DATUM
PLANE
-H0.08 R. MIN.
0–7°
0.20 MIN.
0.09/0.20
0.09/0.16
b
1
BASE METAL
Notes:
1. All dimensioning and tolerancing conform to Ansi Y14.5–1982.
2. Datum plane – H – is located at mold parting line and coincident
with lead, where lead exits plastic body at bottom of parting line.
3. Dimensions D1 and E1 do not include mold protrusion. allowable mold
protrusion is 0.254 mm on D1 and E1 dimensions.
4. The top of package is smaller than the bottom of package by
0.15 millimeters.
5. Dimension B does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08 mm total in excess of the B dimension at
maximum material condition.
6. Controlling dimension: millimeter.
7. Maximum allowable die thickness to be assembled in this package
family is 0.30 millimeters.
8. This outline conforms to Jedec Publication 95 Registration MO–136,
variations AC and AE.
9. Exposed die pad shall be coplanar with bottom of package within
2 mils (0.05 mm).
10. Metal area of exposed die pad shall be within 0.3 mm of the nominal
die pad size.
44
DETAIL “A”
0.08/0.20 R.
0.25
GAUGE PLANE
L
1.00 REF.
DETAIL “B”
S
Y
M
B
O
L
A
A1
A2
D
D1
E
E1
L
M
N
e
b
b1
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
AE
MIN.
NOM.
0.05
0.95
0.10
1.00
9.00 BSC.
7.00 BSC.
9.00 BSC.
7.00 BSC.
0.60
0.45
0.14
0.17
0.17
L64733C/L64734 Tuner and Satellite Receiver Chipset
48
0.5 BSC.
0.22
0.20
MAX.
1.20
0.15
1.05
0.75
0.27
0.23
L64733C-44 Pinout and Packaging Information
The following subsections provide pinout and packaging information for
the 44-pin L64733C chip.
L6433C-44 Pinout
Figure 16 gives the pinout for the 44-pin QFN L64733-44 package.
L64733 44-Pin QFN Pinout
44
43
42
41
40
39
38
37
36
35
34
CP
VTUNE
VCC
VCC
NC
VRLO
NC
NC
VCC
PSOUTn
PSOUTp
Figure 16
L6473
44 Pin QFN
Top View
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
PLLINn
PLLINp
MODn
MODp
IOUTp
IOUTn
VCC
QOUTp
QOUTn
FDIV
FLCLK
IDCn
IDCp
NC
LOCK
CPG1/VCO0
VCC
XTALOUT
CPG2/VCO1
AGC1
AGC2
ICPHI/VCO2
XTALn
XTALp
CFLT
VCC
NC
VCC
RFINn
RFINp
NC
QDCn
QDCP
L64733C/L64734 Tuner and Satellite Receiver Chipset
45
L64733C-44 Mechanical Drawings
Figure 17 is a mechanical drawing for the 44-pin QFN L64733-44
package.
Figure 17
46
L64733C-44 44-pin QFN Mechanical Drawing
L64733C/L64734 Tuner and Satellite Receiver Chipset
Figure 17
L64753-44 44-pin QFN Mechanical Drawing (Cont.)
L64733C/L64734 Tuner and Satellite Receiver Chipset
47
L64734 Pinout and Packaging Information
The following subsections provide pinout and packaging information for
the L64734.
L64734 Pinouts
Figure 18 gives the pinout for the 100-pin PQFP L64734 package.
L64734 100-Pin PQFP Pinout
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
VDD
PLLVSS
LP2
PLLAGND
PLLVDD
PCLK
LCLK
VSS
VDD
CO[0]
CO[1]
CO[2]
CO[3]
VSS
VDD
CO[4]
CO[5]
CO[6]
CO[7]
VSS
VDD
BCLKOUT
DVALIDOUT
FSTARTOUT
ERROROUTn
VSS
VDD
COEn
IDDTN
Figure 18
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VDD
VSS
ADCVDDI
IVINp
IVINn
ADCVSSI
FBUFVDD
IBIAS
FBUFVSS
ADCVDDQ
QVINp
QVINn
ADCVSSQ
VDD
VSS
FDOUB
FLCLK
INSEL
AGC2
AGC1
VDD
VSS
XCTR[1]
XCTR[0]
XCTR[2]
XCTR[3]
XCTR_IN
VDD
VSS
IBYPASS[5]
SADR[1]
SADR[0]
VDD
VSS
SDATA
SCLK
INTn
RESET
VDD
VSS
PSOUTn
PSOUTp
VDD
VSS
PLLINn
PLLINp
RESO_LVDS
VREF_LVDS
MODn
MODp
48
L64733C/L64734 Tuner and Satellite Receiver Chipset
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
XOOUT
XOIN
VSS
CLK
VDD
QBYPASS[0]
QBYPASS[1]
VSS
VDD
QBYPASS[2]
QBYPASS[3]
QBYPASS[4]
QBYPASS[5]
IBYPASS[0]
VSS
VDD
IBYPASS[1]
IBYPASS[2]
IBYPASS[3]
IBYPASS[4]
L64734 Mechanical Drawings
Figure 19 and Figure 20 show the mechanical drawings for the 100-pin
PQFP L64734 package.
Figure 19
100-pin PQFP (UD) Mechanical Drawing
MD97.UD-1
Important:
This drawing may not be the latest version. For board layout and manufacturing, obtain the
most recent engineering drawings from your LSI Logic marketing representative.
L64733C/L64734 Tuner and Satellite Receiver Chipset
49
Figure 20
100-pin PQFP (UD) Mechanical Drawing (Cont.)
MD97.UD-2
Important:
50
This drawing may not be the latest version. For board layout and manufacturing, obtain the
most recent engineering drawings from your LSI Logic marketing representative by
requesting the outline drawing for package code UD.
L64733C/L64734 Tuner and Satellite Receiver Chipset
Notes
L64733C/L64734 Tuner and Satellite Receiver Chipset
51
Sales Offices and Design Resource Centers
LSI Logic Corporation
Corporate Headquarters
Tel: 408.433.8000
Fax: 408.433.8989
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Tel: 630.954.2234
Fax: 630.954.2235
NORTH AMERICA
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Tel: 270.793.0010
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♦ Tel: 949.809.4600
Fax: 949.809.4444
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Tel: 858.467.6981
Fax: 858.496.0548
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♦ Tel: 408.433.8000
Fax: 408.954.3353
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Tel: 858.350.5560
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♦ Tel: 303.447.3800
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Tel: 719.533.7000
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LSI Logic GmbH
♦ Tel: 49.89.4.58.33.0
Fax: 49.89.4.58.33.108
Stuttgart
♦ Tel: 49.711.13.96.90
Korea
Seoul
LSI Logic Corporation of
Korea Ltd
Tel: 82.2.528.3400
Fax: 82.2.528.2250
The Netherlands
Eindhoven
LSI Logic Europe Ltd
Tel: 31.40.265.3580
Fax: 31.40.296.2109
Singapore
Singapore
LSI Logic Pte Ltd
Tel: 65.334.9061
Fax: 65.334.4749
Sweden
Stockholm
LSI Logic AB
♦ Tel: 46.8.444.15.00
Fax: 46.8.750.66.47
Taiwan
Taipei
LSI Logic Asia, Inc.
Taiwan Branch
Tel: 886.2.2718.7828
Fax: 886.2.2718.8869
United Kingdom
Bracknell
LSI Logic Europe Ltd
♦ Tel: 44.1344.426544
Fax: 44.1344.481039
Fax: 49.711.86.61.428
New York
Fairport
Tel: 716.218.0020
Fax: 716.218.9010
North Carolina
Raleigh
Tel: 919.785.4520
Fax: 919.783.8909
Oregon
Beaverton
Tel: 503.645.0589
Fax: 503.645.6612
Italy
Milan
LSI Logic S.P.A.
♦ Tel: 39.039.687371
Fax: 39.039.6057867
♦ Sales Offices with
Design Resource Centers
Japan
Tokyo
LSI Logic K.K.
♦ Tel: 81.3.5463.7821
Fax: 81.3.5463.7820
Osaka
♦ Tel: 81.6.947.5281
Fax: 81.6.947.5287
Visit us at our web site: http://www.lsilogic.com
ISO 9000 Certified
Printed in USA
Order No. I15042
Doc. No. DB08-000162-00
LSI Logic logo design is a registered trademark of LSI Logic
Corporation. All other brand and product names may be
trademarks of their respective companies.
LSI Logic Corporation reserves the right to make changes
to any products and services herein at any time without
notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product
or service described herein, except as expressly agreed to
in writing by LSI Logic; nor does the purchase, lease, or use
of a product or service from LSI Logic convey a license
under any patent rights, copyrights, trademark rights, or any
other of the intellectual property rights of LSI Logic or of
third parties.