Ordering number : ENN*6790 CMOS IC LC4104C-T2A LCD Dot Matrix Segment Driver for STN Displays Preliminary Overview The LC4104C-T2A is a segment driver IC for large-scale dot matrix LCD displays. The LC4104C-T2A latches 160bits of display data transferred from the controller over a 4- or 8-bit parallel interface and generates the LCD drive signals. In conjunction with the LC4102C-T2A common driver, the LC4104C-T2A forms a chip set that can drive large-screen LCD panels. Features • • • • • • • • • High-voltage CMOS (P-sub) process LCD drive voltage: 36 V Logic system power-supply voltage: 2.7 to 5.5 V Maximum fcp: 12 MHz (VDD = 5 V ±10%), 10 MHz (VDD = 2.7 to 4.5 V) Parallel input circuit can be switched between 4 and 8 bits. Output directionality switching DISPOFF function (Holds the LCD drive voltage at a fixed level.) Display duty ratios: 1/160 to 1/480 Package: TCP (Tape Carrier Package) Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 20702TN (OT) No. 6790-1/8 LC4104C-T2A V0 V2 V3 V5 O160 O159 O158 O4 O3 O2 O1 Block Diagram V0 V2 V3 V5 4 Level LCD Drive Circuit (160bits) Output Control VDDH VDDH Level Shifter DISP M 2nd Latch (160bits) LOAD 1st Latch (8bits × 20) BS VDD — D0 Bits Control Address Decoder VSS D7 CP R/L Address Counter TEST Chip Disable & Latch Control EIO1 EIO2 A1367 Specifications The following electrical characteristics apply when sealed in a SANYO standard PGA-208 package. Absolute Maximum Ratings at VSS = 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max –0.3 to +7 V Maximum supply voltage VDDH max –0.3 to +40 V Maximum supply voltage VSS max –0.3 to +0.3 V –0.3 to VDD + 0.3 V Input voltage VIN Input voltage V0, V2 VDDH – 7 to VDDH + 0.3 V Input voltage V3 V3 –0.3 to VSS + 7 V Input voltage V5 V5 –0.3 to +0.3 V D0 to D7, LOAD, CP, R/L, TEST, DISP, M, EIO1, EIO2, BS V0, V2 Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Note: V0, V2, V3, and V5 must obey the following relationships: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS. No. 6790-2/8 LC4104C-T2A Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V Parameter Symbol Conditions Ratings min typ Unit max Supply voltage VDD 2.7 5.5 V Supply voltage VDDH 14 36 V Supply voltage VSS 0 Input high-level voltage VIH D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, EIO1, EIO2 Input low-level voltage VIL D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, EIO1, EIO2 Input voltage V0, V2 Input voltage V3 V0, V2 V3 Input voltage V5 V5 V 0.8 VDD VDD V 0 0.2 VDD V VDDH – 7 VDDH V 0 VSSH + 7 V 0 V Note: V0, V2, V3, and V5 must obey the following relationships: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS. At power on: First turn on the logic system power supply and then turn on the high-voltage system power supply; alternatively, turn both on at the same time. At power off: First turn off the high-voltage system power supply and then turn off the logic system power supply; alternatively, turn both off at the same time. Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 5 V ± 10% Parameter CP clock frequency Symbol fcp Conditions Ratings min typ CP max 12 Unit MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 20 ns Low-level clock pulse width tw (cpL) CP 20 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 10 ns DATA/CP hold time tho (cp) CP, D0 to D7 10 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 24 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below. 1 – tw (cph) – tw (cpl) fcp ➀: tr, tf < 2 ②: tr, tf ≤ 50 ns Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 2.7 to 4.5 V Parameter CP clock frequency Symbol fcp Conditions Ratings min CP typ max 10 Unit MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 37 ns Low-level clock pulse width tw (cpL) CP 37 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 35 ns DATA/CP hold time tho (cp) CP, D0 to D7 35 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 30 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below. 1 – tw (cph) – tw (cpl) fcp ➀: tr, tf < 2 ②: tr, tf ≤ 50 ns No. 6790-3/8 LC4104C-T2A Electrical Characteristics at Ta = –20 to +75°C, VDD = 2.7 to 5.5 V, VSS = 0 V Parameter Input high-level current Symbol Ratings Conditions min max VIN = VDD: D0 to D7, LOAD, CP, R/L, M, DISP, EIO1, EIO2, BS, TEST IIH IIL1 VIN = VSS: D0 to D7, LOAD, CP, R/L, M, DISP, EIO1, EIO2, BS IIL2 VIN = VSS: TEST Output high-level voltage VOH IO = –0.4 mA: EIO1, EIO2 Output low-level voltage VOL IO = 0.4 mA: EIO1, EIO2 Output on resistance ROUT VDDH = 36 V*1, V0 – VO = 0.5 V, V2 – VO = 0.5 V, VO – V3 = 0.5 V, VO – V5 = 0.5 V: O1 to O160 Input low-level current Current drain typ 5 Unit µA –5 µA –500 VDD – 0.4 VDD V VSS 0.4 V 1 3 kΩ IDD VDD = 2.7 to 5.5 V 5.0 mA IDDH VDD = 2.7 to 5.5 V, VDDH = 32 V*2, VDD = 5 V ± 10%, VDDH = 36 V 2.0 mA 2.0 mA *3 500 µA IST Note: 1. VO is the voltage applied for an on output, V0 = VDDH, V2 = 18/20 (VDDH – VSS), V3 = 2/20 (VDDH – VSS), V5 = VSS 2. LOAD = 28 kHz, CP = 10 MHz, M = 75 Hz Alternatively: No output load and with the inputs VIH = VDD and VIL = VSS. 3. The current drain in standby mode. Note that the EIOn pins must be held at VDD. Switching Characteristics at Ta = –20 to +75°C, VSS = 0 V, VDD = 5 V ± 10% Parameter Symbol Ratings Conditions min typ max Unit EIO output delay time td (eo) 30 pF capacitive load: CP, EIO1, EIO2 40 ns LD/EIO output delay time td (leo) 30 pF capacitive load: LOAD, EIO1, EIO2 70 ns LOAD/on delay time td (ldo) 100 pF capacitive load: LOAD, O1 to O160 3 µs M/on delay time td (mo) 100 pF capacitive load: M, O1 to O160 3 µs Switching Characteristics at Ta = –20 to +75°C, VSS = 0 V, VDD = 2.7 to 4.5 V Parameter Symbol Ratings Conditions min EIO output delay time td (eo) 30 pF capacitive load: CP, EIO1, EIO2 LD/EIO output delay time td (leo) 30 pF capacitive load: LOAD, EIO1, EIO2 LOAD/on delay time td (ldo) M/on delay time td (mo) typ max Unit 80 ns 130 ns 100 pF capacitive load: LOAD, O1 to O160 3 µs 100 pF capacitive load: M, O1 to O160 3 µs Timing Chart tw(ldH) LOAD tr(ld) 0.8VDD 0.2VDD tf(ld) tsu(ld) tho(ld) tw(cpH) tr(cp) tf(cp) CP tsu(cp) tho(cp) tw(cpL) D0 to D7 td(mo) M td(ldo) On td(leo) EIOn (output) (Input to the next stage) td(eo) tsu(ei) A13677 No. 6790-4/8 LC4104C-T2A Pin Functions Symbol I/O Function LCD drive outputs O1 to O160 O M Data DISP H H H On V0 H L H V2 L L H V3 L H H V5 * * L V5 *: Don’t care. V0 I V0 level drive voltage supply (selected level) V2 I V2 level drive voltage supply (unselected level) V3 I V3 level drive voltage supply (unselected level) V5 level drive voltage supply (selected level) V5 I VDDH — High-voltage system power supply. VDD — Logic system power supply. VSS — GND DISP I LCD off function. All outputs go to the V5 level when this pin is low. M I Alternation signal input Enable I/O R/L EIO1 EIO2 EIO1 I/O L In Out EIO2 I/O H Out In Enable input: The enable input at the first stage is fixed at VSS. For succeeding stages, the enable input is connected to the enable output from the preceding stage. Enable output: Connected to the enable input of the next stage when cascode connection is used. CP I Data acquisition clock (falling edge) LOAD I Data load clock (falling edge) TEST I Test input. Must be tied high in normal use.* Data shift direction setting R/L BS O2 ↑ D6 O3 ↑ D5 O4 ↑ D4 →... O157 ↑ D3 O158 ↑ D2 O159 ↑ D1 O160 ↑ D0 O1 ↑ D0 O2 ↑ D1 O3 ↑ D2 O4 ↑ D3 . . .← H O157 ↑ D4 O158 ↑ D5 O159 ↑ D6 O160 ↑ D7 O1 ↑ D3 O2 ↑ D2 O3 ↑ D1 O4 ↑ D0 →... L O157 ↑ D3 O158 ↑ D2 O159 ↑ D1 O160 ↑ D0 O1 ↑ D0 O2 ↑ D1 O3 ↑ D2 O4 ↑ D3 . . .← O157 ↑ D0 O158 ↑ D1 O159 ↑ D2 O160 ↑ D3 L H R/L I O1 to O160 outputs O1 ↑ D7 L H D0 to D7 I Parallel data inputs BS I Input bus setting. Set high for 8-bit input, low for 4-bit input. For 4-bit input, D0 to D3 are used for data input and D4 to D7 must be tied to ground. No. 6790-5/8 LC4104C-T2A Pin Assignment DUMMY OUT160 OUT159 OUT158 V5 V3 VDDH V2 V0 D0 D1 D2 D3 D4 D5 D6 LC4104C-T2A (CHIP Top VIEW) D7 VDD EIO2 EIO1 CP LOAD M DISP R/L BS VSS VDDH V0 V2 V3 V5 OUT3 OUT2 OUT1 DUMMY A13678 Note: This figure shows the chip pattern surface as seen from abobe. This figure dose not stipulate the TCP package. No. 6790-6/8 1.2±0.05(SL) 3.7(Cut line) 10.3±0.05 1.7±0.3(SR) 8.5±0.3(SR) 6.7±0.05(SL) 4.9±0.05(SL) 1.2±0.05(SL) 2.0±0.05(SL) 1.2±0.05(SL) 0.6 MAX 0.6 MAX 1.7±0.1(SL) 0.6 MAX 0.4±0.05 VSS VDDH V2 V0 BS DISP R/L CP M EI01 LOAD EIO2 VDD D7 D6 D5 D4 D3 D2 D1 V0 D0 15.0 V2 V5 V3 VDDH 0.3±0.05 19.8±0.1 24.0±0.055 12.55±0.1(SL) V3 V5 19.8±0.1 12.55±0.1(SL) 0.14(P)×(162--1)=22.54±0.055 (W=0.09) 23.6±0.05(SL) ø1.0±0.05 1.7±0.1(SL) 0.4±0.02 0.6±0.02 u) 0.1 ø 2.0 ± (C 1.98(LSI) 1.981±0.03 R0.5±0.05 2.48±0.05 4.75±0.03 R0.8±0.3(SR) 4.0±0.1(SL) 8.0±0.1(SL) 48.175±0.2 42.177±0.07 32.0±0.1 25.5(Cut line) 24.3±0.3(SR) 23.0±0.05(SL) 22.0±0.05(SL) 0.8(P)×(28--1)=21.6±0.055 (W=0.34) 15.55 MAX(Sealing area) 13.55±0.05(Device hole) 13.05(LSI) Device hole Sealing area 0.3 MAX Flex hole LSI chip 0.75 MAX 1.35 MAX LC4104C-T2A Package Dimensions unit: mm LC4104C-T2A No. 6790-7/8 4.75(P)×4=19.0±0.05 4.48 MAX(Sealing area) LC4104C-T2A Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2002. Specifications and information herein are subject to change without notice. PS No. 6790-8/8