Ordering number : EN *5194D CMOS LSI (P-sub) LC4104C LCD Dot Matrix Segment Driver for STN Displays Preliminary Overview The LC4104 is a segment driver LSI for large-scale dot matrix LCD displays. The LC4104 latches 160-bits of display data transferred from the controller over a 4- or 8bit parallel interface and generates the LCD drive signals. In conjunction with the LC4102 common driver, the LC4104 forms a chip set that can drive large-screen LCD panels. Features • • • • • • • • • • • High-voltage CMOS (P-sub) process LCD drive voltage: 36 V Logic system power-supply voltage: 2.7 to 5.5 V Maximum fcp: 12 MHz (VDD = 5 V ±10%), 10 MHz (VDD = 2.7 to 4.5 V) Slim chip (The output pads are located along one of the long sides.) Parallel input circuit can be switched between 4 and 8 bits. Output directionality switching DISPOFF function (Holds the LCD drive voltage at a fixed level.) Display duty ratios: 1/160 to 1/480 Appropriate for COG (chip on glass) mounting. (A gold bump structure is adopted in the pad areas.) LC4104C: Chip product SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 43098HA (OT)/73097HA (OT)/D3095HA (OT) No. 5194-1/9 LC4104C Block Diagram Specifications The following electrical characteristics apply when sealed in a Sanyo standard PGA-208 package. Absolute Maximum Ratings at VSS = 0 V Parameter Symbol Conditions min typ max Unit Maximum supply voltage VDD max –0.3 7 Maximum supply voltage VDDH max –0.3 40 V Maximum supply voltage VSS max –0.3 +0.3 V –0.3 VDD + 0.3 V V D0 to D7, LOAD, CP, R/L, TEST, DISP, M, EIO1, EIO2, BS V Input voltage VIN Input voltage V0, V2 VDDH – 7 VDDH + 0.3 Input voltage V3 V3 –0.3 VSS + 7 V Input voltage V5 V5 –0.3 +0.3 V V0, V2 Operating temperature Topr –20 +75 °C Storage temperature Tstg –55 +125 °C Note: V0, V2, V3, and V5 must obey the following inequalities: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS. No. 5194-2/9 LC4104C Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V Parameter Symbol Conditions min typ max Unit Supply voltage VDD 2.7 5.5 V Supply voltage VDDH 20 36 V Supply voltage VSS 0 Input high-level voltage VIH D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, EIO1, EIO2 Input low-level voltage VIL D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, EIO1, EIO2 Input voltage V0, V2 Input voltage V3 V0, V2 V3 Input voltage V5 V5 V 0.8 VDD VDD V 0 0.2 VDD V VDDH – 7 VDDH V 0 VSSH + 7 V 0 V Note: V0, V2, V3, and V5 must obey the following inequalities: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS. At power on: First turn on the logic system power supply and then turn on the high-voltage system power supply. At power off: First turn off the high-voltage system power supply and then turn off the logic system power supply. Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 5 V ± 10% Parameter CP clock frequency Symbol fcp Conditions min typ CP max Unit 12 MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 20 ns Low-level clock pulse width tw (cpL) CP 20 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 10 ns DATA/CP hold time tho (cp) CP, D0 to D7 10 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 24 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below. 1 – tw (cph) – tw (cpl) fcp ➀: tr, tf < 2 ②: tr, tf ≤ 50 ns Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 2.7 to 4.5 V Parameter CP clock frequency Symbol fcp Conditions min CP typ max Unit 10 MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 37 ns Low-level clock pulse width tw (cpL) CP 37 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 35 ns DATA/CP hold time tho (cp) CP, D0 to D7 35 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 30 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns Note: * The clock rise time (tr) and fall time (tf) must obey inequalities ➀ and ② below. 1 – tw (cph) – tw (cpl) fcp ➀: tr, tf < 2 ②: tr, tf ≤ 50 ns No. 5194-3/9 LC4104C Electrical Characteristics at Ta = –20 to +75°C, VDD = 2.7 to 5.5 V, VSS = 0 V Parameter Input high-level current Symbol IIH Conditions IIL1 VIN = VSS: D0 to D7, LOAD, CP, R/L, M, TEST, DISP, EIO1, EIO2, BS IIL2 VIN = VSS: TEST Output high-level voltage VOH IO = –0.4 mA: EIO1, EIO2 Output low-level voltage VOL IO = 0.4 mA: EIO1, EIO2 Output on resistance ROUT VDDH = 36 V*1, V0 – VO = 0.5 V, V2 – VO = 0.5 V, VO – V3 = 0.5 V, VO – V5 = 0.5 V: O1 to O160 Input low-level current Current drain min typ VIN = VDD: D0 to D7, LOAD, CP, R/L, M, DISP, EIO1, EIO2, BS, TEST max Unit 5 µA –5 µA –500 VDD – 0.4 VDD V VSS 0.4 V 1 3 kΩ IDD VDD = 2.7 to 5.5 V 5.0 mA IDDH VDD = 2.7 to 5.5 V, VDDH = 32 V*2, VDD = 5 V ± 10%, VDDH = 36 V 2.0 mA 2.0 mA *3 500 µA max Unit IST Note: 1. VO is the voltage applied for an on output, V0 = VDDH, V2 = 18/20 (VDDH – VSS), V3 = 2/20 (VDDH – VSS), V5 = VSS 2. LOAD = 28 kHz, CP = 10 MHz, M = 75 Hz Alternatively: No output load and with the inputs VIH = VDD and VIL = VSS. 3. The current drain in standby mode. Note that the EIOn pins must be held at VDD. Switching Characteristics at Ta = –20 to +75°C, VSS = 0 V, VDD = 5 V ± 10% Parameter Symbol EIO output delay time td (eo) 30 pF capacitive load: CP, EIO1, EIO2 Conditions min typ 40 ns LD/EIO output delay time td (leo) 30 pF capacitive load: LOAD, EIO1, EIO2 70 ns LOAD/on delay time td (ldo) 100 pF capacitive load: LOAD, O1 to O160 700 ns M/on delay time td (mo) 100 pF capacitive load: M, O1 to O160 700 ns max Unit Switching Characteristics at Ta = –20 to +75°C, VSS = 0 V, VDD = 2.7 to 4.5 V Parameter Symbol EIO output delay time td (eo) 30 pF capacitive load: CP, EIO1, EIO2 Conditions LD/EIO output delay time td (leo) 30 pF capacitive load: LOAD, EIO1, EIO2 LOAD/on delay time td (ldo) M/on delay time td (mo) min typ 80 ns 130 ns 100 pF capacitive load: LOAD, O1 to O160 3 µs 100 pF capacitive load: M, O1 to O160 3 µs Timing Chart No. 5194-4/9 LC4104C Pin Functions Symbol I/O Function LCD drive outputs O1 to O160 O M Data DISP H H H On V0 H L H V2 L L H V3 L H H V5 * * L V5 *: Don’t care. (Must be held either high or low.) V0 I V0 level drive voltage supply (selected level) V2 I V2 level drive voltage supply (unselected level) V3 I V3 level drive voltage supply (unselected level) V5 I V5 level drive voltage supply (selected level) VDDH — High-voltage system power supply. Pins with the same name must be set to the same potential. VDD — Logic system power supply. VSS — GND DISP I LCD off function. All outputs go to the V5 level when this pin is low. M I Alternation signal input Pins with the same name must be set to the same potential. Enable I/O EIO1 EIO2 R/L EIO1 EIO2 I/O L In Out I/O H Out In Enable input: The enable input at the first stage is fixed at VSS. For succeeding stages, the enable input is connected to the enable output from the preceding stage. Enable output: Connected to the enable input of the next stage when cascode connection is used. CP I Data acquisition clock (falling edge) LOAD I Data load clock (falling edge) TEST I Test input. Must be tied high in normal use.* Data shift direction setting R/L BS O2 ↑ D6 O3 ↑ D5 O4 ↑ D4 →... O157 ↑ D3 O158 ↑ D2 O159 ↑ D1 O160 ↑ D0 O1 ↑ D0 O2 ↑ D1 O3 ↑ D2 O4 ↑ D3 . . .← H O157 ↑ D4 O158 ↑ D5 O159 ↑ D6 O160 ↑ D7 O1 ↑ D3 O2 ↑ D2 O3 ↑ D1 O4 ↑ D0 →... L O157 ↑ D3 O158 ↑ D2 O159 ↑ D1 O160 ↑ D0 O1 ↑ D0 O2 ↑ D1 O3 ↑ D2 O4 ↑ D3 . . .← O157 ↑ D0 O158 ↑ D1 O159 ↑ D2 O160 ↑ D3 L H R/L I O1 to O160 outputs O1 ↑ D7 L H D0 to D7 I Parallel data inputs BS I Input bus setting. Set high for 8-bit input, low for 4-bit input. For 4-bit input, D0 to D3 are used for data input and D4 to D7 must be tied to ground. Note: * This IC is sensitive to ESD care must be used when handling this device. No. 5194-5/9 LC4104C Pin Assignment No. 5194-6/9 LC4104C Pad Coordinates PAD No. Signal X coordinate Y coordinate PAD No. Signal X coordinate 1 O1 –6360.0 825.0 41 O41 –3160.0 Y coordinate 825.0 2 O2 –6280.0 825.0 42 O42 –3080.0 825.0 3 O3 –6200.0 825.0 43 O43 –3000.0 825.0 4 O4 –6120.0 825.0 44 O44 –2920.0 825.0 5 O5 –6040.0 825.0 45 O45 –2840.0 825.0 6 O6 –5960.0 825.0 46 O46 –2760.0 825.0 7 O7 –5880.0 825.0 47 O47 –2680.0 825.0 8 O8 –5800.0 825.0 48 O48 –2600.0 825.0 9 O9 –5720.0 825.0 49 O49 –2520.0 825.0 10 O10 –5640.0 825.0 50 O50 –2440.0 825.0 11 O11 –5560.0 825.0 51 O51 –2360.0 825.0 12 O12 –5480.0 825.0 52 O52 –2280.0 825.0 13 O13 –5400.0 825.0 53 O53 –2200.0 825.0 14 O14 –5320.0 825.0 54 O54 –2120.0 825.0 15 O15 –5240.0 825.0 55 O55 –2040.0 825.0 16 O16 –5160.0 825.0 56 O56 –1960.0 825.0 17 O17 –5080.0 825.0 57 O57 –1880.0 825.0 18 O18 –5000.0 825.0 58 O58 –1800.0 825.0 19 O19 –4920.0 825.0 59 O59 –1720.0 825.0 20 O20 –4840.0 825.0 60 O60 –1640.0 825.0 21 O21 –4760.0 825.0 61 O61 –1560.0 825.0 22 O22 –4680.0 825.0 62 O62 –1480.0 825.0 23 O23 –4600.0 825.0 63 O63 –1400.0 825.0 24 O24 –4520.0 825.0 64 O64 –1320.0 825.0 25 O25 –4440.0 825.0 65 O65 –1240.0 825.0 26 O26 –4360.0 825.0 66 O66 –1160.0 825.0 27 O27 –4280.0 825.0 67 O67 –1080.0 825.0 28 O28 –4200.0 825.0 68 O68 –1000.0 825.0 29 O29 –4120.0 825.0 69 O69 –920.0 825.0 30 O30 –4040.0 825.0 70 O70 –840.0 825.0 31 O31 –3960.0 825.0 71 O71 –760.0 825.0 32 O32 –3880.0 825.0 72 O72 –680.0 825.0 33 O33 –3800.0 825.0 73 O73 –600.0 825.0 34 O34 –3720.0 825.0 74 O74 –520.0 825.0 35 O35 –3640.0 825.0 75 O75 –440.0 825.0 36 O36 –3560.0 825.0 76 O76 –360.0 825.0 37 O37 –3480.0 825.0 77 O77 –280.0 825.0 38 O38 –3400.0 825.0 78 O78 –200.0 825.0 39 O39 –3320.0 825.0 79 O79 –120.0 825.0 40 O40 –3240.0 825.0 80 O80 –40.0 825.0 Continued on next page. No. 5194-7/9 LC4104C Continued from preceding page. PAD No. Signal Y coordinate PAD No. Signal X coordinate Y coordinate 81 O81 X coordinate 40.0 825.0 121 O121 3240.0 825.0 82 O82 120.0 825.0 122 O122 3320.0 825.0 83 O83 200.0 825.0 123 O123 3400.0 825.0 84 O84 280.0 825.0 124 O124 3480.0 825.0 85 O85 360.0 825.0 125 O125 3560.0 825.0 86 O86 440.0 825.0 126 O126 3640.0 825.0 87 O87 520.0 825.0 127 O127 3720.0 825.0 88 O88 600.0 825.0 128 O128 3800.0 825.0 89 O89 680.0 825.0 129 O129 3880.0 825.0 90 O90 760.0 825.0 130 O130 3960.0 825.0 91 O91 840.0 825.0 131 O131 4040.0 825.0 92 O92 920.0 825.0 132 O132 4120.0 825.0 93 O93 1000.0 825.0 133 O133 4200.0 825.0 94 O94 1080.0 825.0 134 O134 4280.0 825.0 95 O95 1160.0 825.0 135 O135 4360.0 825.0 96 O96 1240.0 825.0 136 O136 4440.0 825.0 97 O97 1320.0 825.0 137 O137 4520.0 825.0 98 O98 1400.0 825.0 138 O138 4600.0 825.0 99 O99 1480.0 825.0 139 O139 4680.0 825.0 100 O100 1560.0 825.0 140 O140 4760.0 825.0 101 O101 1640.0 825.0 141 O141 4840.0 825.0 102 O102 1720.0 825.0 142 O142 4920.0 825.0 103 O103 1800.0 825.0 143 O143 5000.0 825.0 104 O104 1880.0 825.0 144 O144 5080.0 825.0 105 O105 1960.0 825.0 145 O145 5160.0 825.0 106 O106 2040.0 825.0 146 O146 5240.0 825.0 107 O107 2120.0 825.0 147 O147 5320.0 825.0 108 O108 2200.0 825.0 148 O148 5400.0 825.0 109 O109 2280.0 825.0 149 O149 5480.0 825.0 110 O110 2360.0 825.0 150 O150 5560.0 825.0 111 O111 2440.0 825.0 151 O151 5640.0 825.0 112 O112 2520.0 825.0 152 O152 5720.0 825.0 113 O113 2600.0 825.0 153 O153 5800.0 825.0 114 O114 2680.0 825.0 154 O154 5880.0 825.0 115 O115 2760.0 825.0 155 O155 5960.0 825.0 116 O116 2840.0 825.0 156 O156 6040.0 825.0 117 O117 2920.0 825.0 157 O157 6120.0 825.0 118 O118 3000.0 825.0 158 O158 6200.0 825.0 119 O119 3080.0 825.0 159 O159 6280.0 825.0 120 O120 3160.0 825.0 160 O160 6360.0 825.0 Continued on next page. No. 5194-8/9 LC4104C Continued from preceding page. PAD No. Signal X coordinate Y coordinate PAD No. Signal 161 V5 6300.0 –825.0 191 EIO1 X coordinate –450.0 Y coordinate –825.0 162 NC 6075.0 –825.0 192 NC –675.0 –825.0 163 V3 5850.0 –825.0 193 CP –900.0 –825.0 164 NC 5625.0 –825.0 194 NC –1125.0 –825.0 165 VDDH 5400.0 –825.0 195 LOAD –1350.0 –825.0 166 NC 5175.0 –800.0 196 NC –1575.0 –825.0 167 V2 4950.0 –800.0 197 M –1800.0 –825.0 168 NC 4725.0 –800.0 198 NC –2025.0 –825.0 169 V0 4500.0 –800.0 199 DISP –2250.0 –825.0 170 NC 4275.0 –825.0 200 NC –2475.0 –825.0 171 D0 4050.0 –825.0 201 TEST –2700.0 –825.0 172 NC 3825.0 –825.0 202 NC –2925.0 –825.0 173 D1 3600.0 –825.0 203 R/L –3150.0 –825.0 174 NC 3375.0 –825.0 204 NC –3375.0 –825.0 175 D2 3150.0 –825.0 205 BS –3600.0 –825.0 176 NC 2925.0 –825.0 206 NC –3825.0 –825.0 177 D3 2700.0 –825.0 207 VSS –4050.0 –800.0 178 NC 2475.0 –825.0 208 NC –4275.0 –800.0 179 D4 2250.0 –825.0 209 VDDH –4500.0 –825.0 180 NC 2025.0 –825.0 210 NC –4725.0 –825.0 181 D5 1800.0 –825.0 211 V0 –4950.0 –825.0 182 NC 1575.0 –825.0 212 NC –5175.0 –825.0 183 D6 1350.0 –825.0 213 V2 –5400.0 –825.0 184 NC 1125.0 –825.0 214 NC –5625.0 –825.0 185 D7 900.0 –825.0 215 V3 –5850.0 –825.0 186 NC 675.0 –825.0 216 NC –6075.0 –825.0 187 VDD 450.0 –825.0 217 V5 –6300.0 –825.0 188 NC 225.0 –825.0 189 EIO2 0.0 –825.0 190 NC –225.0 –825.0 ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ② Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1998. Specifications and information herein are subject to change without notice. PS No. 5194-9/9