MOTOROLA Freescale Semiconductor, Inc. Order this document by: DSP56651/D Rev 0, 6/98 SEMICONDUCTOR TECHNICAL DATA DSP56651 Advance Information Motorola designed the RAM-based DSP56651 emulation device to support the rigorous demands of developing applications for the cellular subscriber market. The high level of on-chip integration in the DSP56651 and its volume production companion device DSP56652 minimizes application system design complexity and component count, resulting in very compact implementations. This integration also yields very low-power consumption and cost-effective system performance. The DSP56651 chip combines the power of Motorola’s 32-bit M•CORE TM MicroRISC Engine (MCU) and the DSP56600 digital signal processor (DSP) core with on-chip memory, protocol timer, and custom peripherals to provide a single-chip cellular base-band processor. Figure 1 shows the basic block diagram of the DSP56651. Timer/ PWM Program Interrupt Timer Watch Dog External Memory RAM 512 x 32 ROM 4K x 32 Edge I/O Smart Card I/F M•CORE MicroRISC Core Keypad I/F Queued SPI Clocks MCU - DSP INTERFACE DSP56651 X Data RAM (7+1)K x 16 X Data ROM 9K x 16 Y Data RAM 8K x 16 Y Data ROM 9K x 16 Program RAM 24K x 24 Program ROM 24K x 24 UART MESSAGING UNIT 56600 DSP Core MUX Serial Audio CODEC I/F MCU OnCE DSP OnCE 1K x 16 RAM JTAG DSP PLL JTAG Freescale Semiconductor, Inc... INTEGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC Protocol Timer Serial Audio CODEC I/F Baseband CODEC I/F AA1617 Figure 1-1 DSP56651 System Block Diagram Development Part Only—Not intended for production. Requires a higher voltage than the production part This document contains information on a new product. Specifications and information herein are subject to change without notice. Preliminary ©1998 MOTOROLA, INC. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56652 Freescale Semiconductor, Inc... TABLE OF CONTENTS SECTION 1 PIN AND SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 FOR TECHNICAL ASSISTANCE: Telephone: 1 (800) 521-6274 Email: [email protected] Internet: http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR Used to indicate a signal that is active when pulled low; for example, the RESET pin is active when low “asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low “deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Note: Signal/Symbol Logic State Signal State Voltage1 PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. Preliminary ii DSP56652 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56651 Features FEATURES Freescale Semiconductor, Inc... RISC M•CORE MCU • 32-bit load/store RISC architecture • Fixed 16-bit instruction length • 16-entry 32-bit general-purpose register file • 32-bit internal address and data buses • Efficient four-stage, fully interlocked execution pipeline • Single-cycle execution for most instructions, two cycles for branches and memory accesses • Special branch, byte, and bit manipulation instructions • Support for byte, half-word, and word memory accesses • Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file High Performance DSP56600 Core • 1 × engine (e.g., 70 MHz = 70 MIPS) • Fully pipelined 16 × 16-bit parallel multiplier-accumulator (MAC) • Two 40-bit accumulators including extension bits • 40-bit parallel barrel shifter • Highly parallel instruction set with unique DSP addressing modes • Position-independent code support • Nested hardware DO loops • Fast auto-return interrupts • On-chip support for software patching and enhancements • Realtime trace capability via address bus visibility mode Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com iii Freescale Semiconductor, Inc. DSP56651 Features Freescale Semiconductor, Inc... On-chip Memories • 4K × 32-bit MCU ROM • 512 × 32-bit MCU RAM • 24K × 24-bit DSP program ROM • 24K × 24-bit DSP program RAM • 18K × 16-bit DSP data ROM, split into 9K × 16-bit X and 9K x 16 Y data ROM spaces • 16K × 16-bit DSP data RAM, split into (7+1)K × 16-bit X and 8K x 16-bit Y data RAM spaces On-chip Peripherals • Fully programmable phase-locked loop (PLL) for DSP clock generation • External interface module (EIM) for glueless system integration • External 22-bit address and 16-bit data MCU buses • Thirty-two source MCU interrupt controller • Intelligent MCU/DSP interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data RAM) with messaging status and control • Serial audio codec port • Serial baseband codec port • Protocol timer frees the MCU from radio channel timing events • Queued serial peripheral interface (SPI) • Keypad port capable of scanning up to an 8 × 8 matrix keypad • General-purpose MCU and DSP timers • Pulse width modulation output • Universal asynchronous receiver/transmitter (UART) with FIFO • IEEE 1149.1-compliant boundary scan JTAG test access port (TAP) • Integrated DSP/M•CORE On-Chip Emulation (OnCE™) module • DSP address bus visibility mode for system development • ISO 7816-compatible Smart Card port Preliminary iv DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. DSP56651 Target Applications Freescale Semiconductor, Inc... Operating Features: • Comprehensive static and dynamic power management • M•CORE operating frequency: dc to 16.8 MHz at 2.4 V • DSP operating frequency: dc to 58.8 MHz at 2.4 V • Operating temperature: –40˚ to 85˚C ambient • Package option: 17 × 17 mm, 196-lead PBGA TARGET APPLICATIONS The DSP56651 is intended for the development of cellular subscriber applications and other applications needing both DSP and control processing. PRODUCT DOCUMENTATION The four manuals listed in Table 1 are required for a complete description of the DSP56651 and are necessary to design with the part properly. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or the World Wide Web. Table 1 DSP56651 Documentation Document Name Description of Contents Order Number DSP56600 Family Manual Detailed description of the DSP56600 family core processor DSP56600FM/AD architecture and instruction set M•CORE Reference Manual Detailed description of the M•CORE MCU and instruction MCORERM/AD set DSP56652 User’s Manual Detailed description of DSP56652 memory, peripherals, and interfaces, much of which are common to the DSP56651 DSP56652UM/AD DSP56651 Technical Data DSP56651 pin and package descriptions; electrical and timing specifications DSP56651/D Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com v Freescale Semiconductor, Inc. DSP56651 Freescale Semiconductor, Inc... Product Documentation Preliminary vi DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 1 PIN AND SIGNAL DESCRIPTIONS Freescale Semiconductor, Inc... INTRODUCTION The pins and signals of the DSP56651 are described in the following sections. Figure 1-1 and Figure 1-2 on page 1-3 are top and bottom views of the package, respectively, showing the pin-outs. Subsequent tables list the pins by number and signal name. Figure 1-3 on page 1-11 is a representational pin-out of the chip grouping the signals by their function. Subsequent tables identify the signals of each group. DSP56651 PIN DESCRIPTION The following section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals of the DSP56651 are allocated for the 196-pin plastic ball grid array (PBGA) package. Top and bottom views of the PBGA package are shown in Figure 1-1 and Figure 1-2 on page 1-3 with their pin-outs. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description PBGA Package Description Freescale Semiconductor, Inc... Top View 1 2 3 4 5 A NC A20 TOUT0 TOUT3 TOUT6 B GNDA A18 A21 TOUT2 C VCCA A17 A19 D A13 A15 E A8 F 6 7 8 9 10 11 12 SPICS4 GNDH VCCHQ DSP_IRQ SRDB GNDE TOUT7 SPICS1 VCCQ MOSI SC2B SC0A SCKA TOUT1 TOUT5 VCCH GNDQ SCKB STDB SC1A PSTAT3 VCCK PSTAT0 SIZ1 A16 A14 TOUT4 SPICS3 SCK MISO SC1B SC2A VCCE SIZ0 MUX_CTL CTS A12 A11 A10 GND SPICS2 SPICS0 NC SC0B GND RTS RX TEST TX VCCA A7 A9 A6 A5 GND GND GND GND TDO TCK DSP_DE TDI TRST G A0 GNDA A4 A3 A2 GND GND GND GND MCU_DE ROW7 VCCHQ ROW6 TMS H CKIH EB1 A1 EB0 CKIL GND GND GND GND GNDG VCCG VCCQ ROW4 ROW5 J GNDF VCCQ VCCHQ CKOH GNDQ GND GND GND GND GNDQ ROW2 INT7 ROW1 ROW3 K CKO VCCF OE R/W GND D12 PWR_EN GNDB VCCP GND INT6 INT5 INT4 ROW0 L CS0 CS1 VCCC D5 GNDD D11 SIMCLK VCCB PCAP RESET_ IN VCCG INT0 GNDG INT3 M GNDC CS2 CS4 D1 VCCD D8 D13 VCCQ SIM DATA RESET_ OUT COL1 COL5 COL7 INT2 N CS3 CS5 D0 D4 D7 D10 D15 GNDQ SIM RESET GNDP1 COL0 COL3 COL6 INT1 P NC D2 D3 D6 D9 D14 VCCHQ SENSE GNDP MOD STO COL2 COL4 NC SRDA 13 14 STDA NC PSTAT2 PSTAT1 GNDK DSP56651 AA1694 Figure 1-1 DSP56651 Plastic Ball Grid Array (PBGA), Top View Preliminary 1-2 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description Freescale Semiconductor, Inc... Bottom View 14 13 12 11 10 NC STDA SRDA GNDE SRDB GNDK PSTAT1 PSTAT2 SCKA SIZ1 PSTAT0 VCCK CTS MUX_CTL TxD 9 8 7 DSP_IRQ VCCHQ GNDH SC0A SC2B MOSI PSTAT3 SC1A STDB SIZ0 VCCE SC2A TEST RxD RTS TRST TDI DSP_DE TMS ROW6 6 5 4 3 2 1 SPICS4 TOUT6 TOUT3 TOUT0 A20 NC A VCCQ SPICS1 TOUT7 TOUT2 A21 A18 GNDA B SCKB GNDQ VCCH TOUT5 TOUT1 A19 A17 VCCA C SC1B MISO SCK SPICS3 TOUT4 A14 A16 A15 A13 D GND SC0B NC SPICS0 SPICS2 GND A10 A11 A12 A8 E TCK TDO GND GND GND GND A5 A6 A9 A7 VCCA F VCCHQ ROW7 MCU_DE GND GND GND GND A2 A3 A4 GNDA A0 G ROW5 ROW4 VCCQ VCCG GNDG GND GND GND GND CKIL EB0 A1 EB1 CKIH H ROW3 ROW1 INT7 ROW2 GNDQ GND GND GND GND GNDQ CKOH VCCHQ VCCQ GNDF J ROW0 INT4 INT5 INT6 GND VCCP GNDB PWR_EN D12 GND R/W OE VCCF CKO K INT3 GNDG INT0 VCCG RESET_ IN PCAP VCCB SIMCLK D11 GNDD D5 VCCC CS1 CS0 L INT2 COL7 COL5 COL1 RESET_ OUT SIM DATA VCCQ D13 D8 VCCD D1 CS4 CS2 INT1 COL6 COL3 COL0 GNDP1 RESET GNDQ D15 D10 D7 D4 D0 CS5 CS3 N NC COL4 COL2 STO SENSE VCCHQ D14 D9 D6 D3 D2 NC P SIM MOD GNDP GNDC M AA1695 Figure 1-2 DSP56651 Plastic Ball Grid Array (PBGA), Bottom View Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-3 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description Table 1-1 DSP56651 PBGA Signal Identification by Pin Number Freescale Semiconductor, Inc... Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name A1 Not Connected (NC), reserved B12 PSTAT2 D9 SC1B A2 A20 B13 PSTAT1 D10 SC2A A3 TOUT0 B14 GNDK D11 VCCE A4 TOUT3 C1 VCCA D12 SIZ0 A5 TOUT6 C2 A17 D13 MUX_CTL A6 SPICS4 C3 A19 D14 CTS A7 GNDH C4 TOUT1 E1 A8 A8 VCCHQ C5 TOUT5 E2 A12 A9 DSP_IRQ C6 VCCH E3 A11 A10 SRDB C7 GNDQ E4 A10 A11 GNDE C8 SCKB E5 GND A12 SRDA C9 STDB E6 SPICS2 A13 STDA C10 SC1A E7 SPICS0 A14 NC C11 PSTAT3 E8 NC B1 GNDA C12 VCCK E9 SC0B B2 A18 C13 PSTAT0 E10 GND B3 A21 C14 SIZ1 E11 RTS B4 TOUT2 D1 A13 E12 RxD B5 TOUT7 D2 A15 E13 TEST B6 SPICS1 D3 A16 E14 TxD B7 VCCQ D4 A14 F1 VCCA B8 MOSI D5 TOUT4 F2 A7 B9 SC2B D6 SPICS3 F3 A9 B10 SC0A D7 SCK F4 A6 B11 SCKA D8 MISO F5 A5 Preliminary 1-4 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description Table 1-1 DSP56651 PBGA Signal Identification by Pin Number (Continued) Freescale Semiconductor, Inc... Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name F6 GND H3 A1 J14 ROW3 F7 GND H4 EB0 K1 CKO F8 GND H5 CKIL K2 VCCF F9 GND H6 GND K3 OE F10 TDO H7 GND K4 R/W F11 TCK H8 GND K5 GND F12 DSP_DE H9 GND K6 D12 F13 TDI H10 GNDG K7 PWR_EN F14 TRST H11 VCCG K8 GNDB G1 A0 H12 VCCQ K9 VCCP G2 GNDA H13 ROW4 K10 GND G3 A4 H14 ROW5 K11 INT6 G4 A3 J1 GNDF K12 INT5 G5 A2 J2 VCCQ K13 INT4 G6 GND J3 VCCHQ K14 ROW0 G7 GND J4 CKOH L1 CS0 G8 GND J5 GNDQ L2 CS1 G9 GND J6 GND L3 VCCC G10 MCU_DE J7 GND L4 D5 G11 ROW7 J8 GND L5 GNDD G12 VCCHQ J9 GND L6 D11 G13 ROW6 J10 GNDQ L7 SIMCLK G14 TMS J11 ROW2 L8 VCCB H1 CKIH J12 INT7 L9 PCAP H2 EB1 J13 ROW1 L10 RESET_IN Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-5 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description Table 1-1 DSP56651 PBGA Signal Identification by Pin Number (Continued) Freescale Semiconductor, Inc... Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name L11 VCCG M13 COL7 P1 NC L12 INT0 M14 INT2 P2 D2 L13 GNDG N1 CS3 P3 D3 L14 INT3 N2 CS5 P4 D6 M1 GNDC N3 D0 P5 D9 M2 CS2 N4 D4 P6 D14 M3 CS4 N5 D7 P7 VCCHQ M4 D1 N6 D10 P8 SENSE M5 VCCD N7 D15 P9 GNDP M6 D8 N8 GNDQ P10 MOD M7 D13 N9 SIMRESET P11 STO M8 VCCQ N10 GNDP1 P12 COL2 M9 SIMDATA N11 COL0 P13 COL4 M10 RESET_OUT N12 COL3 P14 NC M11 COL1 N13 COL6 M12 COL5 N14 INT1 Preliminary 1-6 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description Freescale Semiconductor, Inc... Table 1-2 DSP56651 PBGA Signal Identification by Name Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. A0 G1 CKOH J4 D9 P5 A1 H3 COL0 N11 D10 N6 A2 G5 COL1 M11 D11 L6 A3 G4 COL2 P12 D12 K6 A4 G3 COL3 N12 D13 M7 A5 F5 COL4 P13 D14 P6 A6 F4 COL5 M12 D15 N7 A7 F2 COL6 N13 DSP_DE F12 A8 E1 COL7 M13 DSP_IRQ A9 A9 F3 CS0 L1 EB0 H4 A10 E4 CS1 L2 EB1 H2 A11 E3 CS2 M2 GND E10 A12 E2 CS3 N1 GND E5 A13 D1 CS4 M3 GND F6 A14 D4 CS5 N2 GND F7 A15 D2 CTS D14 GND F8 A16 D3 D0 N3 GND F9 A17 C2 D1 M4 GND G6 A18 B2 D2 P2 GND G7 A19 C3 D3 P3 GND G8 A20 A2 D4 N4 GND G9 A21 B3 D5 L4 GND H6 CKIH H1 D6 P4 GND H7 CKIL H5 D7 N5 GND H8 CKO K1 D8 M6 GND H9 Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-7 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description Freescale Semiconductor, Inc... Table 1-2 DSP56651 PBGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. GND J6 INT2 M14 RESET_OUT M10 GND J7 INT3 L14 ROW0 K14 GND J8 INT4 K13 ROW1 J13 GND J9 INT5 K12 ROW2 J11 GND K10 INT6 K11 ROW3 J14 GND K5 INT7 J12 ROW4 H13 GNDA B1 MCU_DE G10 ROW5 H14 GNDA G2 MISO D8 ROW6 G13 GNDB K8 MOD P10 ROW7 G11 GNDC M1 MOSI B8 RTS E11 GNDD L5 MUX_CTL D13 RxD E12 GNDE A11 NC A1 SC0A B10 GNDF J1 NC A14 SC0B E9 GNDG H10 NC E8 SC1A C10 GNDG L13 NC P1 SC1B D9 GNDH A7 NC P14 SC2A D10 GNDK B14 OE K3 SC2B B9 GNDP P9 PCAP L9 SCK D7 GNDP1 N10 PSTAT0 C13 SCKA B11 GNDQ C7 PSTAT1 B13 SCKB C8 GNDQ J10 PSTAT2 B12 SENSE P8 GNDQ J5 PSTAT3 C11 SIMCLK L7 GNDQ N8 PWR_EN K7 SIMDATA M9 INT0 L12 R/W K4 SIMRESET N9 INT1 N14 RESET_IN L10 SIZ0 D12 Preliminary 1-8 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Pin Description Freescale Semiconductor, Inc... Table 1-2 DSP56651 PBGA Signal Identification by Name (Continued) Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. SIZ1 C14 TOUT0 A3 VCCF K2 SPICS0 E7 TOUT1 C4 VCCG H11 SPICS1 B6 TOUT2 B4 VCCG L11 SPICS2 E6 TOUT3 A4 VCCH C6 SPICS3 D6 TOUT4 D5 VCCHQ A8 SPICS4 A6 TOUT5 C5 VCCHQ G12 SRDA A12 TOUT6 A5 VCCHQ J3 SRDB A10 TOUT7 B5 VCCHQ P7 STDA A13 TRST F14 VCCK C12 STDB C9 TxD E14 VCCP K9 STO P11 VCCA C1 VCCQ B7 TCK F11 VCCA F1 VCCQ J2 TDI F13 VCCB L8 VCCQ H12 TDO F10 VCCC L3 VCCQ M8 TEST E13 VCCD M5 TMS G14 VCCE D11 Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-9 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description DSP56651 SIGNAL DESCRIPTION DSP56651 signals are organized into nineteen functional groups as summarized in Table 1-3. Figure 1-3 is a diagram of DSP56651 signals by functional group. Table 1-3 Signal Functional Group Allocations Number of Signals Detailed Description Power (VCCX) 20 Table 1-4 Ground (GNDX) 17 Table 1-5 Substrate ground (GND) 20 PLL and clocks 5 Table 1-6 22 Table 1-7 16 Table 1-8 4 Table 1-9 6 Table 1-10 Reset, mode, and multiplexer control 5 Table 1-11 External interrupts 9 Table 1-12 Timers 8 Table 1-13 Keypad port 16 Table 1-14 Serial data port (UART) 4 Table 1-15 Serial control port (QSPI) 8 Table 1-16 Smart Card port (SIM) 5 Table 1-17 Serial audio codec port (SAP) 6 Table 1-18 Baseband codec port 6 Table 1-19 6 Table 1-20 2 Table 1-21 6 Table 1-22 Freescale Semiconductor, Inc... Functional Group Address bus External Interface Module (EIM) Data bus Bus control Chip selects Emulation port Development and Test Debug control port JTAG test access port (TAP) Preliminary 1-10 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Freescale Semiconductor, Inc... DSP56651 VCCA VCCB VCCC VCCD VCCE VCCF VCCG VCCH VCCHQ VCCK VCCP VCCQ 2 GNDA GNDB GNDC GNDD GNDE GNDF GNDG GNDH GNDK GNDP GNDP1 GNDQ GND CKIH CKIL CKO CKOH PCAP 2 2 4 4 2 4 20 A0-A21 D0-D15 R/W EB0 EB1 OE Chip Selects RESET_IN RESET_OUT MOD MUX_CTL STO Power Inputs: Address Bus Smart Card Bus Control Data Bus Audio Codec Clock Output GPIO/Keypad/Int/JTAG/UART/STO Baseband Codec/Timers/QSPI Quiet Power High Emulation Port PLL Internal Logic (Quiet) Interrupts Grounds: Address Bus Smart Card Bus Control Data Bus Audio Codec Clock Output GPIO/Keypad/Int/JTAG Baseband Codec/Timers Emulation Port PLL PLL Internal Logic (Quiet) Substrate Ground Serial Data Port (UART) PLL and Clocks Timers 6 INT0–INT5 INT6/STDA/DSR or TRST INT7/SRDA/DTR/SCK or TMS DSP_IRQ 8 TOUT0–TOUT7 6 Keypad Port Queued Serial Port COL0–COL5 COL6/OC1 COL7/PWM ROW0–ROW4 ROW5/IC2B ROW6/SC2A/DCD or DSP_DE ROW7/SCKA/RI or TCK 5 TxD or TDO RxD/IC1 or TDI RTS/IC2 or RESET_IN CTS or MCU_DE 5 SPICS0–SPICS4 SCK MISO MOSI SIMCLK SENSE SIMDATA SIMRESET PWR_EN Smart Card Port STDA SRDA SCKA SC0A–SC2A Serial Audio Codec Port 3 22 16 4 External Data Bus Baseband Codec Port External Bus Control Emulation Port External Address Bus CS0 CS1–CS4 CS5 Reset, Mode, and Multiplexer Control STDB SRDB SCKB SC0B–SC2B 3 2 4 Debug Control Port SIZ0–SIZ1 PSTAT0–PSTAT3 MCU_DE DSP_DE JTAG Port TCK TDI TDO TMS TRST TEST AA1690 Figure 1-3 Signals Identified by Functional Group Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-11 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Power Table 1-4 Power Freescale Semiconductor, Inc... Power Names Description VCCA Address Bus power—These lines supply power to the address bus. VCCB Smart Card interface power—This line supplies isolated power for Smart Card Interface I/O drivers. VCCC Bus control power—This line supplies power to the bus control logic. VCCD Data bus power—These lines supply power to the data bus. VCCE Audio codec port power—This line supplies power to audio codec I/O drivers. VCCF Clock output power—This line supplies a quiet power source for the CKOUT output. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 µF bypass capacitor located as close as possible to the chip package to connect between the VCCF line and the GNDF line. VCCG GPIO power—This line supplies power to the GPIO, keypad, data port, interrupts, STO, and JTAG I/O drivers. VCCH Baseband codec and timer power—This line supplies power to the baseband codec, timer and QSPI I/O drivers. VCCHQ Quiet power high—These lines supply a quiet power source to the pre-driver voltage converters. This value should be greater than or equal to the maximum value of the power supplies of the chip I/O drivers (i.e., the maximum of VCCA, VCCB, VCCC, VCCD, VCCE, VCCF, VCCG, VCCH, and VCCK). VCCK Emulation port power—This line supplies power to the emulation port I/O drivers. VCCP Analog PLL circuit power—This line is dedicated to the analog PLL circuits and must remain noise-free to ensure stable PLL frequency and performance. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 µF capacitor and a 0.01 µF capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP and GND P1 lines. VCCQ Quiet power—These lines supply a quiet power source to the internal logic circuits. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 µF bypass capacitor located as close as possible to the chip package to connect between the VCCQ lines and the GNDQ lines. Preliminary 1-12 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Ground Table 1-5 Ground Freescale Semiconductor, Inc... Ground Names Description GNDA Address Bus ground—These lines connect system ground to the address bus. GNDB Smart Card interface ground—These lines connect system ground to the Smart Card bus. GNDC Bus control ground—This line connects ground to the bus control logic. GNDD Data bus ground—These lines connect system ground to the data bus. GNDE Audio codec port ground—These lines connect system ground to the audio codec port. GNDF Clock output ground—This line supplies a quiet ground connection for the clock output drivers. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 µF bypass capacitor located as close as possible to the chip package to connect between the VCCF line and the GNDF line. GNDG GPIO ground—These lines connect system ground to GPIO, keypad, data port, interrupts, STO, and JTAG I/O drivers. GNDH Baseband codec and timer ground—These lines connect system ground to the baseband codec, timer and QSPI I/O drivers. GNDK Emulation port ground—These lines connect system ground to the emulation port I/O drivers. GNDP Analog PLL circuit ground—This line supplies a dedicated quiet ground connection for the analog PLL circuits and must remain relatively noise-free to ensure stable PLL frequency and performance. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 µF capacitor and a 0.01 µF capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP line. GNDP1 Analog PLL circuit ground—This line supplies a dedicated quiet ground connection for the analog PLL circuits and must remain relatively noise-free to ensure stable PLL frequency and performance. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 µF capacitor and a 0.01 µF capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP line. GNDQ Quiet ground—These lines supply a quiet ground connection for the internal logic circuits. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 µF bypass capacitor located as close as possible to the chip package to connect between the VCCQ line and the GNDQ line. GND Substrate ground—These lines must be tied to ground. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-13 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description PLL and Clock Table 1-6 PLL and Clock Signals Freescale Semiconductor, Inc... Signal Name Signal Type State during Reset Signal Description CKIH Input Input High frequency clock input—This signal provides the high frequency input clock. This clock may be other a CMOS square wave or sinusoid input. CKIL Input Input Low frequency clock input—This signal provides the low frequency input clock and should be less than or equal to the frequency of CKIH. This is the default input clock after reset. CKO Output Driven low DSP/MCU output clock—This signal provides an output clock synchronized to the DSP or MCU core internal clock phases, according the selected programming option. The choices of clock source and enabling/disabling the output signal are software selectable. CKOH Output Driven low High frequency clock output—This signal provides an output clock derived from the CKIH input. This signal can be enabled or disabled by software. PCAP Input/ Output Indeterminate PLL capacitor—This signal is used to connect the required external filter capacitor to the PLL filter. Connect one end of the capacitor to PCAP and the other to VCCP. The value of the capacitor is specified in Section 2 of this data sheet. Address Bus Table 1-7 Address Bus Signals Signal Names A0–A21 Signal Type Output State during Reset Driven low Signal Description Address bus—These signals specify the address for external memory accesses. If there is no external bus activity, A0–A21 remain at their previous values to reduce power consumption. Preliminary 1-14 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Data Bus Table 1-8 Data Bus Signals Signal Names Freescale Semiconductor, Inc... D0–D15 Signal Type Input/ Output State during Reset Input Signal Description Data bus—These signals provide the bidirectional data bus for external memory accesses. D0–D15 are held in the previous logic state when there is no external bus activity and during hardware reset. This is done with weak “keepers” inside the I/O buffers. Bus Control Table 1-9 Bus Control Signals Signal Name Signal Type State during Reset Signal Description R/W Output Driven high Read/write—This signal indicates the bus access type. A high signal indicates a bus read. A low signal indicates a write to the bus. When accessing memory it can also be used as write enable (WE) signal. When accessing a peripheral chip, the signal acts as a read/write. EB0 Output Driven high Enable byte 0—When driven low, this signal indicates access to data byte 0 (D8–D15) during a read or write cycle. This pin may also act as a write byte enable, if so programmed. This output is used when accessing 16-bit wide SRAM. EB1 Output Driven high Enable byte 1—When driven low, this signal indicates access to data byte 1 (D0–D7) during a read or write cycle. This pin may also act as a write byte enable, if so programmed. This output is used when accessing 16-bit wide SRAM. OE Output Driven high Bus select—When driven low, this signal indicates that the current bus access is a read cycle and enables slave devices to drive the data bus with a read. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-15 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Chip Selects Table 1-10 Chip Select Signals Freescale Semiconductor, Inc... Signal Name Signal Type State during Reset Signal Description CS0 Output Chipdriven Chip select 0—This signal is asserted low based on the decode of the internal address bus bits A[31:24] and is typically used as the external flash memory chip select. After reset, accesses using this CS have a default of 15 wait states. CS1–CS4 Output Driven high Chip select 1–chip select 4—These signals are asserted low based on the decode of the internal address bus bits A[31:24] of the access address. When not selected as chip select signals, these signals become general purpose outputs (GPOs). After reset, these signals are GPOs that are driven high. CS5 Output Driven low Chip select 5—This signal is asserted high based on the decode of the internal address bus bits A[31:24] of the access address. When not selected as a chip select signal, this signal becomes a GPO. After reset, this signal is a GPO that is driven low. Preliminary 1-16 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Reset, Mode, and Multiplexer Control Table 1-11 Reset, Mode, and Multiplexer Control Signals Freescale Semiconductor, Inc... Signal Name Signal Type State during Reset Signal Description RESET_IN Input Input Reset input—This signal is an active low Schmitt trigger input that provides a reset signal to the internal circuitry. The input is valid if it is asserted for at least three CKIL clock cycles. This pin has a 47kΩ pull-up resistor. Note: If MUX_CTL is held high, the RTS signal of the serial data port (UART) becomes the RESET_IN input line. (See Table 1-15 on page 1-26.) RESET_OUT Output Pulled low Reset output—This signal is asserted low for at least seven CKIL clock cycles under one of the following conditions: • RESET_IN is pulled low for at least three CKIL clock cycles • The alternate RESET_IN signal is enabled by MUX_CTL and is pulled low for at least three CKIL clock cycles • The watchdog count expires This signal is asserted immediately after the qualifier detects a valid RESET_IN signal, remains asserted during RESET_IN assertion, and is stretched for at least seven more CKIL clock cycles after RESET_IN is deasserted. Three CKIL clock cycles before RESET_OUT is deasserted, the MCU boot mode is latched from the MOD signal. MOD Input Input Mode select—This signal selects the MCU boot mode during hardware reset. If MOD is driven low at least four CKIL clock cycles before RESET_OUT is deasserted, then the internal MCU ROM ignores the first access and the M•CORE fetches the first word from the first location the external flash memory. If MOD is driven high four CKIL clock cycles before RESET_OUT deassertion, then the internal MCU ROM is enabled and the M•CORE fetches the first word from the first location in the internal ROM. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-17 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-11 Reset, Mode, and Multiplexer Control Signals (Continued) Signal Name Freescale Semiconductor, Inc... MUX_CTL Signal Type Input State during Reset Input Signal Description Multiplexer control—This input allows the designer to select an alternate set of pins to be used for RESET_IN, the debug control port signals, and the JTAG signals as defined below: Normal Alternate (MUX_CTL low) (MUX_CTL high) TRST Interrupt signals INT6/STDA/DSR (See Table 1-12) INT7/SRDA/DTR/SCLK TMS Keypad signals ROW6/SC2A/DCD DSP_DE (See Table 1-14 ROW7/SCKA/RI TCK on page 1-22) TDO Serial Data Port TxD TDI (UART) signals RxD/IC1 (See Table 1-15 RTS/IC2A RESET_IN on page 1-26) CTS MCU_DE If MUX_CTL is driven low, the normal functions are selected. If MUX_CTL is driven high, the alternate functions are selection. Note: The user is responsible to ensure that transition between normal and alternate functions are made smoothly. No provisions are made in the on-chip hardware to assure such a smooth switch. The external command converter uses to drive this signal must ensure that critical pins (such as the JTAG TMS and TRST signals and RESET_IN) are driven with inactive values during and after the switch. The MUX_CTL signal has an internal 100 kΩ pull-down resistor. STO Output Chip driven Soft turn off—This is a general purpose output pin. Its logic state is not affected by reset. For Reset, mode, and MUX control signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary 1-18 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Interrupts Table 1-12 Interrupt Signals Signal Name Freescale Semiconductor, Inc... INT0–INT3 Signal Type State during Reset Input or Input Output Signal Description Interrupt 0–interrupt 3—These signals can be programmed as interrupt inputs or GPIO signals. The signals have on-chip 100 kΩ pull-up resistors. As Schmitt trigger interrupt inputs the signals can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. The signals are GPIOs when not programmed as interrupts. After reset, the default state for these signals is general purpose input (GPI). INT4–INT5 Input or Input Output Interrupt 4–interrupt 5—These signals can be programmed as interrupt inputs or GPIO signals, and have 10-27kΩ pull-up resistors. As Schmitt trigger interrupt inputs, the signals can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. The signals are GPIOs when not programmed as interrupts. After reset, the default state for these signals is GPI. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-19 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-12 Interrupt Signals (Continued) Signal Name Signal Type State during Reset Signal Description Normal: Freescale Semiconductor, Inc... INT6 MUX_CTL driven low Input or Input Output Interrupt 6—When selected, this signal can be programmed as an interrupt input or a GPIO signal, and has a 47kΩ pull-up resistor. As a Schmitt trigger interrupt input, the signal can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. STDA Output Audio codec serial transmit data (alternate)—When programmed as STDA, this signal transmits data from the serial transmit shift register in the serial audio codec port. Note: DSR Output When this signal is used as STDA, the primary STDA signal is disabled. (See Table 1-18 on page 1-31.) Data set ready—When programmed as GPIO output, this signal can be used as the DSR output for the serial data port. (See Table 1-15 on page 1-26) The signal is a GPIO when not programmed as one of the above functions. After reset, the default state for this signal is GPI. Alternate: TRST MUX_CTL driven high Input Input Test Reset—When selected, this signal acts as the TRST input for the JTAG TAP controller. The signal is a Schmitt trigger input that asynchronously initializes the JTAG test controller when asserted. Note: When this signal is enabled, the primary TRST signal is disconnected from the TAP controller. (See Table 1-22.) Preliminary 1-20 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-12 Interrupt Signals (Continued) Signal Name Signal Type State during Reset Signal Description Normal: Freescale Semiconductor, Inc... INT7 MUX_CTL driven low Input or Input Output Interrupt 7—When selected, this signal can be programmed as an interrupt input or a GPIO signal, and has a 47kΩ pull-up resistor. As a Schmitt trigger interrupt input, the signal can be programmed to be level sensitive, positive edge-triggered, or negative edgetriggered. When edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal; however, as signal fall time of the interrupt signal increases, the probability of generating multiple interrupts due to this noise also increases. SRDA Input Audio codec serial receive data (alternate)—When programmed as SRDA, this signal receives data into the serial receive shift register in the serial audio codec port. Note: When this signal is used as SRDA, the primary SRDA signal is disabled. (See Table 1-18 on page 1-31.) DTR Input Data terminal ready—When programmed as GPIO, this signal is used as the DTR positive and negative edge-triggered interrupt input for the serial data port. (See Table 1-15 on page 1-26.) SCLK Input Serial clock–When so programmed, this signal provides the input clock for the serial data port (UART). (See Table 1-15 on page 1-26.) The signal is a GPIO when not programmed as one of the above functions. After reset, the default state for this signal is GPI. Alternate: TMS MUX_CTL driven high Input Input Test mode select—When selected, this signal acts as the TMS input for the JTAG TAP controller. The signal is used to sequence that TAP controller state machine. The TMS is sampled on the rising edge of TCK. Note: When this signal is enabled, the primary TMS signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-21 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-12 Interrupt Signals (Continued) Signal Name Signal Type Freescale Semiconductor, Inc... DSP_IRQ Input State during Reset Signal Description Input DSP external interrupt request—This active low Schmitt trigger input can be programmed as a level-sensitive or negative edgetriggered maskable interrupt request input during normal instruction processing. If the DSP is in the stop state and DSP_IRQ is asserted, the DSP exits the stop state. This signal has an on-chip 47 kΩ pull-up resistor. For Interrupt signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Timers Table 1-13 Timer Signals Signal Name TOUT0– TOUT7 Signal Type State during Reset Input or Input Output Signal Description Timer output 0–7—These are timer output signals. After reset, the default state for these signals is GPI. Note: These signals are GPIOs when not used as timer outputs. Keypad Port Table 1-14 Keypad Port Signals Signal Name COL0–COL5 Signal Type State during Reset Input or Input Output Signal Description Column strobe 0–5—These signals function as keypad column strobes that can be programmed as regular or open-drain outputs. When not used as column strobe signals, these are GPIO signals. After reset, the default state is GPI. Preliminary 1-22 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-14 Keypad Port Signals (Continued) Freescale Semiconductor, Inc... Signal Name Signal Type State during Reset Signal Description COL6 Input or Input Output Column strobe 6—This signal functions as a keypad column strobe that can be programmed as a regular or open-drain output. OC1 Output MCU timer 1 output compare —When programmed as OC1, this is the MCU Timer 1 output compare signal. When not programmed as OC1 and not used as a column strobe signal, this is a GPIO signal. After reset, the default state is GPI COL7 Input or Input Output Column strobe 7—This signal functions as a keypad column strobe that can be programmed as a regular or open-drain output. PWM Output Pulse width modulator output—When so programmed, this is the pulse width modulator output. When not programmed as PWM and not used as a column strobe signal, this is a GPIO signal. After reset, the default state is GPI ROW0– ROW4 Input or Input Output Row sense 0–4—These signals function as keypad row senses. When not used as Row Sense signals, these are GPIO signals. After reset, the default state is GPI. These signals have on-chip 22 kΩ pullup resistors. ROW5 Input or Input Output Row sense 5—This signal functions as a keypad row sense. IC2B Input MCU input compare 2 timer—When so programmed, this signal can be the input capture for the MCU input compare 2 timer. When not programmed as IC2B and not used as a row sense signal, this is a GPIO signal. After reset, the default state is GPI. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-23 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-14 Keypad Port Signals (Continued) Signal Name Signal Type State during Reset Freescale Semiconductor, Inc... Normal: Signal Description MUX_CTL driven low ROW6 Input or Input Output Row sense 6—This signal functions as a keypad row sense and is equipped with an on-chip 100kΩ pull-up resistor. SC2A Input or Output Audio codec serial control 2 (alternate)—When programmed as SC2A, this signal provides I/O frame synchronization for the serial audio codec port. In synchronous mode, the signal provides the frame sync for both the transmitter and receiver. In asynchronous mode, the signal provides the frame sync for the transmitter only. As SC2A, this pin has a 100kΩ pull-down resistor. Note: When this signal is used as SC2A, the primary SC2A signal is disabled. (See Table 1-18 on page 1-31.) DCD Output Data Carrier Detect—When programmed as GPIO output, this signal can be used as the DSR output for the serial data port. (See Table 1-15 on page 1-26.) After reset, the default state is GPI. Alternate: DSP_DE MUX_CTL driven high Input Output Input Digital signal processor debug event—As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the DSP has entered the debug mode. When programmed as DSP_DE, this signal has an open-drain 100kΩ pull-up. When the DSP enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts DSP_DE as an output signal for three clock cycles. Note: When this signal is enabled, the primary DSP_DE signal is disabled. (See Table 1-21 on page 1-35.) Preliminary 1-24 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-14 Keypad Port Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Semiconductor, Inc... Normal: MUX_CTL driven low ROW7 Input or Input Output SCKA Input Row sense 7—This signal functions as a keypad row sense. Audio codec serial clock (alternate)—When programmed as SCKA, this signal provides the serial bit rate clock for the serial audio codec port. In synchronous mode, the signal provides the clock input or output for both the transmitter and receiver. In asynchronous mode, the signal provides the clock for the transmitter only. Note: RI Ring indicator—When programmed as GPIO output, this signal can be used as the RI output for the serial data port. (See Table 1-15.) After reset, the default state is GPI. Output Alternate: TCK When this signal is used as SCKA, the primary SCKA signal is disabled. (See Table 1-18 on page 1-31.) MUX_CTL driven high Input Input Test clock—When selected, this signal provides the TCK input for the JTAG TAP controller. The signal is used to synchronize the JTAG test logic. This signal is equipped with a 47kΩ pull-up resistor. Note: When this signal is enabled, the primary TCK signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) For keypad port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-25 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Serial Data Port (UART) Table 1-15 Serial Data Port (UART) Signals Signal Name Signal Type State during Reset Signal Description Normal: Freescale Semiconductor, Inc... TxD MUX_CTL driven low Input or Input Output UART transmit—This signal transmits data from the UART. The signal is a GPIO when not programmed as the TxD signal. After reset, the default state for this signal is GPI. Alternate: TDO MUX_CTL driven high Output Test data output—When selected, this signal provides the TDO serial output for test instructions and data from the JTAG TAP controller. TDO is a tri-state signal that is actively driven in the shift-IR and shift-DR controller states. Note: Normal: When this signal is enabled, the primary TDO signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) MUX_CTL driven low RxD Input or Input Output UART receive—This signal receives data into the UART. IC1 Input Input compare 1—When so programmed, the signal connects to an input capture/output compare timer used for autobaud mode support. The signal is a GPIO when not programmed as one of the above functions. This signal has an on-chip 47 kΩ pull-up resistor. After reset, the default state for this signal is GPI. Alternate: TDI MUX_CTL driven high Input Input Test data in—When selected, this signal provides the TDI serial input for test instructions and data for the JTAG TAP controller. TDI is sampled on the rising edge of TCK. Note: When this signal is enabled, the primary TDI signal is disconnected from the TAP controller. (See Table 1-22 on page 1-36.) Preliminary 1-26 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-15 Serial Data Port (UART) Signals (Continued) Signal Name Signal Type State during Reset Signal Description Freescale Semiconductor, Inc... Normal: MUX_CTL driven low RTS Input or Input Output Request to send—This signal functions as the UART RTS signal. IC2A Input Input compare 2 A—When so programmed, this signal connects to an input capture timer channel. The signal is a GPIO when not programmed as one of the above functions. After reset, the default state for this signal is GPI. Alternate: RESET_IN MUX_CTL driven high Input Input Reset input—This signal is an active low Schmitt trigger input that provides a reset signal to the internal circuitry. The input is valid if it is asserted for at least three CKIL clock cycles. Note: When this signal is enabled, the primary RESET_IN signal is disabled. (See Table 1-11 on page 1-17.) Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-27 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-15 Serial Data Port (UART) Signals (Continued) Signal Name Signal Type State during Reset Signal Description Normal: MUX_CTL driven low CTS Input or Input Output Clear to send—This signal functions as the UART CTS signal, and is equipped with a 47kΩ pull-up. Freescale Semiconductor, Inc... After reset, the default state for this signal is GPI. Note: Alternate: MCU_DE MUX_CTL driven high Input Output Input Microcontroller debug event—As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the MCU has entered the debug mode. The signal is equipped with an open-drain 47kΩ pull-up resistor. When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts MCU_DE as an output signal for several clock cycles. Note: Note: • • • • The signal is a GPIO when not used as CTS. When this signal is enabled, the primary MCU_DE signal is disabled. (See Table 1-21.) There are four additional signals that support UART operation, provided as follows: DSR—data set ready. This is an alternate function for the INT6 signal. (See Table 1-12 on page 1-19.) DTR—data terminal ready. This is an alternate function for the INT7 signal. (See Table 1-12 on page 1-19.) DCD—data carrier detect. This is an alternate function for the ROW6 signal. (See Table 1-14 on page 1-22.) RI—ring indicator. This is an alternate function for the ROW7 signal. (See Table 1-14 on page 1-22.) For serial data port (UART) signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary 1-28 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Serial Control Port Table 1-16 Serial Control Port Signals Signal Name Freescale Semiconductor, Inc... SPICS0– SPICS3 Signal Type Output State during Reset Input Input or Output SPICS4 Output Output Input Input Input Output Input or Output Serial clock — This output signal provides the serial clock from the QSPI for the accessed peripherals. There is a programmable number of clock cycles delay between the assertion of the chip select signal and the first transmission of the serial clock. The polarity and phase of SCK are programmable. This is a GPIO signal when the SCK function is not being used. After reset, the default state is GPI. Input Synchronous master in slave out—This input signal provides serial data input to the QSPI. Input data can be sampled on the rising or falling edge of SCK and received in QSPI RAM MSB or LSB first. This is a GPIO signal when the function is not being used. After reset, the default state is GPI. Input or Output MOSI Synchronous peripheral chip select 4—This output signal provides a chip select signal for the QSPI. This signal is programmable as active high or active low. This signal has an on-chip 100 kΩ pulldown resistor. This is a GPIO signal when the chip select function is not being used. After reset, the default state is GPI. Input or Output MISO Synchronous peripheral chip select 0–3—The output signals provide chip select signals for the queued serial peripheral interface (QSPI). The signals are programmable as active high or active low. Each signal has an on-chip 100 kΩ pull-up resistor. These are GPIO signals when the chip select functions are not being used. After reset, the default state for each signal is GPI. Input or Output SCK Signal Description Input Synchronous master out slave in—This output signal provides serial data from the QSPI. Output data can be sampled on the rising or falling edge of SCK and transmitted MSB or LSB first. This is a GPIO signal when the function is not being used. After reset, the default state is GPI. For serial control port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-29 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Smart Card Port After rest, the default state of all Smart Card port pins is GPI. For Smart Card port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Table 1-17 Smart Card Port Signals Freescale Semiconductor, Inc... Signal Name SIMCLK Signal Type Output State during Reset Input Input or Output SENSE Input Input/ Output Input Output Input Output Input or Output SIM data—This bidirectional signal is used to transmit data to and receive data from the Smart Card. In the output state, the signal is open-drain. This signal is a GPIO signal when the Smart Card port is not being used. The signal has an on-chip 47 kΩ pull-up resistor. Input Input or Output PWR_EN SIM sense—This signal is a Schmitt trigger input that signals when a Smart Card is inserted or removed. This signal is a GPIO signal when the Smart Card port is not being used. The signal has an on-chip 100 kΩ pull-down resistor. Input or Output SIMRESET SIM clock—This signal is an output clock from the Smart Card port to the Smart Card. This signal is a GPIO signal when the Smart Card Port is not being used. Input or Output SIMDATA Signal Description SIM reset—This signal is an output reset signal from the Smart Card port to the Smart Card. The Smart Card port can activate the reset of an attached Smart Card by driving SIMRESET low. This signal is a GPIO signal when the Smart Card port is not being used. Input SIM power enable—This active high output enables the external device that supplies VCC to the Smart Card. If this pin is driven high, the external device supplies power to the Smart Card. Driving the signal low cuts off power to card. This permits effective power management and power sequencing for Smart Card enable/disable. This signal is a GPIO signal when the Smart Card port is not being used. This signal has an on-chip 100 kΩ pull-down resistor. Preliminary 1-30 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Serial Audio Codec Port After reset, the default state of all serial audio codec pins is Hi-Z. For serial audio codec port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Table 1-18 Serial Audio Codec Port Signals Freescale Semiconductor, Inc... Signal Name STDA Signal Type State during Reset Input or Input Output Signal Description Audio codec transmit data— This output signal transmits serial data from the audio codec serial transmitter shift register. It is equipped with a 100kΩ pull-up resistor. This is a GPIO signal when STDA is not being used. Note: SRDA Input or Input Output Audio codec receive data — This input signal receives serial data and transfers the data to the audio codec receive shift register. It is equipped with a 100kΩ pull-down resistor. This is a GPIO signal when SRDA is not being used. Note: SCKA Input or Input Output Input or Input Output This signal is disabled if the alternate SRDA function on INT7 is selected. (See Table 1-12 on page 1-19.) Audio codec serial clock — This bidirectional signal provides the serial bit rate clock when only one clock is being used or the TxD clock otherwise. It is equipped with a 100kΩ pull-down resistor. This is a GPIO signal when the serial audio codec port is not being used. Note: SC0A This signal is disabled if the alternate STDA function on INT6 is selected. (See Table 1-12 on page 1-19.) This signal is disabled if the alternate SCKA function on ROW7 is selected. (See Table 1-14 on page 1-22.) Audio codec serial clock 0—This signal’s function is determined by the SCLK mode. • Synchronous mode—serial I/O flag 0 • Asynchronous mode—receive clock I/O This is a GPIO signal when SC0A is not being used. SC1A Input or Input Output Audio codec serial clock 1—This signal’s function is determined by the SCLK mode. • Synchronous mode—serial I/O flag 0 • Asynchronous mode—receiver frame sync I/O This is a GPIO signal when SC1A is not being used. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-31 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-18 Serial Audio Codec Port Signals (Continued) Signal Name Freescale Semiconductor, Inc... SC2A Signal Type State during Reset Input or Input Output Signal Description Audio codec serial clock 2—This signal’s function is determined by the SCLK mode. • Synchronous mode—transmitter and receiver frame sync I/O • Asynchronous mode—transmitter frame sync I/O It is equipped with a 100kΩ pull-down resistor. This is a GPIO signal when SC2A is not being used. Note: This signal is disabled if the alternate SC2A function on ROW6 is selected. (See Table 1-14 on page 1-22.) Baseband Codec Port After reset, the default state of the baseband codec port pins is Hi-Z. For baseband codec port signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Table 1-19 Baseband Codec Port Signals Signal Name STDB Signal Type Output State during Reset Input Input or Output SRDB Input Baseband codec transmit data— This output signal transmits serial data from the baseband codec serial transmitter shift register. This signal is equipped with a 100 pull-up resistor. This is a GPIO signal when STDB is not being used. Input Input or Output SCKB Signal Description Input or Input Output Baseband codec receive data — This input signal receives serial data and transfers the data to the baseband codec receive shift register. This signal is equipped with a 100kΩ pull-down resistor. This is a GPIO signal when SRDB is not being used. Baseband codec serial clock — This bidirectional signal provides the serial bit rate clock when only one clock is being used or the TxD clock otherwise. This signal is equipped with a 100kΩ pull-down resistor. This is a GPIO signal when the serial baseband codec port is not being used. Preliminary 1-32 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Table 1-19 Baseband Codec Port Signals (Continued) Freescale Semiconductor, Inc... Signal Name Signal Type State during Reset Signal Description SC0B Input or Input Output Baseband codec serial clock 0—This signal’s function is determined by the SCLK mode. • Synchronous mode—serial I/O flag 0 • Asynchronous mode—receive clock I/O This signal is equipped with a 100kΩ pull-down resistor. This is a GPIO signal when SC0B is not being used. SC1B Input or Input Output Baseband codec serial clock 1—This signal’s function is determined by the SCLK mode. • Synchronous mode—serial I/O flag 0 • Asynchronous mode—receiver frame sync I/O This signal is equipped with a 100KkΩ pull-down resistor. This is a GPIO signal when SC1B is not being used. SC2B Input or Input Output Baseband codec serial clock 2—This signal’s function is determined by the SCLK mode. • Synchronous mode—transmitter and receiver frame sync I/O • Asynchronous mode—transmitter frame sync I/O This signal is equipped with a 100kΩ pull-down resistor. This is a GPIO signal when SC2B is not being used. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-33 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Emulation Port After reset, the default state for the emulation port pins is GPI. Table 1-20 Emulation Port Signals Signal Name Freescale Semiconductor, Inc... SIZ0–SIZ1 Signal Type State during Reset Input or Input Output Signal Description Data size 0–1—These signals encode the data size for the current MCU access. When not programmed as data size signals, these are GPIO signals. The signals have on-chip 100 kΩ pull-up resistors. PSTAT0– PSTAT3 Input or Input Output Pipeline state 0–3—These signals encode the internal MCU execution unit status. When not programmed as pipeline state signals, these are GPIO signals. The signals have on-chip 100 kΩ pull-up resistors. Preliminary 1-34 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description Debug Port Control If the MUX_CTL signal is driven high, the alternate MCU_DE and DSP_DE signal locations are selected, and this interface is disabled. For debug port control signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output Table 1-21 Debug Port Control Signals Freescale Semiconductor, Inc... Signal Name MCU_DE Signal Type Input State during Reset Input Output DSP_DE Input Output Signal Description Microcontroller debug event—As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the MCU has entered the debug mode. This signal is equipped with an open-drain 47kΩ pull-up resistor. When the MCU enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts MCU_DE as an output signal for three clock cycles. Input Digital signal processor debug event—As an input signal, this signal provides a means to enter the debug mode of operation from an external command converter. An an output signal, it acknowledges that the DSP has entered the debug mode.This signal is equipped with an open-drain 4kΩ K pull-up resistor. When the DSP enters the debug mode due to a debug request or as the result of meeting a breakpoint condition, it asserts DSP_DE as an output signal for three clock cycles. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 1-35 Freescale Semiconductor, Inc. Pin and Signal Descriptions DSP56651 Signal Description JTAG Port When the bottom connector pins are selected as a debug port by holding the MUX_CTL pin at a logic high, the dedicated JTAG pins become inactive. That is, they are disconnected from the JTAG TAP controller. For JTAG signals equipped with resistors, all pull-ups and pull-downs are automatically disconnected when the pin is an output. Freescale Semiconductor, Inc... Table 1-22 JTAG Port Signals Signal Name Signal Type State during Reset Signal Description TMS Input Input Test mode select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal 47 kΩ pull-up resistor. MUX_CTL high: INT7 is connected to the JTAG TAP controller and functions as TMS, see Table 1-12 on page 1-19.) TDI Input Input Test data input—TDI is a serial test data input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal 47 kΩ pull-up resistor. MUX_CTL high: RxD is connected to the JTAG TAP controller and functions as TDI, see Table 1-15 on page 1-26.) TDO Output Tristated Test data output—TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. MUX_CTL high: TxD is connected to the JTAG TAP controller and functions as TDO, see Table 1-15 on page 1-26.) TCK Input Input Test clock—TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal 47 kΩ pull-up resistor. MUX_CTL high: ROW7 is connected to the JTAG TAP controller and functions as TCK, see Table 1-14 on page 1-22.) TRST Input Input Test reset—TRST is an active-low Schmitt-trigger input signal used to asynchronously initialize the test controller. TRST has an internal 47 kΩ pull-up resistor. MUX_CTL high: INT6 is connected to the JTAG TAP controller and functions as TRST, see Table 1-12 on page 1-19.) TEST Input Input Factory test mode—Selects factory test mode. Reserved. This pin MUST be connected to ground. Preliminary 1-36 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 2 SPECIFICATIONS Freescale Semiconductor, Inc... GENERAL CHARACTERISTICS The DSP56651 is fabricated in high-density CMOS. The DSP56651 specifications are preliminary from design simulations and may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after full characterization and device qualifications are complete. MAXIMUM RATINGS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. Specifications Thermal characteristics Table 2-1 Absolute Maximum Ratings (GND = 0 V) Rating Symbol Value Unit Internal supply voltage VCCI –0.3 to +2.75 V External supply voltage VCCE –0.3 to +3.6 V TA –40 to +85 °C TSTG –55 to +125 °C Operating temperature range Freescale Semiconductor, Inc... Storage temperature THERMAL CHARACTERISTICS Table 2-2 Thermal Characteristics Symbol BGA Value3 Unit Junction-to-ambient thermal resistance1 RθJA or θJA TBD ˚C/W Junction-to-case thermal resistance2 RθJC or θJC TBD ˚C/W Thermal characterization parameter ΨJT TBD ˚C/W Characteristic Notes: 1. 2. 3. Junction-to-ambient thermal resistance is based on measurements on a horizontalsingle-sided printed circuit board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. These are measured values; testing is not complete. Values were measured on a nonstandard four-layer thermal test board (two internal planes) at one watt in a horizontal configuration. Preliminary 2-2 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics Characteristics Symbol Min Typ Max Units Internal supply voltage VCCI 2.3 — 2.5 V External supply voltage VCCE VCCI — 3.4 V VCCHQ VCCE — 3.4 V Input high voltage VIH 0.7 × VCCE — VCCE + 0.2 V Input low voltage VIL –0.3 — 0.2 × VCCE V Input leakage current IIN –10 — 10 µA Output high voltage (IOH = –400 µA) VOH 0.75 × VCCE — VCCE V Output low voltage (IOL = 800 µA) VOL 0 — 0.18 × VCCE V Total stop mode (DSP and MCU stopped, PLL powered down, timers disabled) ICC_STOP — 60 — µA DSP run current at 58.8 MHz (MCU stopped, timers disabled, DSP running algorithm from internal memory, BBP and SAP active) ICCDSP_RUN — 35 — mA PLL supply current (16.8 MHz input, DSP freq = 58.8 MHz, MCU clock = 16.8 MHz) ICC_PLL — 1.6 — mA DSP wait current at 58.8 MHz (MCU stopped, timers disabled, BBP and SAP active) ICC_DSP_WAIT — 4.5 — mA MCU run current at 16.8 MHz (DSP and DSP PLL stopped, timers disabled, MCU peripherals ICC_MCU_RUN active) — 9 — mA MCU doze current at 16.8 MHz (DSP and DSP PLL stopped, timers disabled, MCU peripherals active) ICC_MCU_DOZE — 3 — mA MCU wait current at 16.8 MHz (DSP and DSP PLL stopped, timers disabled, MCU peripherals active) ICC_MCU_WAIT — 3 — mA Timer current (MCU and DSP stopped; 16.8 MHz to timer) ICC_TIMER — 500 — µA CIN — — TBD pF — 50% 100% 180% — Freescale Semiconductor, Inc... I/O predriver supply voltage Input capacitance per pin Pull-up resistor Note: 1. value1 Applies to 22 K and 47 K resistors. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. Specifications Clock Requirements CLOCK REQUIREMENTS Table 2-4 Clock Requirements Freescale Semiconductor, Inc... Characteristics Symbol Min Typ Max Units CKIH input frequency f1 0 — 16.8 MHz CKIL input frequency f2 0 32.768 f1 kHz MCU internal frequency fMCU-CLK 0 — 16.8 MHz DSP internal frequency fDSP-CLK — — 58.8 MHz CKIH input amplitude VI-CKIH 500 — — mVPP CKIL input low voltage VIL-CKIL -0.3 — 0.2xVCCE V CKIL input high voltage VIH-CKIL VCCI — 2.77 V CKIH input impedance RI-CKIH High TBD — — MΩ EXTERNAL BUS INTERFACE REQUIREMENTS When the MCU is operating at 16.8 MHz, the bus interface can access 100 ns access time external memory with one wait state or 15 ns access time external memory with no wait states. AC ELECTRICAL CHARACTERISTICS The characteristics listed in this section are given for VDDI = 2.4 V and VDDE = 3.3 V with a capacitive load of 50 pF. Preliminary 2-4 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Internal Clocks INTERNAL CLOCKS For each occurrence of TDH, TDL, TDC, or IDCYC, substitute with the numbers in Table 2-6. DF, MF, and PDF are the DSP PLL division, multiplication, and predivision factors set in registers. Table 2-5 DSP Clocks Characteristics Symbol Min Max Unit EfD 0 16.8 MHz ETDC 59.5 59.5 ∞ 273100 ns ns Freescale Semiconductor, Inc... DSP PLL input frequency DSP PLL input clock cycle time • with PLL disabled • with PLL enabled Table 2-6 Internal DSP Clocks Characteristics Symbol Expression Internal DSP operation frequency with PLL enabled fD (EfD × MF) / (PDF × DF) Internal DSP operation frequency with PLL disabled fD EfD/2 Internal DSP clock high period • with PLL disabled • with PLL enabled and MF ≤ 4 ETDC (Min) 0.49 × ETDC × PDF × DF/MF (Max) 0.51 × ETDC × PDF × DF/MF (Min) 0.47 × ETDC × PDF × DF/MF (Max) 0.53 × ETDC × PDF × DF/MF TDH • with PLL enabled and MF > 4 Internal clock low period • with PLL disabled • with PLL enabled and MF ≤ 4 ETDC (Min) 0.49 × ETDC × PDF × DF/MF (Max) 0.51 × ETDC × PDF × DF/MF (Min) 0.47 × ETDC × PDF × DF/MF (Max) 0.53 × ETDC × PDF × DF/MF TDL • with PLL enabled and MF > 4 Internal clock cycle time with PLL enabled TDC ETDC × PDF × DF/MF Internal clock cycle time with PLL disabled TDC 2 × ETDC IDCYC TDC DSP instruction cycle time Table 2-7 MCU Clocks Characteristics Symbol Min Max Unit fM 0 16.8 MHz TMC 59.5 ∞ ns Frequency of the internal MCU-CLK clock Internal MCU-CLK clock cycle time Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. Specifications Phase-Locked Loop (PLL) Characteristics PHASE-LOCKED LOOP (PLL) CHARACTERISTICS Table 2-8 Phase-Locked Loop (PLL) Characteristics Characteristics VCO frequency when PLL enabled1 Expression Min Max Unit MF × EfD × 2 / PDF 30 120 MHz PLL external capacitor (PCAP pin to VCCP) • MF ≤ 4 Freescale Semiconductor, Inc... CPCAP 2 • Notes: 2. pF (1100 • MF) recommended (830 • MF) minimum (1470 • MF) maximum MF > 4 1. (680 • MF-120) recommended (580 • MF-100) minimum (780 • MF-140) maximum The VCO output is further divided by 2 when PLL is enabled. If the division factor (DF) is 1, the operating frequency is VCO . ------------2 CPCAP is the value of the PLL capacitor (connected between PCAP pin and VCCP). (The recommended value for Cpcap is (680 × MF – 120) pF for MF ≤ 4 and (1100 × MF) pF for MF > 4.) RESET, MODE SELECT, AND INTERRUPT TIMING Table 2-9 Reset, Mode Select, and Interrupt Timing Num Characteristics Expression MCU @16.8 MHz DSP @58.8 MHz Min Max — 1 RESET_IN duration to guarantee reset 3 × TCKIL + 0.05 91.6 2 Delay from RESET_IN assertion to RESET_OUT assertion min: 4.5 × TCKIL max: 5.5 × TCKIL 137.33 7 × TCKIL 213.62 Unit µs µs 167.85 — µs 167.85 µs µs 107 — µs — 0 — ns Minimum edge-triggered DSP_IRQ assertion width — 10 — ns Minimum edge-triggered DSP_IRQ deassertion width — 10 — ns 3 Duration of RESET_OUT assertion 4 Delay from RESET_IN assertion to all pins at Reset Value (periodically sampled and not 100% tested) min: 4.5 × TCKIL max: 5.5 × TCKIL 137.33 5 MOD select setup time 3.5 × TCKIL + 0.02 6 MOD select hold time 7 8 Preliminary 2-6 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications RESET, Mode Select, and Interrupt Timing Table 2-9 Reset, Mode Select, and Interrupt Timing (Continued) Freescale Semiconductor, Inc... Num Characteristics MCU @16.8 MHz DSP @58.8 MHz Expression Min Max Unit 9 Minimum edge-triggered INTn width high — TBD — ns 10 Minimum edge-triggered INTn width low — TBD — ns RESET_IN 1 RESET_OUT All Pins 3 2 4 Reset Value AA1679 Figure 2-1 Reset Timing RESET_OUT 5 6 MOD AA1680 Figure 2-2 Operating Mode Select Timing Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-7 Freescale Semiconductor, Inc. Specifications RESET, Mode Select, and Interrupt Timing DSP_IRQ 7 DSP_IRQ 8 AA1681 Freescale Semiconductor, Inc... Figure 2-3 DSP External Interrupt Timing (Negative Edge-Triggered) INTn 9 INTn 10 AA1682 Figure 2-4 INT0-INT7 External Interrupt Timing Preliminary 2-8 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications External Interface Module (EIM) Timing EXTERNAL INTERFACE MODULE (EIM) TIMING The EIM provides the bus interface between the DSP56651 and external memory and peripherals. It uses the external address bus, data bus, bus control signals, and the chip select signals. Table 2-10 EIM External Bus Output AC Timing Specifications1 MCU @16.8 MHz Freescale Semiconductor, Inc... Num Characteristics Unit Min Max 11 MCU_CLK rise to address and R/W valid2 — 4 ns 12 MCU_CLK rise to address and R/W invalid (output hold) 0 — ns 13 MCU_CLK rise to CS asserted — 4 ns 14 MCU_CLK rise to CS deasserted (output hold) 0 — ns 15 MCU_CLK fall to OE, EB asserted (read, OEA = 0), EB asserted (write)3 — 4 ns 16 MCU_CLK rise to OE, EB asserted (read, OEA = 1)3 — 4 ns 0 — ns MCU_CLK rise to EB deasserted (output hold) (write, WEN = 0) 0 — ns 18 MCU_CLK fall to EB deasserted (output hold) (write, WEN = 1) 0 — ns 19 MCU_CLK fall to OE, EB asserted (WSC = 0)3 — 4 ns 0 — ns 17 MCU_CLK rise to OE, EB deasserted (output hold) (read)3 0)3 20 MCU_CLK rise to OE, EB deasserted (output hold) (WSC = 21 Data-in valid to MCU_CLK rise (setup) 15 — ns 22 MCU_CLK rise to data-in invalid (hold) 0 — ns 23 MCU_CLK rise to data-out valid — 4 ns 24 MCU_CLK rise to data-out invalid (output hold) 0 — ns 25 MCU_CLK rise to data-out high impedance — 4 ns 26 MCU_CLK fall to data-out valid (WSC = 0) — 6 ns 27 MCU_CLK rise to data-out invalid (output hold) (WSC = 0) 0 — ns 28 MCU_CLK rise to data-out high impedance (WSC = 0) — 6 ns Note: 1. 2. 3. The following notes apply to this table: • Output timing is measured at the pin. The specifications assume a capacitive load of 50 pF. • R/W, EB, and CS deassertion to address change is 0 ns minimum. • MCU_CLK can be viewed on the CKO pin by programming the clock control register (CKCTL). Address setup to R/W and CS assertion is 0 ns minimum. EB outputs are asserted for reads if the EBC bit in the corresponding CS control register is clear. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-9 Freescale Semiconductor, Inc. Specifications External Interface Module (EIM) Timing MCU_CLK 11 ADDRESS R/W 12 CS 13 Freescale Semiconductor, Inc... 14 15 OE, EB (OEA=0) (READ) 17 16 OE, EB (OEA=1) (READ) 17 15 EB (WEN=0) (WRITE) 17 15 EB (WEN=1) (WRITE) 18 19 OE, EB (WSC=0) 20 21 DATA in (READ) 22 23 25 DATA out (WRITE) 24 26 28 DATA out (WSC=0) (WRITE) 27 AA1683 Figure 2-5 EIM Read/Write Timing Preliminary 2-10 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Smart Card Timing SMART CARD TIMING Table 2-11 Smart Card Port to Smart Card AC Timing CKIH @16.8 MHz Freescale Semiconductor, Inc... Num Characteristics Unit Min Max 31 SIMRESET low to SIMCLK low 1.18 200/f µs 32 SIMCLK deactivated to SIMDATA tri-state to low 1.18 200/f µs 33 SIMDATA low to PWR_EN low 1.18 200/f µs 34 SIMRESET low 40000/f — ns 35 SENSE high to SIMRESET low 57 76 µs Note: “f” is CKIH/4 (for 5 V sims) or CKIH/5 (for 3 V sims), as programmed in the Smart Card port. SENSE 35 34 SIMRESET 31 SIMCLK 32 38 SIMDATA 33 PWR_EN AA1684 Figure 2-6 Smart Card Interface Power Down AC Timing Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-11 Freescale Semiconductor, Inc. Specifications QSPI Timing QSPI TIMING The QSPI uses the signals in the serial control port to select individual serial peripherals (using the SPI chip select signals) and transfer data between peripherals and the DSP56651. Table 2-12 QSPI Timing Freescale Semiconductor, Inc... Num Characteristics 301 Cycle time 302 Symbol Expression MCU_CLK @ 16.8 MHz Min Max Unit TQCYC — 1 504 TMC Clock (SCK) high or low time TSW — — 252 TMC 303 Chip-select lag time TLAG — 1 ∞ TQCYC 304 Inter-queue transfer delay TTD — 1 ∞ TQCYC 305 Chip-select lead time TLEAD — 1 128 TQCYC 306 Data setup time (inputs) TSU — 0 — nS 307 Data hold time (inputs) THI — 0.5 — TQCYC 308 Data valid (after SCK edge) TV — — 6 nS 309 Data hold time (outputs) THO — –2 — nS 310 Rise time TI — — 10 nS 311 Fall time TF — — 10 nS 305 303 PCS [4:0] 301 310 304 302 SCK (CSPOL = 0) 304 SCK (CSPOL = 1) MISO MSB IN DATA 308 MOSI 307 311 306 MSB OUT MSB IN LSB IN 309 DATA LSB OUT MSB OUT AA1685 Figure 2-7 QSPI Timings for CPHA = 0 Preliminary 2-12 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Audio Serial Codec and Baseband Serial Codec Timing 303 305 PCS [4:0] 310 301 304 SCK (CSPOL = 0) 302 SCK (CSPOL = 1) 302 Freescale Semiconductor, Inc... MISO MSB IN DATA 308 MOSI 307 311 306 MSB IN LSB IN 309 MSB OUT DATA LSB OUT MSB OUT AA1686 Figure 2-8 QSPI Timings for CPHA = 1 AUDIO SERIAL CODEC AND BASEBAND SERIAL CODEC TIMING The audio serial codec port (also called the serial audio port or SAP) and the baseband serial codec port (also called the baseband port or BBP) have the same timing specifications. The timing table uses the following acronyms to describe the signal parameters: tSSICC TXC (SCKA/SCKB Pin) RXC (SC0A/SC0B or SCKA/SCKB Pin) FST (SC2A/SC2B Pin) FSR (SC1A/SC1B or SC2A/SC2B Pin) i ck x ck i ck a = = = = = = = = i ck s = bl = wl = wr = BBP/SAP clock cycle time Transmit clock Receive clock Transmit frame sync Receive frame sync Internal clock External Clock Internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) Internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) Bit length Word length Word length relative Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-13 Freescale Semiconductor, Inc. Specifications Audio Serial Codec and Baseband Serial Codec Timing Table 2-13 SAP and BBP Timing Num Characteristics Symbol Expression DSP @ 58.8 MHz Case Unit Freescale Semiconductor, Inc... Min Max 4 × TDC 3 × TDC 430 Clock cycle1 431 Clock high period for internal clock for external clock — Clock low period for internal clock for external clock — 433 RXC rising edge to FSR out (bl) high — — — — 45.1 x ck 26.8 i ck a ns ns 434 RXC rising edge to FSR out (bl) low — — — — 45.1 x ck 26.8 i ck a ns ns 435 RXC rising edge to FSR out (wr) high2 — — — — 47.6 x ck 29.3 i ck a ns ns 436 RXC rising edge to FSR out (wr) low2 — — — — 47.6 x ck 29.3 i ck a ns ns 437 RXC rising edge to FSR out (wl) high — — — — 45.9 x ck 25.6 i ck a ns ns 438 RXC rising edge to FSR out (wl) low — — — — 45.1 x ck 26.8 i ck a ns ns 439 Data in setup time before RXC (SCK in synchronous mode) falling edge — — 0.0 23.2 — — x ck i ck ns ns 440 Data in hold time after RXC falling edge — — 6.1 3.6 — — x ck i ck ns ns 441 FSR input (bl, wr) high before RXC falling edge2 — — 1.2 28.0 — — x ck i ck a ns ns 442 FSR input (wl) high before RXC falling edge — — 1.2 28.0 — — x ck i ck a ns ns 443 FSR input hold time after RXC falling edge — — 3.6 0.0 — — x ck i ck a ns ns 444 Flags input setup before RXC falling edge — — 0.0 23.2 — — x ck i ck s ns ns 445 Flags input hold time after RXC falling edge — — 7.3 0.0 — — x ck i ck s ns ns 432 tSSICC 68 51 — — i ck x ck ns ns 2 × TDC – 12.2 21.8 1.5 × TDC 25.5 — — ick xck ns ns 2 × TDC – 12.2 21.8 1.5 × TDC 25.5 — — ick xck ns ns Preliminary 2-14 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Audio Serial Codec and Baseband Serial Codec Timing Table 2-13 SAP and BBP Timing (Continued) Num Characteristics Symbol Expression DSP @ 58.8 MHz Case Unit Freescale Semiconductor, Inc... Min Max 446 TXC rising edge to FST out (bl) high — — — — 35.4 x ck 18.3 i ck ns ns 447 TXC rising edge to FST out (bl) low — — — — 37.8 x ck 20.7 i ck ns ns 448 TXC rising edge to FST out (wr) high2 — — — — 37.8 x ck 20.7 i ck ns ns 449 TXC rising edge to FST out (wr) low2 — — — — 40.3 x ck 23.2 i ck ns ns 450 TXC rising edge to FST out (wl) high — — — — 36.6 x ck 19.5 i ck ns ns 451 TXC rising edge to FST out (wl) low — — — — 37.8 x ck 20.7 i ck ns ns 452 TXC rising edge to data out enable from high impedance — — — — 37.8 x ck 20.7 i ck ns ns 454 TXC rising edge to data out valid — 35 + 0.5 × TDC — — 43.5 x ck 25.6 i ck ns ns 455 TXC rising edge to data out high impedance3 — — — — 37.8 x ck 19.5 i ck ns ns 457 FST input (bl, wr) setup time before TXC falling edge2 — — 2.0 21.0 — — 458 FST input (wl) to data out enable from high impedance3 — — — 32.9 460 FST input (wl) setup time before TXC falling edge — — 2.0 21.0 461 FST input hold time after TXC falling edge — — 4.0 0.0 462 Flag output valid after TXC rising edge — — — — Note: 1. 2. 3. x ck i ck ns ns — ns — — x ck i ck ns ns — — x ck i ck ns ns 39.0 x ck 22.0 i ck ns ns For internal clock, external clock cycle is defined by ICYC and BBP/SAP control register. Word relative frame sync signal wave form, relates to clock, as the bit length frame sync signal wave form, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. Periodically sampled and not 100% tested. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-15 Freescale Semiconductor, Inc. Specifications Audio Serial Codec and Baseband Serial Codec Timing 430 431 TXC (Input/Output) 432 446 Freescale Semiconductor, Inc... FST (Bit) Out FST (Word) Out 447 450 451 Data Out 455 455 457 452 FST (Bit) In First Bit Last Bit 460 461 FST (Word) In Flags Out 458 461 460 462 AA1687 Note: In the network mode, output flag transitions can occur at the start of each time slot within the frame. In the normal mode, the output flag state is asserted for the entire frame period. Figure 2-9 BBP and SAP Transmitter Timing Preliminary 2-16 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications Audio Serial Codec and Baseband Serial Codec Timing 430 431 432 RXC (Input/Output) Freescale Semiconductor, Inc... 433 434 FSR (Bit) Out FSR (Word) Out 437 438 Data In 440 439 FSR (Bit) In First Bit Last Bit 443 441 FSR (Word) In Flags In 442 444 443 445 AA1688 Figure 2-10 BBP And SAP Receiver Timing Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-17 Freescale Semiconductor, Inc. Specifications JTAG Port Timing JTAG PORT TIMING Table 2-14 JTAG Timing DSP @ 58.8 MHz Freescale Semiconductor, Inc... Num Characteristics Expression Unit Min Max 1/(3 × TDC) 0.0 19.6 MHz 500 TCK frequency of operation 501 TCK cycle time in crystal mode — 45.0 — ns 502 TCK clock pulse width measured at 1.5 V — 20.0 — ns 503 TCK rise and fall times — 0.0 3.0 ns 504 Boundary scan input data setup time — 5.0 — ns 505 Boundary scan input data hold time — 24.0 — ns 506 TCK low to output data valid — 0.0 40.0 ns 507 TCK low to output high impedance — 0.0 40.0 ns 508 TMS, TDI data setup time — 5.0 — ns 509 TMS, TDI data hold time — 25.0 — ns 510 TCK low to TDO data valid — 0.0 44.0 ns 511 TCK low to TDO high impedance — 0.0 44.0 ns 512 TRST assert time — 100.0 — ns 513 TRST setup time to TCK low — 40.0 — ns 501 TCK (Input) VIH 502 502 VM VM VIL 503 503 AA0496 Figure 2-11 Test Clock Input Timing Diagram Preliminary 2-18 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Specifications JTAG Port Timing TCK (Input) VIH VIL 504 Data Inputs 505 Input Data Valid 506 Freescale Semiconductor, Inc... Data Outputs Output Data Valid 507 Data Outputs 506 Data Outputs Output Data Valid AA0497 Figure 2-12 Boundary Scan (JTAG) Timing Diagram TCK (Input) 513 TRST (Input) AA1689 512 Figure 2-13 TRST Timing Diagram Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 2-19 Freescale Semiconductor, Inc. Specifications JTAG Port Timing TCK (Input) VIH VIL 508 TDI TMS (Input) 509 Input Data Valid 510 Freescale Semiconductor, Inc... TDO (Output) Output Data Valid 511 TDO (Output) 510 TDO (Output) Output Data Valid AA0498 Figure 2-14 Test Access Port Timing Diagram Preliminary 2-20 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 3 PACKAGING Freescale Semiconductor, Inc... PACKAGE INFORMATION This section provides information about the available packages for this product. The DSP56651 is available in a 196-pin plastic ball grid array (PBGA) package. The DSP56651 part (RAM-based DSP program memory) is delivered in a 17-mm (outline) PBGA package having a solder-ball footprint identical to that of the 15 mm PBGA. Compatibility between the footprints of the two packages is maintained to minimize impact to the customer’s application board routing, such that the same board can be used for both the DSP56651 and DSP56652. 196 PBGA (GT), 17 x 17 mm, with Footprint of 15-mm PBGA The DSP56651 is offered in the non-JEDEC standard, 17-mm PBGA package. The package is “non-standard” in that the single outermost row of solder balls in the array is removed, leaving a 14 x 14 array (196) of solder balls. This package footprint is identical to that of the JEDEC standard 15 mm (outline) 196 PBGA. The pitch of the solder balls is 1 mm. Refer to the following table and figure for package drawing and dimensions. Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 3-1 Freescale Semiconductor, Inc. Packaging PBGA Package Dimensions PBGA PACKAGE DIMENSIONS Table 3-1 Dimensions for 196 PBGA (17-mm Outline) MILLIMETERS Freescale Semiconductor, Inc... DIM MIN MAX A 1.32 1.75 A1 0.27 0.47 A2 0.30 0.40 A3 0.75 0.88 b 0.35 0.65 D 17.00 BASIC D1 13.00 BASIC D2 TBD 17.00 E 17.00 BASIC E1 13.00 BASIC E2 TBD 17.00 e 1.00 BASIC R1 — 2.50 Preliminary 3-2 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Packaging PBGA Package Mechanical Drawing PBGA PACKAGE MECHANICAL DRAWING D Freescale Semiconductor, Inc... E E2 2x R R1 D2 4X R R1 A2 D1 e/2 13x, e A3 P A1 N M L K J H G F E D C B A A E1 e/2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 196x, b AA1696 Figure 3-1 DSP56651 Mechanical Drawing Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 3-3 Freescale Semiconductor, Inc. Packaging Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56651 packaging is available by facsimile through Motorola's Mfax system. Call the following number to obtain information by facsimile: (602) 244-6591 Freescale Semiconductor, Inc... The Mfax automated system requests the following information: • The receiving facsimile telephone number including area code or country code • The caller’s personal identification number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. • The type of information requested: – Instructions for using the system – A literature order form – Specific part technical information or data sheets – Other information described by the system messages A total of three documents may be ordered per call. The DSP56651 196-pin PBGA package mechanical drawing is referenced as Case 1128-01 Rev. D. Preliminary 3-4 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 4 DESIGN CONSIDERATIONS Freescale Semiconductor, Inc... HEAT DISSIPATION An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation: Equation 1: T J = T A + ( P D × R θJA ) Where: TA = ambient temperature ˚C RθJA = package junction-to-ambient thermal resistance ˚C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R θJA = R θJC + R θCA Where: RθJA = package junction-to-ambient thermal resistance ˚C/W RθJC = package junction-to-case thermal resistance ˚C/W RθCA = package case-to-ambient thermal resistance ˚C/W RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or otherwise change the thermal dissipation capability of the area surrounding the device on a printed circuit board. This model is most useful for ceramic packages with heat sinks; Ninety percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the printed circuit board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the printed circuit board to which the package is mounted. Again, if the Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 4-1 Freescale Semiconductor, Inc. Design Considerations Heat Dissipation estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Freescale Semiconductor, Inc... A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: • To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. • To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. • If the temperature of the package case (TT) as determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD. As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, this value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or ΨJT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. Note: Table 2-2 on page 2-2 of this document contains the package thermal values for this chip. Preliminary 4-2 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Design Considerations Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS Freescale Semiconductor, Inc... CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Use the following list of recommendations to assure correct DSP operation: • Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. • Use at least four 0.1 µF bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. • Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. • Use at least a four-layer printed circuit board (PCB) with two inner layers for VCC and GND. • Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the R/W, DSP_IRQ, and INT0–INT7 signals. • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. • All inputs must be terminated (i.e., not allowed to float) using CMOS levels. • Take special care to minimize noise levels on the PLL supply pins (both VCC and GND). Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 4-3 Freescale Semiconductor, Inc. Design Considerations Freescale Semiconductor, Inc... Electrical Design Considerations Preliminary 4-4 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. SECTION 5 ORDERING INFORMATION Table 5-1 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Freescale Semiconductor, Inc... Table 5-1 DSP56651 Ordering Information Part Package Type DSP56651 Plastic ball grid array (PBGA) Pin Count Order Number 196 PC56651GC Preliminary MOTOROLA DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com 5-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Ordering information Preliminary 5-2 DSP56651 Technical Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. M•CORE, Mfax, and OnCE are trademarks of Motorola, Inc. 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How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1 (800) 441-2447 (within US) 1 (303) 675-2140 (outside US) 1 (303) 675-2150 (direct FAX) Mfax™: [email protected] TOUCHTONE (602) 244-6609 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-2662928 Technical Resource Center: 1 (800) 521-6274 Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office, 141 4-32-1, Nishi-Gotanda Shinagawa-ku, Tokyo, Japan 81-3-5487-8488 Internet: www.motorola-dsp.com DSP Helpline [email protected] For More Information On This Product, Go to: www.freescale.com