with Sem, In t, Busy CY7C006 CY7C016 16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy Features • True dual-ported memory cells which allow simultaneous reads of the same memory location • 16K x 8 organization (CY7C006) • 16K x 9 organization (CY7C016) • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns • Low operating power: ICC = 140 mA (typ.) • Fully asynchronous operation • Automatic power-down • TTL compatible • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device • Busy arbitration scheme provided • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Available in 68-pin PLCC (7C006), 64-pin (7C006) and 80-pin (7C016) TQFP • Pin compatible and functional equivalent to IDT7006/IDT7016 schemes are included on the CY7C006/016 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C006/016 can be utilized as a standalone 128-/144-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16-/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16-/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Functional Description Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags, BUSY and INT, are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a Chip Enable (CE) pin or SEM pin. The CY7C006 and CY7C016 are high-speed CMOS 16K x 8 and 16K x 9 dual-port static RAMs. Various arbitration The CY7C006 and CY7C016 are available in 68-pin PLCC (CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP. Logic Block Diagram R/WL R/W R CE L OEL CE R OE R (7C016) I/O 8L I/O7L I/O0L I/O 8R (7C016) I/O 7R I/O CONTROL I/O CONTROL I/O 0R [1,2] [1,2] BUSYL BUSYR A 13L A 13R ADDRESS DECODER A 0L CE L OE L ADDRESS DECODER MEMORY ARRAY INTERRUPT SEMAPHORE ARBITRATION R/W L SEM L INTL  A 0R CER OER R/W R SEM R INTR C006-1 M/S Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 22, 1999 CY7C006 CY7C016 Pin Configurations 10 I/O5L GND 13 A5L A4L 58 A3L A2L A1L A11L A10L A9L A8L A7L A6L 64 63 62 61 65 A12L 66 VCC A13L CEL 3 68 67 SEML 4 NC R/WL 5 2 1 I/O0L NC(I/O8L) OEL 56 55 14 15 54 16 17 53 CY7C006 18 52 51 50 19 20 49 48 21 22 23 24 47 A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R 42 43 A6R 41 40 A8R A7R A9R 38 39 37 A11R A10R 36 35 GND A12R A13R 32 33 34 31 CER NC 44 30 26 SEMR 46 45 29 25 I/O7R I/O3R I/O4R I/O5R I/O6R 60 59 57 OER R/WR I/O2R VCC 12 27 28 VCC GND I/O0R I/O1R 11 NC(I/O8R ) I/O6L I/O7L 7 6 I/O1L 9 I/O2L I/O3L I/O4L 8 68-Pin PLCC Top View C006-2 49 54 A6L A5L A12L 56 55 A8L A7L VCC 57 51 50 CEL A13L 59 52 SEML 60 A9L R/WL 62 61 53 OEL 63 A11L A10L I/O0L 64 58 I/O1L 64-Pin TQFP Top View I/O2L 1 48 A4L I/O3L I/O4L 2 47 3 4 46 45 A3L A2L 5 44 I/O6L I/O7L 6 43 7 42 VCC 8 I/O5L GND CY7C006 41 A1L A0L INTL BUSYL GND M/S 14 15 35 34 A2R I/O5R 16 33 A4R 2 A6R A5R A8R A7R A9R A11R A10R A12R GND CER A13R SEMR OER R/WR I/O7R I/O6R Note: 3. I/O for CY7C016 only. 32 I/O3R I/O4R 30 31 A0R A1R 29 36 28 13 27 VCC 25 26 37 24 12 23 INTR I/O2R 22 38 21 11 19 20 40 39 18 9 10 17 GND I/O0R I/O1R BUSYR A3R C006-3 CY7C006 CY7C016 Pin Configurations (continued) A11L A10L A9L A8L A7L A6L 67 66 65 64 63 62 61 NC NC A12L 68 NC 69 CE L NC A13L SEM L 74 VCC R/W L 75 70 OE L 76 72 71 I/O8L 78 77 73 I/O1L I/O0L 1 79 NC I/O 2L I/O 3L 80 80-Pin TQFP Top View 60 NC A5L A4L 2 59 I/O 4L 3 4 58 57 I/O 5L 5 56 A3L A2L GND I/O 6L 6 55 A1L 7 54 A0L I/O 7L 8 53 V CC 9 10 52 51 11 50 INTL BUSYL GND M/S 12 49 BUSYR 13 48 INTR I/O2R 14 47 V CC 15 16 46 45 A0R A1R 17 44 I/O 5R I/O 6R 18 19 43 42 A4R NC 20 41 NC 38 39 40 NC NC A5R 37 A6R A7R 35 36 34 A9R A8R 33 29 30 A 13R 32 28 NC A11R A10R 27 NC 31 26 CER A12R 25 SEMR GND 23 24 R/WR OER 22 I/O7R 21 I/O 3R I/O 4R CY7C016 I/O8R NC GND I/O0R I/O1R A2R A3R NC C006-4 Pin Definitions Left Port Right Port Description I/O0L–7L(8L) A0L–13L CEL OEL R/WL SEML I/O0R–7R(8R) A0R–13R CER OER R/WR SEMR Data Bus Input/Output Address Lines Chip Enable Output Enable Read/Write Enable Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. INTL INTR BUSYL M/S VCC GND BUSYR Interrupt Flag. INTL is set when right port writes location 3FFE and is cleared when left port reads location 3FFE. INTR is set when left port writes location 3FFF and is cleared when right port reads location 3FFF. Busy Flag Master or Slave Select Power Ground 3 CY7C006 CY7C016 Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current for ISB1 (mA) 7C006-15 7C016-15 15 260 7C006-25 7C016-25 25 220 7C006-35 7C016-35 35 210 7C006-55 7C016-55 55 200 70 60 50 40 Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current .................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied ............................................. –55°C to +125°C Ambient Temperature 0°C to +70°C –40°C to +85°C Range Commercial Industrial Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V VCC 5V ± 10% 5V ± 10% DC Input Voltage......................................... –0.5V to +7.0V Electrical Characteristics Over the Operating Range 7C006-15 7C016-15 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA Min. Min. Typ. Max. Unit 2.4 V 0.4 2.2 VIL Input LOW Voltage IIX Input Leakage Current GND ≤ VI ≤ VCC IOZ Output Leakage Current Outputs Disabled, GND ≤ VO ≤ V CC ICC Operating Current VCC = Max., IOUT = 0 mA Outputs Disabled Com’l Standby Current (Both Ports TTL Levels) CEL and CER ≥ VIH, f = fMAX Com’l ISB2 Standby Current (One Port TTL Level) CEL or CER ≥ VIH, f = fMAX Com’l ISB3 Standby Current (Both Ports CMOS Levels) Both Ports CE and CER ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0 Com’l Standby Current (One Port CMOS Level) One Port CEL or CER ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≥ 0.2V, Active Port Outputs, f = fMAX Com’l ISB4 Max. 2.4 VIH ISB1 Typ. 7C006-25 7C016-25 0.4 2.2 V 0.8 –10 –10 170 +10 –10 +10 –10 260 Ind 50 70 Ind 110 170 3 15 Ind Ind Ind 100 150 V 0.8 V +10 µA +10 µA 160 220 mA 160 270 40 60 40 75 90 130 90 150 3 15 3 15 80 120 80 130 mA mA mA mA Notes: 4. Pulse width < 20 ns. 5. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 4 CY7C006 CY7C016 Electrical Characteristics (continued) 7C006-35 7C016-35 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA Min. Typ. 7C006-55 7C016-55 Max. Min. Typ. 2.4 2.4 2.2 Input LOW Voltage IIX Input Leakage Current GND ≤ VI ≤ VCC –10 +10 IOZ Output Leakage Current –10 +10 ICC Operating Current Outputs Disabled, GND ≤ VO ≤ V CC VCC = Max., IOUT = 0 mA Com’l Outputs Disabled Ind ISB1 Standby Current (Both Ports TTL Levels) CEL and CER ≥ VIH, f = fMAX Com’l Standby Current (One Port TTL Level) ISB4 0.4 V 2.2 VIL ISB3 V 0.4 VIH ISB2 Max. Unit V 0.8 0.8 V –10 +10 µA –10 +10 µA mA 150 210 140 200 150 250 140 240 30 50 20 40 Ind 30 65 20 55 CEL or CER ≥ VIH, f = fMAX Com’l 80 120 70 100 Ind 80 130 70 115 Standby Current (Both Ports CMOS Levels) Both Ports CE and CER ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0 Com’l 3 15 3 15 Ind 3 15 3 15 Standby Current (One Port CMOS Level) One Port CEL or CER ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, Active Port Outputs, f = fMAX Com’l 70 100 60 90 Ind 70 110 60 95 mA mA mA mA Capacitance Parameter Description Input Capacitance Output Capacitance CIN COUT Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF AC Test Loads and Waveforms 5V 5V R1=893Ω C = 30 pF R1=893Ω RTH =250Ω OUTPUT OUTPUT OUTPUT C = 5 pF C=30 pF R2=347Ω R2=347Ω VTH =1.4V (b) Thévenin Equivalent (a) Normal Load (Load 1) (Load) OUTPUT ALL INPUT PULSES 3.0V C = 30 pF GND 10% 90% 10% 90% ≤ 3 ns ≤ 3 ns Load (Load 2) (c) Three-State Delay (Load 3) C006-6 C006-5 C006-8 C006-9 Note: 6. Tested initially and after any design or process changes that may affect these parameters. 5 C006-7 CY7C006 CY7C016 Switching Characteristics Over the Operating Range 7C006-15 7C016-15 Parameter Description Min. Max. 7C006-25 7C016-25 Min. Max. 7C006-35 7C016-35 Min. Max. 7C006-55 7C016-55 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 15 tOHA Output Hold From Address Change tACE CE LOW to Data Valid 15 25 35 55 ns tDOE OE LOW to Data Valid 10 13 20 25 ns tLZOE[8, 9, 10] tHZOE[8, 9, 10] tLZCE[8, 9, 10] tHZCE[8, 9, 10] tPU tPD OE Low to Low Z 3 10 CE LOW to Power-Up 15 0 CE HIGH to Power-Down 15 0 15 0 25 ns 25 3 15 ns ns 25 0 35 ns ns 3 3 15 ns 55 3 3 3 10 55 35 3 3 3 CE HIGH to High Z 35 25 3 3 OE HIGH to High Z CE LOW to Low Z 25 15 ns ns 55 ns WRITE CYCLE tWC Write Cycle Time 15 25 35 55 ns tSCE CE LOW to Write End 12 20 30 45 ns tAW Address Set-Up to Write End 12 20 30 45 ns tHA Address Hold From Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE Write Pulse Width 12 20 25 40 ns tSD Data Set-Up to Write End 10 15 15 25 ns tHD tHZWE[9, 10] tLZWE[9, 10] tWDD tDDD Data Hold From Write End 0 0 0 0 ns BUSY R/W LOW to High Z R/W HIGH to Low Z 10 3 15 3 20 3 25 3 ns ns Write Pulse to Data Delay 30 50 60 80 ns Write Data Valid to Read Data Valid 25 30 35 60 ns TIMING tBLA BUSY LOW from Address Match 15 20 20 30 ns tBHA BUSY HIGH from Address Mismatch 15 20 20 30 ns tBLC BUSY LOW from CE LOW 15 20 20 30 ns tBHC BUSY HIGH from CE HIGH 15 17 25 30 ns tPS Port Set-Up for Priority tWB R/W LOW after BUSY LOW 0 0 tWH R/W HIGH after BUSY HIGH 13 17 tBDD BUSY HIGH to Data Valid 5 5 Note 13 5 Note 13 5 ns 0 0 ns 25 30 ns Note 13 Note 13 ns Notes: 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 8. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 9. Test conditions used are Load 3. 10. This parameter is guaranteed but not tested. 11. Must be met by the device writing to the RAM under all operating conditions. 12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 13. Test conditions used are Load 2. 14. tBDD is a calculated parameter and is the greater of tWDD – tPWE (actual) or tDDD – tSD (actual). 6 CY7C006 CY7C016 Switching Characteristics Over the Operating Range (continued) 7C006-15 7C016-15 Parameter Description INTERRUPT Min. Max. 7C006-25 7C016-25 Min. Max. 7C006-35 7C016-35 Min. Max. 7C006-55 7C016-55 Min. Max. Unit TIMING tINS INT Set Time 15 25 25 30 ns tINR INT Reset Time 15 25 25 30 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 10 15 20 ns tSWRD SEM Flag Write to Read Time 5 5 5 5 ns tSPS SEM Flag Contention Window 5 5 5 5 ns Switching Waveforms Read Cycle No. 1 (Either Port Address Access)[15, 16] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID C006-10 Read Cycle No. 2 (Either Port CE/OE Access)[15, 17, 18] SEM or CE tHZCE tACE OE tLZOE tHZOE tDOE tLZCE DATA VALID DATA OUT tPU tPD ICC ISB C006-11 Notes: 15. R/W is HIGH for read cycle. 16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads. 17. Address valid prior to or coincident with CE transition LOW. 18. CEL = L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores. 7 CY7C006 CY7C016 Switching Waveforms (continued) Read Timing with Port-to-Port Delay (M/S=L)[19, 20] tWC ADDRESSR MATCH t R/W R PWE t DATA INR t SD HD VALID ADDRESSL MATCH tDDD DATA OUTL VALID tWDD C006-12 Write Cycle No. 1: OE Three-State Data I/Os (Either Port)[21, 22, 23] tWC ADDRESS tSCE SEM OR CE tHA tAW tPWE R/W tSA tSD DATA IN tHD DATA VALID OE t tHZOE DATA OUT LZOE HIGH IMPEDANCE C006-13 Notes: 19. BUSY = HIGH for the writing port. 20. CEL = CER = LOW. 21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE. 23. R/W must be HIGH during all address transitions. 8 CY7C006 CY7C016 Switching Waveforms (continued) Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)[20, 22, 24] tWC ADDRESS tSCE tHA SEM OR CE tAW tSA tPWE R/W tSD tHD DATA VALID DATA IN tLZWE tHZWE HIGH IMPEDANCE DATA OUT C006-14 Semaphore Read After Write Timing, Either Side tAA A0–A 2 VALID ADDRESS VALID ADDRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O 0 DATA IN VALID tSA tPWE DATA OUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE C006-15 Notes: 24. Data I/O pins enter high-impedance when OE is held LOW during write. 25. CE = HIGH for the duration of the above timing (both write and read cycle). 9 CY7C006 CY7C016 Switching Waveforms (continued) Semaphore Contention [26, 27, 28] A0L–A2L MATCH R/WL SEML tSPS A0R–A 2R MATCH R/WR SEMR C006-16 Read with BUSY (M/S=HIGH) tWC ADDRESSR MATCH tPWE R/W R tHD tSD DATA IN R VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD C006-17 Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH C006-18 Notes: 26. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 27. Semaphores are reset (available to both ports) at cycle start. 28. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. 10 CY7C006 CY7C016 Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CELValid First: ADDRESS L,R ADDRESS MATCH CE L tPS CE R tBLC tBHC BUSYR C006-19 CERValid First: ADDRESS L,R ADDRESS MATCH CE R tPS CE L tBLC tBHC BUSYL C006-20 Busy Timing Diagram No. 2 (Address Arbitration) Left AddressValid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESS R tBLA tBHA BUSYR C006-21 Right Address Valid First: tRC or tWC ADDRESS R ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESS L tBLA tBHA BUSYL C006-22 Notes: 29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted. 30. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 31. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 11 CY7C006 CY7C016 Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR: tWC ADDRESSL WRITE 3FFF tHA  CE L R/WL INTR tINS C006-23 Right Side Clears INTR: tRC ADDRESS R READ 3FFF CE R tINR R/WR OE R INTR C006-24 Right Side Sets INTL: tWC ADDRESS R WRITE 3FFF tHA  CE R R/W R INTL tINS  C006-25 Left Side Clears INTL: tRC ADDRESS R READ 3FFF CE L tINR R/W L OEL INT L C006-26 12 CY7C006 CY7C016 Interrupts The interrupt flag (INT) permits communications between ports. When the left port writes to location 3FFF(HEX), the right port’s interrupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port’s interrupt flag (INTL) is accomplished when the right port writes to location 3FFE(HEX). This flag is cleared when the left port reads location 3FFE(HEX). The message at 3FFE(HEX) and 3FFF(HEX) is user-defined. See Table 2 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate. Architecture The CY7C006/016 consists of a an array of 16K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C006/016 can function as a Master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C006/016 has an automatic power-down feature controlled by CE. Each port is provided with its own Output Enable control (OE), which allows data to be read from the device. Busy The CY7C006/016 provides on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other the Busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. BUSYL and BUSYR in master mode are push-pull outputs and do not require pull-up resistors to operate. Master/Slave An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing of slave devices must be delayed until after the BUSY input has settled (tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. When presented a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the OE pin (see Write Cycle No.1 waveform) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Table 1. Non-Contending Read/Write Inputs CE R/W OE SEM H X X H High Z Power-Down H H L L Data Out Read Data in Semaphore X X H X High Z I/O Lines Disabled X L Data In Write to Semaphore H Semaphore Operation The CY7C006/016 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a 1 is written to cancel its request. Outputs I/O 0–7/8 Operation L H L H Data Out Read L L X H Data In Write L X X L Illegal Condition Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7C006/016 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin. Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Right Port R/W CE OE A0L–13L Set Left INT X X X X Reset Left INT X L L 3FFE INT R/W CE OE A0R–13R INT L L L X 3FFE X H X L L X X Set Right INT L L X 3FFF X X X X X L Reset Right INT X X X X X X L L 3FFF H 13 CY7C006 CY7C016 the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access.When writing or reading a semaphore, the other address pins have no effect. When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. When writing to the semaphore, only I/O 0 is used. If a 0 is written to the left port of an unused semaphore, a 1 will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing 0 (the left port in this case). If the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. However, if the right port had requested the semaphore (written a 0) while the left port had control, Initialization of the semaphore is not automatic and must be reset during initialization program at power-up. All Semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Table 3. Semaphore Operation Example Function No action Left port writes semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore I/O 0-7/8 Left 1 0 0 1 1 0 1 1 1 0 1 I/O0-7/8 Right 1 1 1 0 0 1 1 0 1 1 1 Status Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to semaphore No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore Ordering Information 16K x8 Dual-Port SRAM Speed (ns) 15 25 35 55 Ordering Code CY7C006-15AC CY7C006-15JC CY7C006-25AC CY7C006-25JC CY7C006-25AI CY7C006-25JI CY7C006-35AC CY7C006-35JC CY7C006-35AI CY7C006-35JI CY7C006-55AC CY7C006-55JC CY7C006-55AI CY7C006-55JI Package Name A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 A65 J81 Package Type 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 64-Lead Thin Quad Flat Package 68-Lead Plastic Leaded Chip Carrier 14 Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial CY7C006 CY7C016 Ordering Information (continued) 16K x9 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C016-15AC 25 CY7C016-25AC CY7C016-25AI 35 CY7C016-35AC CY7C016-35AI 55 CY7C016-55AC CY7C016-55AI Package Name A80 A80 A80 A80 A80 A80 A80 80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin 80-Lead Thin Package Type Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package Quad Flat Package Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Document #: 38-00416-B Package Diagrams 64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65 51-85046-B 15 CY7C006 CY7C016 Package Diagrams (continued) 80-Pin Thin Plastic Quad Flat Pack A80 51-85065-B 68-Lead Plastic Leaded Chip Carrier J81 51-85005-A © Cypress Semiconductor Corporation, 1999. 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