1 PRELIMINARY CY7C024V/025V/026V CY7C0241V/0251V/036V 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM • Automatic power-down • Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Separate upper-byte and lower-byte control • Pin select for Master or Slave • Commercial and industrial temperature ranges • Available in 100-pin TQFP • Pin-compatible and functionally equivalent to IDT70V24, 70V25, and 7V0261. Features • True dual-ported memory cells which allow simultaneous access of the same memory location • 4/8/16K x 16 organization (CY7C024V/025V/026V) • 4/8K x 18 organization (CY7C0241V/0251V) • 16K x 18 organization (CY7C036V) • 0.35-micron CMOS for optimum speed/power • High-speed access: 15[1]/20/25 ns • Low operating power — Active: ICC = 115 mA (typical) — Standby: ISB3 = 10 µA (typical) • Fully asynchronous operation Logic Block Diagram R/WL UBL R/WR UBR CEL CER LBL LBR OEL OE R [2] I/O 8/9L–I/O 15/17L [3] 8/9 8/9 8/9 I/O Control I/O 0L–I/O 7/8L [4] A0L–A11/1213L [4] 12/13/14 Address Decode 8/9 I/O Control 12/13/14 [3] I/O0L–I/O7/8R Address Decode True Dual-Ported RAM Array [2] I/O8/9L–I/O 15/17R 12/13/14 [4] A0R–A11/12/13R 12/13/14 A0L–A11/12/13L CEL OEL R/WL SEM L [4] A0R–A11/12/13R CER OE R R/WR SEM R Interrupt Semaphore Arbitration [5] [5] BUSYL INTL UBL LBL BUSY R INT R UBR LB R M/S Notes: 1. Call for availability. 2. I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices. 3. I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices. 4. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices. 5. BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 18, 1999 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. Functional Description The CY7C024V/025V/026V and CY7C0241V/0251V/036V are low-power CMOS 4K, 8K, and 16K x16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dualport video/graphics memory. The CY7C024V/025V/026V and CY7C0241V/0251V/036V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). Pin Configurations A7L A6L A9L A8L UBL LBL NC [6] A11L A10L OEL VCC R/WL SEML CEL I/O1L I/O0L I/O4L I/O3L I/O2L GND I/O9L I/O8L I/O7L I/O6L I/O5L 100-Pin TQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C024V (4K x 16) CY7C025V (8K x 16) Notes: 6. A12L on the CY7C025. 7. A12R on the CY7C025. 2 A7R A6R A5R R/WR GND SEMR CER UBR LBR NC [7] A11R A10R A9R A8R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND I/O15R ŒR NC NC NC NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Pin Configurations (continued) A7L A6L A9L A8L OEL VCC R/WL SEML CEL I/O1L I/O0L I/O4L I/O3L I/O2L GND I/O10L I/O9L I/O7L I/O6L I/O5L UBL LBL NC [8] A11L A10L Top View 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC A9L A8L A7L A7R A6R A5R A12L A11L A10L CEL UBL LBL A113L VCC R/WL SEML GND I/O1L I/O0L OEL I/O8L I/O7L I/O6L I/O9L NC [9] A11R A10R A9R A8R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O7R I/O9R NC NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C0241V (4K x 18) CY7C0251V (8K x 18) I/O5L I/O4L I/O3L I/O2L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND I/O16R OER R/WR GND SEMR CER UBR LBR NC NC I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 72 4 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 61 15 60 16 59 17 18 58 19 57 20 56 21 55 22 54 23 53 24 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Notes: 8. A12L on the CY7C0251. 9. A12R on the CY7C0251. 3 A8R A7R A6R A11R A10R A9R UBR LBR A13R A12R GND SEMR CER GND I/O15R OER R/WR I/O11R I/O12R I/O13R I/O14R I/O8R I/O9R I/O10R CY7C026V (16K x 16) I/O7R NC NC NC NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R NC NC NC NC NC NC NC A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R NC NC NC CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Pin Configurations (continued) A7L A6L A9L A8L A11L A10L UBL LBL A12L OEL VCC R/WL SEML CEL I/O1L I/O0L I/O4L I/O3L I/O2L GND I/O10L I/O9L I/O7L I/O6L I/O5L 100-Pin TQFP Top View 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C036V (16K x 18) NC NC NC A13L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A13R NC NC NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O7R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND I/O16R OER R/WR GND SEMR CER UBR LBR A12R A11R A10R A9R A8R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A7R A6R A5R NC NC I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L Selection Guide CY7C024V/025V/026V CY7C024V/025V/026V CY7C0241V/0251V/036V CY7C0241V/0251V/036V -15[1] -20 CY7C024V/025V/026V CY7C0241V/0251V/036V -25 Maximum Access Time (ns) 15 20 25 Typical Operating Current (mA) 125 120 115 Typical Standby Current for ISB1 (mA) (Both ports TTL level) 35 35 30 Typical Standby Current for ISB3 (µA) (Both ports CMOS Level) 10 µA 10 µA 10 µA Shaded areas contain advance information. 4 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A13L A0R–A13R Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K) I/O0L–I/O 17L I/O0R–I/O 17R Data Bus Input/Output SEML SEMR Semaphore Enable UBL UBR Upper Byte Select (I/O8–I/O 15 for x16 devices; I/O9–I/O 17 for x18 devices) LBL LBR Lower Byte Select (I/O0–I/O 7 for x16 devices; I/O0–I/O 8 for x18 devices) INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current .................................................... >200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperature with Power Applied .............................................–55°C to +125°C Range Supply Voltage to Ground Potential ............... –0.5V to +4.6V Commercial DC Voltage Applied to Outputs in High Z State ...........................–0.5V to VCC+0.5V DC Input Voltage[10] .................................–0.5V to VCC+0.5V Industrial Ambient Temperature VCC 0°C to +70°C 3.3V ± 300 mV –40°C to +85°C 3.3V ± 300 mV Shaded areas contain advance information. Note: 10. Pulse width < 20 ns. 5 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Electrical Characteristics Over the Operating Range CY7C024V/025V/026V CY7C0241V/0251V/036V -15[1] Parameter Output HIGH Voltage (VCC=3.3V) VOL Output LOW Voltage Input HIGH Voltage -25 Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Description VOH VIH -20 2.4 2.4 2.4 0.4 VIL Input LOW Voltage IOZ Output Leakage Current IIX Input Leakage Current ICC Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled ISB1 Standby Current (Both Ports TTL Level) CEL & CE R ≥ VIH, f = fMAX Com’l. ISB2 Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f = fMAX Com’l. ISB3 ISB4 2.0 0.8 –10 –10 10 –10 185 35 50 80 120 Standby Current (Both Ports CMOS Com’l. Level) CEL & CER ≥ VCC−0.2V, f = 0 Indust. 10 250 Standby Current (One Port CMOS Com’l. Level) CEL | CER ≥ VIH, f = fMAX[11] Indust. 75 105 Indust. Indust. Indust. 10 –10 10 –10 V V 0.8 10 125 Com’l. 0.4 2.0 –10 V 0.4 2.0 Unit 0.8 V 10 µA 10 µA 120 175 115 165 mA 140 195 135 185 mA 35 45 30 40 mA 45 55 40 50 mA 75 110 65 95 mA 85 120 75 105 mA 10 250 10 250 µA 10 250 10 250 µA 70 95 60 80 mA 80 105 70 90 mA Shaded areas contain advance information. Capacitance[12] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF 10 pF AC Test Loads and Waveforms 3.3V 3.3V R1 = 590Ω C = 30 pF RTH = 250Ω OUTPUT OUTPUT R1 = 590Ω OUTPUT C = 30pF R2 = 435Ω C = 5 pF VTH = 1.4V (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) R2 = 435Ω (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) ALL INPUT PULSES 3.0V GND 10% 90% 10% 90% ≤ 3 ns ≤ 3 ns Notes: 11. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 12. Tested initially and after any design or process changes that may affect these parameters. 6 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Switching Characteristics Over the Operating Range[13] CY7C024V/025V/026V CY7C0241V/0251V/036V -15[1] Parameter Description Min. -20 Max. Min. -25 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 15 20 tAA Address to Data Valid tOHA Output Hold From Address Change tACE[14] CE LOW to Data Valid 15 20 25 ns tDOE OE LOW to Data Valid 10 12 13 ns tLZOE[15, 16, 17] tHZOE[15, 16, 17] tLZCE[15, 16, 17] tHZCE[15, 16, 17] tPU[17] tPD[17] tABE[14] OE Low to Low Z 15 3 20 3 3 OE HIGH to High Z 3 CE HIGH to High Z CE LOW to Power-Up 0 25 12 ns 15 3 12 0 ns ns 3 3 10 ns 3 3 10 CE LOW to Low Z 25 ns ns 15 0 ns ns CE HIGH to Power-Down 15 20 25 ns Byte Enable Access Time 15 20 25 ns WRITE CYCLE tWC Write Cycle Time 15 20 25 ns tSCE[14] CE LOW to Write End 12 15 20 ns tAW Address Valid to Write End 12 15 20 ns tHA Address Hold From Write End 0 0 0 ns tSA[14] Address Set-Up to Write Start 0 0 0 ns tPWE Write Pulse Width 12 15 20 ns tSD Data Set-Up to Write End 10 15 15 ns tHD Data Hold From Write End 0 0 0 ns tHZWE[16, 17] tLZWE[16, 17] tWDD[18] tDDD[18] R/W LOW to High Z 10 R/W HIGH to Low Z 3 12 3 15 0 ns ns Write Pulse to Data Delay 30 45 50 ns Write Data Valid to Read Data Valid 25 30 35 ns Notes: 13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OI/IOH and 30-pF load capacitance. 14. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 16. Test conditions used are Load 3. 17. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 7 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Switching Characteristics Over the Operating Range[13] (continued) CY7C024V/025V/026V CY7C0241V/0251V/036V -15[1] Parameter BUSY TIMING Description Min. -20 Max. Min. -25 Max. Min. Max. Unit [19] tBLA BUSY LOW from Address Match 15 20 20 ns tBHA BUSY HIGH from Address Mismatch 15 20 20 ns tBLC BUSY LOW from CE LOW 15 20 20 ns tBHC BUSY HIGH from CE HIGH 15 17 17 ns tPS Port Set-Up for Priority 5 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 13 15 17 ns tBDD[20] BUSY HIGH to Data Valid INTERRUPT TIMING 15 20 25 ns [19] tINS INT Set Time 15 20 20 ns tINR INT Reset Time 15 20 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 10 12 ns tSWRD SEM Flag Write to Read Time 5 5 5 ns tSPS SEM Flag Contention Window 5 5 5 ns tSAA SEM Address Access Time 15 Data Retention Mode 20 25 ns Timing The CY7C024V/025V/026V and CY7C0241V/0251V/036V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: Data Retention Mode VCC 3.0V 1. Chip Enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 volts). Parameter ICC DR1 Notes: 19. Test conditions used are Load 2. 20. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 21. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested. 8 3.0V VCC to VCC – 0.2V CE 2. CE must be kept between V CC – 0.2V and 70% of VCC during the power-up and power-down transitions. VCC > 2.0V Test Conditions[21] @ VCCDR = 2V tRC V IH Max. Unit 50 µA PRELIMINARY CY7C024V/025V/026V CY7C0241V/0251V/036V Switching Waveforms Read Cycle No.1 (Either Port Address Access)[22, 23, 24] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Read Cycle No.2 (Either Port CE/OE Access)[22, 25, 26] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Read Cycle No. 3 (Either Port)[22, 24, 25, 26] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes: 22. R/W is HIGH for read cycles. 23. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 24. OE = VIL. 25. Address valid prior to or coincident with CE transition LOW. 26. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 9 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Switching Waveforms (continued) Write Cycle No.1: R/W Controlled Timing[27, 28, 29, 30] tWC ADDRESS tHZOE [33] OE tAW CE [31,32] tPWE[30] tSA tHA R/W tHZWE[33] DATA OUT tLZWE NOTE 34 NOTE 34 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing[27, 28, 29, 35] tWC ADDRESS tAW CE [31,32] tSA tSCE tHA R/W tSD tHD DATA IN Notes: 27. R/W must be HIGH during all address transitions. 28. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 29. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 30. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 31. To access RAM, CE = VIL, SEM = VIH. 32. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 34. During this period, the I/O pins are in the output state, and input signals must not be applied. 35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 10 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side[36] tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O 0 DATA IN VALID tSA tPWE DATA OUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[37, 38, 39] A0L –A 2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Notes: 36. CE = HIGH for the duration of the above timing (both write and read cycle). 37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 38. Semaphores are reset (available to both ports) at cycle start. 39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. 11 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)[40] tWC ADDRESSR MATCH tPWE R/WR tHD tSD DATA IN R VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note: 40. CEL = CER = LOW. 12 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Switching Waveforms (continued) Busy Timing Diagram No.1 (CE Arbitration)[41] CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Busy Timing Diagram No.2 (Address Arbitration)[41] Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note: 41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. 13 PRELIMINARY CY7C024V/025V/026V CY7C0241V/0251V/036V Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR : ADDRESSL tWC WRITE 1FFF (OR 1/3FFF) tHA [42] CE L R/W L INT R tINS [43] Right Side Clears INT R: tRC READ 7FFF (OR 1/3FFF) ADDRESSR CE R tINR [43] R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE 1FFE (OR 1/3FFE) tHA[42] CE R R/W R INT L [43] tINS Left Side Clears INT L: tRC READ 7FFE OR 1/3FFE) ADDRESSR CE L tINR[43] R/W L OE L INT L Notes: 42. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 43. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 14 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Architecture The CY7C024V/025V/026V and CY7C0241V/0251V/036V consist of an array of 4K, 8K, and 16K words of 16 and 18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Functional Description Write Operation Semaphore Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. The CY7C024V/025V/026V and CY7C0241V/0251V/036V provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C024V/41V, 1FFF for the CY7C025V/51V, 3FFF for the CY7C026V/36V) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024V/41V, 1FFE for the CY7C025V/51V, 3FFE for the CY7C026V/36V) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Busy The CY7C024V/025V/026V and CY7C0241V/0251V/036V provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted 15 CY7C024V/025V/026V CY7C0241V/0251V/036V PRELIMINARY Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE UB LB SEM H X X X X H High Z I/O 9–I/O17 High Z I/O0–I/O8 Deselected: Power-Down Operation X X X H H H High Z High Z Deselected: Power-Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes X X H X X X High Z High Z Outputs Disabled H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H X X X L Data In Data In Write D IN0 into Semaphore Flag X X H H L Data In Data In Write D IN0 into Semaphore Flag L X X L X L Not Allowed L X X X L L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[44] Left Port Function R/WL CEL OEL Right Port A0L–13L [47] INTL R/WR CER OE R A0R–13R INTR X X X X X L[46] Set Right INTR Flag L L X FFF Reset Right INTR Flag X X X X X X L L FFF (or 1/3FFF) H[45] Set Left INTL Flag X X X X L[45] L L X 1FFE (or 1/3FFE) X Reset Left INTL Flag X L L 1FFE[47] H[46] X X X X X Table 3. Semaphore Operation Example Function No action I/O0–I/O17 Left I/O0–I/O17 Right 1 1 Semaphore free Status Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Notes: 44. See Functional Description for specific highest memory locations by device. 45. If BUSYR=L, then no change. 46. If BUSYL=L, then no change. 47. See Functional Description for specific addresses by device. 16 PRELIMINARY CY7C024V/025V/026V CY7C0241V/0251V/036V Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15[1] CY7C024V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C024V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C024V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C024V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C024V-25AI A100 100-Pin Thin Quad Flat Pack Industrial 25 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15[1] CY7C025V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C025V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C025V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C025V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C025V-25AI A100 100-Pin Thin Quad Flat Pack Industrial 25 16K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15[1] CY7C026V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C026V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C026V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C026V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C026V-25AI A100 100-Pin Thin Quad Flat Pack Industrial 25 4K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15[1] CY7C0241V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C0241V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C0241V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C0241V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C0241V-25AI A100 100-Pin Thin Quad Flat Pack Industrial 25 8K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15[1] CY7C0251V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C0251V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C0251V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C0251V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C0251V-25AI A100 100-Pin Thin Quad Flat Pack Industrial 25 Shaded areas contain advance information. 17 PRELIMINARY CY7C024V/025V/026V CY7C0241V/0251V/036V Ordering Information (continued) 16K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15[1] CY7C036V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C036V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C036V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C036V-25AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C036V-25AI A100 100-Pin Thin Quad Flat Pack Industrial 25 Shaded areas contain advance information. Document #: 38–00678–B Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B 18 PRELIMINARY CY7C036 Dual Port Design Consideration – Data Sheet Addendum This design consideration applies to the Internal Power-OnReset (POR) circuit used on the CY7C036 and its derivatives listed below. Power supply ramp—The devices will function properly and meet all data sheet specifications if the power supply ramp rate is greater than 100 ns. If ramp is less than 100 ns, you may see a non-destructive failure in which the device will not respond to changes in address or clock, but the I/Os will respond to the output enable. Applications consideration—If the power supply ramps in less than 100 ns, a small resistor (20–50Ω), a large capacitor, or an RC network can be connected at the output of the power supply to ground. The addition of a resistor will help clean up the power lines, while the capacitor will slow down the ramp rate without the loss of any power. Contact your local Cypress FAE for assistance as needed. CY7C024V/025V/026V CY7C0241V/0251V/036V Troubleshooting—If a problem occurs with the part, power down the device to ground and then power up again at slower ramp rate (greater than 100 ns) in order to confirm that the problem might be due to the POR circuit. If the dual-port functions properly once the ramp rate is slowed to 100 ns or greater, then the POR circuit is at fault. Applicable devices—All speed/package/temperature combinations of the following: • CY7C024V • CY7C025V • CY7C026V • CY7C0241V • CY7C0251V • CY7C036V Cypress design change—Cypress design team has identified the root cause. A permanent circuit change and die revision will be available beginning in October and will be identified by the letter “A” in the part number. © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.