25/0251 CY7C008V/009V CY7C018V/019V 3.3V 64K/128K x 8/9 Dual-Port Static RAM • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Dual Chip Enables • Pin select for Master or Slave • Commercial and Industrial Temperature Ranges • Available in 100-pin TQFP Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • 0.35-micron CMOS for optimum speed/power • High-speed access: 15/20/25 ns • Low operating power — Active: ICC = 115 mA (typical) — Standby: ISB3 = 10 µA (typical) Logic Block Diagram R/WL R/WR CE0L CE1L CEL CE0R CE1R CER OEL OER  8/9 I/O0R–I/O7/8R I/O Control  A0L–A15/16L   8/9 I/O0L–I/O7/8L 16/17 Address Decode I/O Control Address Decode True Dual-Ported RAM Array 16/17 16/17  A0R–A 15/16R 16/17 A0L–A15/16L CEL OEL R/WL SEM L  A0R–A 15/16R CER OE R R/WR SEM R Interrupt Semaphore Arbitration   BUSYL INTL BUSYR INT R M/S Notes: 1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices. 2. A0–A15 for 64K devices; A0–A16 for 128K. 3. BUSY is an output in master mode and an input in slave mode. For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 21, 2000 CY7C008V/009V CY7C018V/019V Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. Functional Description The CY7C008V/009V and CY7018V/019V are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. The CY7C008V/009V and CY7018V/019V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). Pin Configurations NC NC A6R A5R A4R A3R A1R A2R A0R INTR BUSYR M/S GND INTL BUSYL A0L NC A2L A1L A3L A4L A5L A6L NC NC 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76  NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R A15L 11 65 A15R A16L 12 64 A16R  VCC 13 63 GND NC 14 NC CY7C009V (128K x 8) CY7C008V (64K x 8) 62 NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R SEML 20 56 SEMR R/WL 21 55 R/WR OEL 22 54 OER GND 23 53 GND NC 24 52 GND NC 25 51 NC 2 NC NC NC I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R GND Note: 4. This pin is NC for CY7C008V. I/O0R VCC I/O0L GND I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CY7C008V/009V CY7C018V/019V Pin Configurations (continued) NC A6R A5R A4R A3R A2R A1R A0R BUSYL INTR M/S VCC GND BUSYL GND INTL A0L A1L A3L A2L A4L A5L A6L NC NC 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R A15L 11 65 A15R  A16L 12 64 A16R  VCC 13 63 GND NC 14 NC CY7C019V (128K x 9) CY7C018V (64K x 9) 62 NC 15 61 NC NC 16 60 NC NC 17 59 NC CE0L 18 58 CE0R CE1L 19 57 CE1R SEML 20 56 SEMR R/WL 21 55 R/WR OEL 22 54 OER GND 23 53 GND NC 24 52 GND NC 25 51 NC NC NC I/O8R I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R GND I/O0R VCC I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O8L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide CY7C008V/009V CY7C018V/019V -15 CY7C008V/009V CY7C018V/019V -20 CY7C008V/009V CY7C018V/019V -25 Maximum Access Time (ns) 15 20 25 Typical Operating Current (mA) 125 120 115 Typical Standby Current for ISB1 (mA) (Both ports TTL level) 35 35 30 Typical Standby Current for ISB3 (µA) (Both ports CMOS level) 10 µA 10 µA 10 µA Note: 5. This pin is NC for CY7C018V. 3 CY7C008V/009V CY7C018V/019V Pin Definitions Left Port Right Port Description CE0L, CE1L CER, CE1R Chip Enable (CE is LOW when CE0 ≤ VIL and CE1 ≥ VIH) R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A16L A0R–A16R Address (A0–A15 for 64K devices and A0–A16 for 128K devices) I/O0L–I/O 8L I/O0R–I/O 8R Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O 8 for x9) SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground NC No Connect Maximum Ratings DC Input Voltage ..................................... –0.5V to VCC+0.5V Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >1100V Storage Temperature .................................–65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied .............................................–55°C to +125°C Operating Range Supply Voltage to Ground Potential ............... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State ...........................–0.5V to VCC+0.5V Note: 6. Industrial parts are available in CY7C009V and CY7C019V only. 4 Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 300 mV Industrial –40°C to +85°C 3.3V ± 300 mV CY7C008V/009V CY7C018V/019V Electrical Characteristics Over the Operating Range CY7C008V/009V CY7C018V/019V -15 Symbol Parameter Min. VOH Output HIGH Voltage (VCC=Min., IOH= –4.0 mA) Typ. -20 Max. 2.4 VOL Output LOW Voltage (VCC=Min., IOH= +4.0 mA) VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current IOZ Output Leakage Current ICC Operating Current (VCC=Max. IOUT=0 mA) Outputs Disabled –10 Com’l. -5 10 –10 185 Ind. 50 ISB2 Standby Current (One Port TTL Level) CEL | CER ≥ VIH, f=fMAX Com’l. 80 120 Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC−0.2V, f=0 Com’l. 10 250 Standby Current (One Port CMOS Level) CEL | CER ≥ VIH, f=fMAX Com’l. 75 105  Ind.  Ind. Ind. Max. Unit V 0.4 V 2.2 V 0.8 5 125 Typ. 0.4 0.8 -5 Min. 2.4 2.2 35 Capacitance Max. 0.4 2.2 Standby Current (Both Ports TTL Lev- Com’l. el) CEL & CER ≥ VIH, f=fMAX Ind. ISB4 -25 Typ. 2.4 ISB1 ISB3 Min. 5 -5 10 –10 120 175 140 195 35 45 45 55 75 110 85 120 10 250 10 250 70 95 80 105 0.8 V 5 µA 10 µA 115 165 mA 30 40 65 95 10 250 µA 60 80 mA mA mA mA mA mA µA mA  Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF 10 pF AC Test Loads and Waveforms 3.3V 3.3V R1 = 590Ω C = 30 pF RTH = 250Ω OUTPUT OUTPUT R1 = 590Ω OUTPUT C = 30pF R2 = 435Ω C = 5 pF VTH = 1.4V (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V GND 10% R2 = 435Ω (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) 90% 10% 90% ≤ 3 ns ≤ 3 ns Notes: 7. fMAX=1/t RC=All inputs cycling at f=1/tRC (except output enable). f=0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 8. Tested initially and after any design or process changes that may affect these parameters. 5 CY7C008V/009V CY7C018V/019V Switching Characteristics Over the Operating Range CY7C008V/009V CY7C018V/019V -15 Parameter Description Min. -20 Max. Min. -25 Max. Min. Max. Unit 25 ns 25 ns 13 ns READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold From Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE[11, 12, 13] OE LOW to Low Z tHZOE[11, 12, 13] tLZCE[11, 12, 13] tHZCE[11, 12, 13] tPU tPD tABE OE HIGH to High Z 15 20 15 3 3 15 12 3 10 3 CE HIGH to High Z 0 ns 3 12 3 10 CE LOW to Power-Up ns 3 20 10 3 CE LOW to Low Z 25 20 ns 15 3 12 0 ns ns 15 0 ns ns CE HIGH to Power-Down 15 20 25 ns Byte Enable Access Time 15 20 25 ns WRITE CYCLE tWC Write Cycle Time 15 20 25 ns tSCE CE LOW to Write End 12 16 20 ns tAW Address Valid to Write End 12 16 20 ns tHA Address Hold From Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE Write Pulse Width 12 17 22 ns tSD Data Set-Up to Write End 10 12 15 ns tHD Data Hold From Write End 0 tHZWE[12, 13] R/W LOW to High Z tLZWE[12, 13] R/W HIGH to Low Z tWDD Write Pulse to Data Delay 30 tDDD Write Data Valid to Read Data Valid 25 0 10 3 0 12 ns 15 ns 40 50 ns 30 35 ns 3 3 ns BUSY TIMING tBLA BUSY LOW from Address Match 15 20 20 ns tBHA BUSY HIGH from Address Mismatch 15 20 20 ns tBLC BUSY LOW from CE LOW 15 20 20 ns tBHC BUSY HIGH from CE HIGH 15 16 17 ns tPS Port Set-Up for Priority 5 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 13 tBDD BUSY HIGH to Data Valid 15 15 17 20 ns 25 ns Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OI/IOH and 30-pF load capacitance. 10. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 11. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 12. Test conditions used are Load 2. 13. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 14. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 15. Test conditions used are Load 1. 16. t BDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). 6 CY7C008V/009V CY7C018V/019V Switching Characteristics Over the Operating Range (continued) CY7C008V/009V CY7C018V/019V -15 Parameter Description INTERRUPT TIMING Min. -20 Max. Min. -25 Max. Min. Max. Unit  tINS INT Set Time 15 20 20 ns tINR INT Reset Time 15 20 20 ns SEMAPHORE TIMING tSOP SEM Flag Update Pulse (OE or SEM) 10 10 12 ns tSWRD SEM Flag Write to Read Time 5 5 5 ns tSPS SEM Flag Contention Window 5 tSAA SEM Address Access Time 5 5 15 Data Retention Mode ns 20 25 ns Timing The CY7C008V/009V and CY7018V/019V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: Data Retention Mode VCC 3.0V 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2V. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (3.0 volts). Parameter ICC DR1 Note: 17. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested. 7 3.0V VCC to VCC – 0.2V CE 2. CE must be kept between VCC – 0.2V and 70% of VCC during the power-up and power-down transitions. VCC > 2.0V Test Conditions @ VCCDR = 2V tRC V IH Max. Unit 50 µA CY7C008V/009V CY7C018V/019V Switching Waveforms Read Cycle No.1 (Either Port Address Access)[18, 19, 20] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Read Cycle No.2 (Either Port CE/OE Access)[18, 21, 22] tACE CE tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Read Cycle No. 3 (Either Port)[18, 20, 21, 22] tRC ADDRESS tAA tOHA tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes: 18. R/W is HIGH for read cycles. 19. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads. 20. OE = VIL. 21. Address valid prior to or coincident with CE transition LOW. 22. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 8 CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing[23, 24, 25, 26] tWC ADDRESS tHZOE  OE tAW CE  tPWE tSA tHA R/W tHZWE DATA OUT tLZWE NOTE 29 NOTE 29 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing[23, 24, 25, 30] tWC ADDRESS tAW CE  tSA tSCE tHA R/W tSD tHD DATA IN Notes: 23. R/W must be HIGH during all address transitions. 24. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM. 25. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 26. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 27. To access RAM, CE = VIL, SEM = VIH. 28. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 29. During this period, the I/O pins are in the output state, and input signals must not be applied. 30. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 9 CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side tSAA A 0–A 2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O 0 DATA IN VALID tSA tPWE DATA OUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[32, 33, 34] A0L –A 2L MATCH R/WL SEM L tSPS A 0R –A 2R MATCH R/WR SEM R Note: 31. CE = HIGH for the duration of the above timing (both write and read cycle). 32. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 33. Semaphores are reset (available to both ports) at cycle start. 34. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. 10 CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) tWC ADDRESSR MATCH tPWE R/WR tHD tSD DATA IN R VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATA OUTL VALID tWDD Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note: 35. CEL = CER = LOW. 11 CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CELValid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESS L,R ADDRESS MATCH CER tPS CE L tBLC tBHC BUSY L Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSY R Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSY L Note: 36. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. 12 CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR : ADDRESSL tWC WRITE FFFF (1FFFF for CY7C009V/19V) tHA  CE L R/W L INT R tINS  Right Side Clears INT R : tRC READ FFFF (1FFFF for CY7C009V/19V) ADDRESSR CE R tINR  R/WR OE R INTR Right Side Sets INT L: tWC ADDRESSR WRITE FFFE (1FFFF for CY7C009V/19V) tHA CE R R/W R INT L  tINS Left Side Clears INT L: tRC READ 1FFE (1FFFF for CY7C009V/19V) ADDRESSR CE L tINR R/W L OE L INT L Notes: 37. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 38. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 13 CY7C008V/009V CY7C018V/019V (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Architecture The CY7C008V/009V and CY7018V/019V consist of an array of 64K and 128K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Functional Description Write Operation Semaphore Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. The CY7C008V/009V and CY7018V/019V provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. The upper two memory locations may be used for message passing. The highest memory location (FFFF for the CY7C008/18, 1FFFF for the CY7C009/19) is the mailbox for the right port and the second-highest memory location (FFFE for the CY7C008/18, 1FFFE for the CY7C009/19) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C008V/009V and CY7018V/019V provide on-chip arbitration to resolve simultaneous memory location access 14 CY7C008V/009V CY7C018V/019V Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE SEM H X X H High Z Deselected: Power-Down H H L L Data Out Read Data in Semaphore Flag X X H X High Z I/O Lines Disabled X L Data In Write into Semaphore Flag H I/O0–I/O8 Operation L H L H Data Out Read L L X H Data In Write L X X L Not Allowed Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH) Left Port Function Right Port R/WL CEL OEL A0L–16L INTL R/WR CER OER A0R–16R INTR Set Right INTR Flag L L X FFFF (or 1FFFF) X X X X X L Reset Right INTR Flag X X X X X X L L FFFF (or 1FFFF) H Set Left INTL Flag X X X X L L L X FFFE (or 1FFFE) X Reset Left INTL Flag X L L FFFE (or 1FFFE) H  X X X X X Table 3. Semaphore Operation Example I/O0–I/O8 Left I/O0–I/O8Right No action Function 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Notes: 39. A0L–16L and A0R–16R, 1FFFF/1FFFE for the CY7C009V/19V. 40. If BUSYR=L, then no change. 41. If BUSYL=L, then no change. 15 Status CY7C008V/009V CY7C018V/019V Ordering Information 64K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C008V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C008V-20AC A100 100-Pin Thin Quad Flat Pack Commercial 25 CY7C008V-25AC A100 100-Pin Thin Quad Flat Pack Commercial 64K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C018V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C018V-20AC A100 100-Pin Thin Quad Flat Pack Commercial 25 CY7C018V-25AC A100 100-Pin Thin Quad Flat Pack Commercial 128K x8 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C009V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C009V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C009V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C009V-25AC A100 100-Pin Thin Quad Flat Pack Commercial 25 128K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range 15 CY7C019V-15AC A100 100-Pin Thin Quad Flat Pack Commercial 20 CY7C019V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C019V-20AI A100 100-Pin Thin Quad Flat Pack Industrial CY7C019V-25AC A100 100-Pin Thin Quad Flat Pack Commercial 25 Document #: 38–00669–*D 16 CY7C008V/009V CY7C018V/019V Package Diagram © Cypress Semiconductor Corporation, 2000. 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