Rev.1.2 S-3530A REAL-TIME CLOCK 2 S-3530A is a CMOS real-time clock IC supporting an I C-BUS, which is designed to transfer or set each data of a clock and calender as requested by a CPU. It provides connection with a CPU via two wires and has two systems of an interrupt/alarm features, allowing the alleviation of software treatment on the side of a host. It also works on lower power with the oscillating circuit operated at a constant voltage. The shipping form is either a die or an 8-pin SSOP ultra compact package. ! Features ! Applications • Low power consumption : 0.7 µA typ. (VDD=3.0 V) • Wide area of operating voltage : 1.7 to 5.5 V • BCD input/output of year, month, day, day of a week, hour, minute and second 2 • CPU interface via two wires (I C- BUS) • Auto calender till the year of 2,099 (automatic leap year arithmetic feature included) • Built-in power voltage detecting circuit • Built-in constant voltage circuit • Built-in flag generating circuit on power on/off • Built-in alarm interrupter (two systems) • Steady-state interrupt frequency/duty setting feature • Built-in 32 kHz crystal oscillating circuit (Internal Cd, External Cg) • Die or 8-pin SSOP package (pin pitch: 0.65 mm) 2 (*) I C-BUS is a trademark of PHILLIPS ELECTRONICS N.V. • • • • • Cellular phone PHS A variety of pagers TV set and VCR Games ! Block Diagram XIN XOUT Oscillating circuit Timing generatio n INT1 Register Clock generating circuit Comparator 1 Status register VDD Power voltage detecting circuit Constant voltage circuit Second Minute Hour INT1 Day of week Day Month Comparator 2 INT2 Register INT2 Clock generating circuit 2 VSS Shift register Year I C-BUS SDA Interface SCL Figure 1 Block diagram Seiko Instruments Inc. 1 REAL-TIME CLOCK S-3530A n Pin Assignment (1) Package : S-3530AEFS 8-pin SSOP Top view INT1 XIN 1 2 8 7 XOUT VSS 3 4 6 5 VDD SDA SCL INT2 Figure 2 Pin assignment (2) Die : S-3530AECA Y INT1 VDD XIN SDA 0 X XOUT SCL S-3530A INT2 VSS 2.10 × 1.60 mm Sizes shown are for design purposes only. The corners of the die shrink by approximately 30 µm after dicing. (*2) Pad size : 100 × 100 µm (*1) Die size : Pad Coordinates Symbol XYCoordinate Coordinate Symbol INT1 −890 641 VDD 890 641 XIN −890 351 SDA 890 356 XOUT −890 −114 SCL 890 −240 VSS −890 −641 INT2 890 −641 Figure 2-2 Pad assignment 2 XYCoordinate Coordinate Seiko Instruments Inc. REAL-TIME CLOCK S-3530A n Description of Pins Table 1 Description of pins Pin No. Symbol Description Configuration 1 INT1 N-channel open drain Alarm interrupt 1 output pin. Depending on the mode set by the INT1 output (No protective diode register and status register, it outputs low or on the side of VDD) Clock when time is reached. It is disabled by rewriting the status register. 2 XIN Crystal oscillator connect pin (32,768 Hz) 3 XOUT 4 VSS Negative power supply pin (GND) 5 INT2 N-channel open drain Alarm interrupt 2 output pin. Depending on the mode set by the INT2 output (No protective diode register and status register, it outputs low or on the side of VDD) Clock when time is reached. It is disabled by rewriting the status register. 6 SCL 7 SDA CMOS input (No protective Serial clock input pin. Follow the specification with great care to the diode on the side of VDD) rising/falling time of the SCL signal because the signal is treated at its rising/falling edge. N-channel open drain Serial data input/output pin. output (No protective diode This pin is usually pulled up to VDD via a on the side of VDD) resistor, and connected to other open-drain or CMOS input open-collector output devices in wired OR configuration. 8 VDD Positive power supply pin. (Internal Cd, External Cg) Seiko Instruments Inc. 3 REAL-TIME CLOCK S-3530A n Description of Operation 1. Serial interface S-3530A receives various commands through the I2C-BUS-based serial interface to read/write data. The method of I2C-BUS-based transfer is described here. 1-1. Start condition Changing the SDA line from “H” to “L” when the SCL line is “H” activates the start condition. All the operations begin at the start condition. 1-2. Stop condition Changing the SDA line from “L” to “H” when the SCL line is “H” activates the stop condition. During a read sequence, any read operation is stopped and a device enters its stand-by mode when a stop condition is received. tSU.STA tHD.STA tSU.STO SCL SDA Start condition Stop condition Figure 3 Start/Stop condition 1-3. Data transfer When the SDA line is changed while the SCL line is on “L”, data transfer is performed. When the SDA line is changed while the SCL line is on “H”, a start or stop condition is recognized. tSU.DAT tHD.DAT SCL SDA Figure 4 Data transfer timing 4 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A 1-4. Acknowledge Data transfer is performed in eight-bit sequence. A device on the system bus, which succeedingly receives data during a period of a ninth clock cycle, puts the SDA line on “L” and returns an acknowledge signal meaning that the data has been received. SCL (S-3530A input) 1 8 9 SDA (Master output) Acknowledge output SDA (S-3530A output) Start condition tPD tDH Figure 5 Acknowledge output timing 1-5. Device addressing The master device on the system generates a start condition to its slave device to make communication. It continuously issues the device address of a four-bit length, the command of a three-bit length and the read/write command of a one-bit length over the SDA bus. The upper four bits, called a device code, represent a device address and are fixed at “0110.” Device code 0 1 1 Command 0 C2 C1 Read/Write bit C0 MSB R/W LSB Figure 6 Communication data Seiko Instruments Inc. 5 REAL-TIME CLOCK S-3530A 1-6. Data reading After a start condition is detected from the outside, the device code and command are received. At this point, the real-time reading mode or status register reading mode is entered when the read/write bit is "1". In either the real-time reading mode or status register reading mode, data are output in the order from LSB. (1) Real-time data reading 1 S T A R T SDA LINE NO ACK from Master Device R E DEVICE Command A D ADDRESS 0 1 1 0 0 1 0 M S B A C K S T O P A C K 1 L R A S / C B W K L S B Real-time data access 1 command L S B M S B Year data M S B Second data (2) Real-time data reading 2 S T A R T SDA LINE NO ACK from Master Device R E DEVICE Command A D ADDRESS 0 1 1 0 0 1 1 M S B A C K S T O P A C K 1 L R A S / C B W K L S B Real-time data access 2 command L S B M S B Hour data M S B Second data (3) Status register reading S T A R T SDA LINE NO ACK from Master Device R E DEVICE Command A D ADDRESS 0 M S B 1 1 0 0 0 1 ®NOTE¯ 1 L R A S / C B W K Status register access command S T O P L S B M S B Status data Figure 7 Read communication 6 Seiko Instruments Inc. ACK Upside: Generate from the master device ACK Downside: Generate from the S-3530A REAL-TIME CLOCK S-3530A 1-7. Data writing After a start condition is detected from the outside, the device code and command are received. At this point, the real-time data writing mode or other register writing mode is entered when the read/write bit is "0". Data must be entered in the order from LSB of the real-time data writing mode or status register writing mode. In real-time data writing, the counter of a calender and time is reset when the ACK signal rises following the real-time writing command, and any update operation is disabled. After a minute data is received, the end of a month is corrected while a second data is imported. Then, the count-up is started when the ACK signal rises after the second data is received. (1) Real-time data writing 1 S T A R T SDA LINE W R I DEVICE Command T E ADDRESS 0 1 1 0 0 1 0 M S B S T O P 0 L R A S / C B W K L S B Real-time data access 1 command M S B L S B A C K Year data M S B A C K Second data (2) Real-time data writing 2 S T A R T SDA LINE W R I DEVICE Command T E ADDRESS 0 1 1 0 0 1 1 M S B S T O P 0 L R A S / C B W K L S B Real-time data access 2 command M S B L S B A C K Hour data M S B A C K Second data (3) Status register writing S T A R T SDA LINE W R I DEVICE Command T E ADDRESS 0 M S B 1 1 0 0 0 1 0 L R A S / C B W K Status register access command S T O P L S B M S B A C K Status data Figure 8 Write communication Seiko Instruments Inc. 7 REAL-TIME CLOCK S-3530A 2. Command configuration There are eight commands by which the read/write operation of various registers is performed. The table below lists them. Table 2 Command list C2 C1 C0 Description Number of ACK 0 0 0 Reset (00 (year), 01 (month), 01 (day), 0 (day of week), 00 (minute), 00 (second)) (*1) 1 0 0 1 Status register access 2 0 1 0 Real-time data access 1 (year data to) 8 0 1 1 Real-time data access 2 (hour data to) 4 1 0 0 Alarm time/frequency duty setting 1 (for INT1 pin) 3 1 0 1 Alarm time/frequency duty setting 2 (for INT2 pin) 3 1 1 0 Test mode start (*2) 1 1 1 1 Test mode end (*2) 1 (*1) Don’t care the R/W bit of this command. (*2) This command is access-disabled due to specific use for the IC test. 8 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A 2-1. Real-time data register The real-time data register is a fifty-six-bit register which stores the BCD code of the data of year, month, day, day of week, hour, minute and second. Any read/write operation performed by the real-time data access command sends or receives the data from LSB on the first digit of the year data. Y80 Y40 Y20 Y10 Y8 Y4 Y2 MSB Y1 LSB Year data (00 to 99) Sets the lower two digits of the Christian era (00 to 99) and links together with the auto calender feature till 2,099. Month data (01 to 12) 0 0 0 M10 M8 M4 M2 MSB 0 M1 LSB 0 D20 D10 D8 D4 D2 The count value is automatically changed by the auto calender feature: 1, 3, 5, 7, 8, 10, 12: 1 to 31 4, 6, 9, 11: 1 to 30 2 (leap year): 1 to 29 2 (common year): 1 to 28 D1 Day data (01 to 31) MSB 0 LSB 0 0 0 0 W4 W2 MSB W1 Day of week data (00 to 06) A septenary counter. Set it so that it corresponds to the day of the week. LSB Hour data (00 to 23 or 00 to 11) AM/ PM 0 H20 H10 H8 H4 H2 MSB 0 LSB m40 m20 m10 m8 m4 m2 MSB TE ST MSB H1 m1 AM/PM : For 12-hour expression, 0:AM and 1:PM. For 24-hour expression, this flag has no meaning but either 0 or 1 must be written. Minute data (00 to 59) LSB Second data (00 to 59) and test flag S40 S20 S10 S8 S4 S2 S1 TEST : Turns to “1” during the test mode. LSB Figure 9 Real-time data register Seiko Instruments Inc. 9 REAL-TIME CLOCK S-3530A 2-2. Status register The status register is an eight-bit register which allows you to display and set various modes. The POWER flag is read-only and others are read/write-enabled. B6 B7 MSB POWER B5 12/24 R R/W B4 B3 B2 B1 B0 INT2ME INT1FE INT2FE R/W R/W R/W INT1AE INT2AE INT1ME R/W R/W R/W LSB Figure 10 Status register B7:POWER This flag turns to "1" if the power voltage detecting circuit operates during power-on or changes in power voltage (below VDET). Once turning to "1", this flag does not turns back to "0" even when the power voltage reaches or exceeds the detection voltage. When the flag is "1", you must send the reset command (or status register command) and turn it to "0." It is a readonly flag. B6:12/24 This flag is used to set 12-hour or 24-hour expression. 0 : 12-hour expression 1 : 24-hour expression B5:INT1AE, B4:INT2AE This flag is used to choose the state of INT1 pin (or INT2 pin) output with alarm interrupt output set. Enable this flag after setting alarm time that forms a meeting condition in the INT1 register (or INT2 register): 0 : Alarm interrupt output is disabled. 1 : Alarm interrupt output is enabled. B3:INT1ME, B2:INT2ME This flag is used to make the output of the INT1 pin (or INT2 pin) per-minute edge interrupt or per-minute steady interrupt. To make the output perminute steady interrupt, set "1" at INT1ME and INT1FE (or INT2ME and INT2FE). 0 : Alarm interrupt or selected frequency steady interrupt output 1 : Per-minute edge interrupt or per-minute steady interrupt output B1:INT1FE, B0:INT2FE This flag is used to make the output of the INT1 pin (or INT2 pin) per-minute steady interrupt output (a period of one minute, 50% of duty) or selected frequency steady interrupt. Note that the INT1 register (INT2 register) is considered as the data of frequency/duty if selected frequency steady interrupt is chosen. 0 : Alarm interrupt or per-minute edge interrupt output 1 : Per-minute steady interrupt or selected frequency steady interrupt output 10 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A 2-3. Alarm time/Frequency duty setting register There are two types of alarm time/frequency duty setting registers, sixteen-bit registers, which set alarm time or frequency duty. They are switched by INTxAE or INTxFE register. AM/PM flag to be set must be in accordance with 12-hour or 24-hour expression. If AM/PM flag is not rightly then set hour data is not met to alarm data. The alarm time/frequency duty setting register is a writeonly register. (1) When INTxAE = 1 INT1 register AM/ PM INT2 register 0 H20 H10 H8 H4 H2 MSB 0 m40 m20 m10 m8 m4 m2 H1 AM/ PM LSB MSB m1 MSB 0 0 LSB H20 H10 H8 H4 H2 H1 LSB m40 m20 m10 m8 m4 m2 m1 MSB LSB Figure 11 INT1 and INT2 registers (alarm) INT1 and INT2 registers are considered as alarm time data. Having the same configuration as the time and minutes registers of real-time data register configuration, they represent hours and minutes with BCD codes. When setting them, do not set any none-existent day. Data to be set must be in accordance with 12-hour or 24-hour expression that is set at the status register. (2) When INTxFE = 1 INT1 and INT2 registers are considered as frequency duty data. By turning each bit of the registers to "1", a frequency corresponding to each bit is chosen in an ANDed form. INT1 register f7 INT2 register f6 f5 f4 f3 f2 f1 MSB f15 f14 f13 f12 f11 f10 f9 MSB f0 f7 LSB MSB f8 f15 LSB MSB f8 f6 f5 f4 f3 f2 f1 f0 LSB f14 f13 f12 f11 f10 f9 f8 LSB f0 32768 Hz f4 2048 Hz 128 Hz f12 8 Hz f1 16384 Hz f5 1024 Hz f9 64 Hz f13 4 Hz f2 8192 Hz f6 512 Hz f10 32 Hz f14 2 Hz f3 4096 Hz f7 256 Hz f11 16 Hz f15 1 Hz Figure 12 INT1 and INT2 registers (frequency duty) Seiko Instruments Inc. 11 REAL-TIME CLOCK S-3530A Example If f15 to f0 = 000A H 32 kHz 16 kHz 8 kHz 4 kHz 2 kHz INT1 or INT2 pin output Set to selected frequency steady interrupt output Figure 13 Clock output 2-4. Test flag The test flag is a one-bit register which is assigned to MSB of the second data of the real-time data register. If transferred data is considered as the test mode starting command due to the receiving of the test mode starting command or noises, "1" is set. When "1" is set, you must send the test mode ending command or reset command. 3. Initialization Note that S-3530A has different initializing operations, depending on states. 3-1. When power is turned on When power is turned on, the status register is set to "82h" and the INT1 register to "8000h" by the power-on detecting circuit. In other words, "1" is sets at the bit 7 (POWER flag) of the status register and the clock of 1 Hz is output from the INT1 pin. This is provided to adjust oscillating frequencies. In normal use, the reset command must be sent when power is turned on. Real-time data register : 00 (year), 01 (month), 01 (day), 0 (day of week), 00 (hour), 00 (minute), 00 (second) Status register : "82h" INT1 register : "8000h" INT2 register : "0000h" 3-2. When the power voltage detecting circuits operates The power voltage detecting circuit included in S-3530A operates and sets "1" at the bit 7 (POWER flag) of the internal status register when power is turned on or power voltage is reduced. Once "1" is set, it is held even after the power voltage gets equal to or higher than the detection voltage, i.e., the power voltage detector threshold. When the flag has "1," you must send the reset command from CPU and initialize the flag. At this point, other registers does not change. However, if the POWER flag has "0" during the power-on reset of CPU (S-3530A does not reach any indefinite area during backup), you do not have to send the reset command. 12 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A 3-3. When the reset command is received When the reset command is received, each register turns as follows: Real-time data register : 00 (year), 01 (month), 01 (day), 0 (day of week), 00 (hour), 00 (minute), 00 (second) Status register : "00h" INT1 register : "0000h" INT2 register : "0000h" VDD POWER flag A C K DEVICE command ADDRESS 0 1 1 0 0 0 1 1 SDA LINE S M T S A B R T 0 1 0 0 0 0 0 VDD 0 1 1 L R A S / C B W K POWER flag status access command DEVICE command ADDRESS S T O P 1 1 0 0 0 0 S M T S B A R T 1 L R A S S / C T B W K O P Don't care status data reset command backup state (S-3530A does not reach any indefinite area) POWER flag A C K DEVICE command ADDRESS 0 SDA LINE CPU down S T A R T M S B 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 L R A S / C B W K POWER flag status access command status data DEVICE command ADDRESS 0 1 S T O P S M T S A B R T 1 1 0 0 1 0 1 L R A L S / C S B W K B real-time data access command Figure 14 Initializing Seiko Instruments Inc. 13 REAL-TIME CLOCK S-3530A 4. Processing of none-existent data and end-of-month When writing real-time data, validate it and treat any invalid data and end-of-month correction. [None-existent data processing] Table 3 None-existent data processing Register Normal data Error data Result Year data 00 to 99 XA to XF, AX to FX 00 Month data 01 to 12 00, 13 to 19, XA to XF 01 Day data 01 to 31 00, 32 to 39, XA to XF 01 Day of week data 0 to 6 7 0 Hour data (24-hour) 0 to 23 24 to 29, 3X, XA to XF 00 (*) (12-hour) 0 to 11 12 to 19, XA to XF 00 Minute data 00 to 59 60 to 79, XA to XF 00 Second data (**) 00 to 59 60 to 79, XA to XF 00 (*) For 12-hour expression, write the AM/PM flag. The AM/PM flag is ignored in 24-hour expression, but "0" for 0 to 11 o'clock and "1" for 12 to 23 o'clock are read in a read operation. (**) None-existent data processing for second data is performed by a carry pulse one second after the end of writing. At this point, the carry pulse is sent to the minute counter. [End-of-month correction] Any none-existent day is corrected to the first day of the next month. For example, February 30 is changed to March 1. Leap-year correction is also performed here. 5. Interrupt There are different five output formats from the INT1 and INT2 pins, which are chosen by the INTxAE, INTxME and INTxFE bits of the status register (x:1 or 2). (1) Alarm interrupt output Alarm interrupt is enabled by setting hour and minute data to the INT1 register (or INT2 register) and turning the status register's INT1AE to "1" and INT1ME and INT1FE to "0" (or INT2AE to "1" and INT2ME and INT2FE to "0"). When set hour data is met, low is output from the INT1 pin (or INT2 pin). Since the output is held, rewrite INT1AE (or INT2AE) of the status register to "0" through serial communication to turn the output to high (OFF state). The coincidence signal retains for one minute. Pay attention that the “Low” signal is output from the INTx pin once again when DISABLE or ENABLE communication is executed during this oneminute period. (2) Selected frequency steady interrupt output When you set frequency/duty data to the INT1 register (or INT2 register) and turn the status register's INT1ME to "0" and INT1FE to "1" (or INT2ME to "0" and INT2FE to "1"), clock set at the INTx register is output from the INT1 pin (or INT2 pin). (3) Per-minute edge interrupt output When a first minute carry is performed after the status register's INT1ME is set with "1" and INT1FE with "0" (or INT2ME with "1" and INT2FE with "0"), low is output from the INT1 pin (or INT2 pin). Since the output is held, rewrite INT1AE, INT1ME and INT1FE (or INT2AE, INT1ME and INT2FE) of the status register to "0" through serial communication to turn the output to high (OFF state). When you perform DISABLE or ENABLE communication while the minute carry processing signal is being retained (for 10 msec), "Low" signal is output from the INTx pin again. (4) Per-minute steady interrupt output When a first minute carry is performed after the status register's INT1ME and INT1FE are set with "1" (or INT2ME and INT2FE with "1"), clock is output from the INT1 pin (or INT2 pin) with a period of one minute (50% duty). When you perform DISABLE or ENABLE communication while the INTx pin is at "L," "Low" signal is output from the INTx pin again. 14 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A Note 1 : If changing an output mode, give care to the state of the INT1 and INT2 registers and output. Note 2 : If per-minute edge interrupt output or per-minute steady interrupt output is chosen, the INT1 and INT2 registers have no meaning. Table 4 Interrupt description NO. INT1AE INT1ME INT1FE 0 1 0 * 0 0 0 1 2 3 4 * * 1 1 1 0 0 1 0 NO. INT2AE INT2ME INT2FE 5 6 0 * 0 0 0 1 Description INT1 pin output disabled (No interrupt output) Selected frequency steady interrupt output from the INT1 pin Per-minute edge interrupt output from the INT1 pin Per-minute steady interrupt output from INT1 pin Alarm interrupt output from INT1 pin Description INT2 pin output disabled (No interrupt output) Selected frequency steady interrupt output from the INT2 pin 7 * 1 0 Per-minute edge interrupt output from the INT2 pin 8 * 1 1 Per-minute steady interrupt output from INT2 pin 9 1 0 0 Alarm interrupt output from INT2 pin Note * : Don't care (both 0 and 1 are available) (1) Alarm interrupt output Change by program INTxAE Alarm time corresponds Alarm time corresponds INTxME=INTxFE=0 INTx pin OFF "Low" signal is output again in case of 1 minute or less (2) Selected frequency steady interrupt output Change by program INTxFE Free run output starts INTxAE=INTxME=0 INTx pin OFF (3) Per-minute edge interrupt output Change by program INTxME INTxAE=INTxFE=0 Minute-carry processing Minute-carry processing INTx pin OFF "Low" signal is output again in case of 10 msec or less Seiko Instruments Inc. 15 REAL-TIME CLOCK S-3530A (4) Per-minute steady interrupt output Change by program (OFF) INTxFE,INTxME Minute-carry processing Minute-carry processing Minute-carry processing Minute-carry processing Minute-carry processing INTxAE=0 INTx pin 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds “Low” signal is output again in case of 10 msec or less. “High” signal is output in case of 10 msec or more. “Low” signal is output by the next minute-carry processing. (5) During power-on detecting circuit operation Change by the reset command INTxFE INTxAE=INTxME=0 INT1 pin OFF INT2 pin is in OFF state 0.5 second 0.5 second Figure 15 Output mode 16 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A 6. Power voltage detecting circuit S-3530 has an internal power voltage detecting circuit. This circuit gives sampling movement for only 15.6msec. once a second. If the power voltage decreases below the detection voltage (VDET), the BLD latch circuit latches “H” level and sampling movement stops. Only when subsequent communication is of the status read command, the output of the latch circuit is transferred to the sift register and the sampling movement is resumed. Decrease in power voltage can be monitored by reading the POWER flag. That is to say, once decrease in power voltage is detected, any detecting operation is not performed and "H" is held unless you perform initialization or send the status read command. [Note] When power voltage is increased and the first read operation is performed after decrease in power voltage occurs and the latch circuit latches "H", "1" can be read on the POWER flag. However, if the next read operation is performed after the sampling of the detecting circuit, the POWER flag is reset since sampling is subsequently allowed. See the timing diagram below. VDD VDET Communication 1sec 1sec Stop Sampling pulse Stop Stop Latch circuit output POWER flag (0) (1) (1) (1) (1) (1) (1) (0) VDD VDET Communication 1sec 1sec Stop Stop Stop Stop Sampling pulse Latch circuit output POWER flag (1) (1) (0) (0) [Timing of sampling pulse] 1 Hz 0.5sec 0.5sec Carry pulse Sampling pulse 7.8msec Latch timing Carry-up timing 15.6msec Figure 16 Timing of the power voltage detecting circuit Seiko Instruments Inc. 17 REAL-TIME CLOCK S-3530A 7. Example of software treatment (1) Initialization flow at power-on START (*1) If S-3530 is back-up and power is turned on only on the CPU side, the reset command does not need transferring. (*2) If conditions are no good (e.g., noise) and probable changes in commands occurs via serial communications, it is recommended to make sure the TEST flag. (*3) The test ending command may be used alternately Power on NO POWER=1 YES Reset command transfer NO TEST=1 (*1) (*2) YES Reset command transfer (*3) Status register setting command transfer Real-time data setting command transfer INTx register setting command transfer END Figure 17 Initialization flow 18 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A n Samples of Applied Circuits Vcc S-3530AEFS System power Vcc INT1 VDD INT2 External CPU Vss SDA SCL XIN XOUT Vss Cg Due to the I/O pin with no protective diode on the VDD side, the relation of VCC≥VDD has no problem. But give great care to the standard. Make communications after the system power is turned on and a stable state is obtained. Figure 18 Applied circuit 1 Power switching circuit System power S-3530AEFS Vcc INT1 VDD INT2 External CPU SDA Vss SCL XIN Vss XOUT Cg Make communications after the system power is turned on and a stable state is obtained. Figure 19 Applied circuit 2 Seiko Instruments Inc. 19 REAL-TIME CLOCK S-3530A n Order Specification S-3530AE FS Shipping form: FS: Package (8-pin SSOP) CA: Die Description (fixed) n Adjustment of Oscillating Frequency 1. Configuration of the oscillating circuit Since crystal oscillation is sensitive to external noises (clock accuracy is affected), the following measures are essential for optimizing your oscillating circuit configuration: (1) S-3530A, crystal oscillator and external capacitor (Cg) are placed as close to each other as possible. (2) Make high the insulation resistance between pins and the substrate wiring patterns of XIN and XOUT. (3) Do not place any signal or power lines close to the oscillating circuit. XIN Cg Rf Oscillating circuit internal constant standard values: Rf=20MΩ Rd=220KΩ XOUT Rd Cd=12pf Cd Crystal oscillator:32.768kHz CL=6pf S-3530A Cg=3 to 35pf Figure 20 Connection diagram 20 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A 2. Measurement of oscillating frequencies When power is turned on, S-3530A has the internal power-on detecting circuit operating and outputs a signal of 1 Hz from the INT1 pin to select the crystal oscillator and optimize the Cg value. Turn power on and measure the signal with a frequency counter following the circuit configuration shown in Figure 21. Refer to 12 and 16 pages in this document for further information. (*) If the error range is ±1ppm in relation to 1 Hz, time is shifted by approximately 2.6 seconds a month: 10-6 (1ppm) × 60 seconds × 60 minutes × 24 hours × 30 days = 2.592 seconds Note 1: Use a high-accuracy VDD frequency counter (1ppm order). XIN Note 2: Since the 1 Hz signal Cg continues to be output, you must send the reset command in normal operation. SDA XOUT Note 3: Determine Cg with its frequency slow/fast range SCL INT1 Open or pull-up property referred. Frequency counter INT2 VSS S-3530A Figure 21 Connection diagram Seiko Instruments Inc. 21 REAL-TIME CLOCK S-3530A 3. Adjustment of oscillating frequencies Matching of a crystal oscillator with the nominal frequency must be performed with parasitic capacitance on the board included. Select a crystal oscillator and optimize the Cg value in accordance with the flow chart below. START Select a crystal oscillator. (*1) YES Variable capacity <Trimer capacitor> NO <Fixed capacitor> Set to the center of Cg set (*3) variable capacitor. (*3) NO Does the frequency match ? Is Cg in the specification ? Change Cg. NO YES YES NO Is it an optimal value ? Make fine adjustment of the frequency in variable capacity. (*2) YES END (*1) For making matching adjustment of the IC with a crystal, contact an appropriate crystal maker to determine the CL value (load capacity) and RI value (equivalent serial resistance). The CL value = 6 pf and RI value = 30 kΩ TYP. are recommended values. (*2) Cg value selection must be performed on the actual PCB since parasitic capacitance affects it. Select the Cg value in a range from 3 pf to 35 pf. If the frequency does not match, change the CL value of the crystal. (*3) Adjust the rotation angle of the variable capacity so that the capacity value is somewhat smaller than the center, and confirm the oscillating frequency and the center value of the variable capacity. This is done in order to make the capacity of the center value smaller than one half of the actual capacity value because a smaller capacity value makes a greater quantity of changes in a frequency. If the frequency does not match, change the CL value of the crystal. Note 1 : Oscillating frequencies are changed by ambient temperature and power voltage. Refer to property samples. Note 2 : The 32 kHz crystal oscillator operates slower at higher or lower ambient temperature than 20 to 25°C. Therefore, it is recommended to adjust or set the oscillator to operate somewhat faster at normal temperature. 22 Seiko Instruments Inc. REAL-TIME CLOCK S-3530A n Absolute Maximum Ratings Item Table 5 Absolute maximum ratings Symbol Rating Unit Power voltage Input voltage Output voltage Operating temperature Storage temperature VDD VIN VOUT Topr Tstg -0.3 to +6.5 -0.3 to +6.5 -0.3 to +6.5 -40 to +85 -55 to +125 V V V °C °C Applicable pin, conditions SCL,SDA SDA,INT1, INT2 VDD=3.0V n Recommended Operating Conditions Table 6 Recommended operating conditions Item Symbol Condition Min. Typ. Power voltage VDD 1.7 3.0 Operating temperature Topr -20 +25 Max. 5.5 +70 Unit V °C n Oscillation Characteristics Table 7 Oscillation characteristics (Ta=25°C, VDD=3V, DS-VT-200 (crystal oscillator, CL=6pF, 32,768Hz) manufactured by Seiko Instruments Inc.) Item Oscillation start voltage Oscillation start time IC-to-IC frequency diversity Frequency voltage diversity Input capacity Output capacity Symbol VSTA TSTA δIC δV Cg Cd Condition Within ten seconds VDD=1.7 to 5.5V Applied to the XIN pin Applied to the XOUT pin Seiko Instruments Inc. Min. 1.7 -10 -3 3 Typ. 12 Max. 5.5 1 +10 +3 35 Unit V SEC ppm ppm/V pF pF 23 REAL-TIME CLOCK S-3530A n DC Electrical Characteristics Table 8 DC characteristics (3V) (Ta=25°C, VDD=3V, DS-VT-200 (crystal oscillator, CL=6pF, 32,768Hz) manufactured by Seiko Instruments Inc.) Item Symbol Condition Min. Typ. Max. Range of operating voltage Current consumption 1 VDD Ta=-20 to +70°C 1.7 3.0 5.5 Unit Applicable pin V IDD1 0.7 1.5 µA Current consumption 2 IDD2 12 20 µA Input leak current 1 Input leak current 2 Output leak current1 IIZH IIZL IOZH During no communications During communications (SCL=100 kHz) VIN= VDD VIN= VSS VOUT =VDD -0.5 -0.5 -0.5 Output leak current2 IOZL VOUT =VSS -0.5 VIH VIL IOL1 IOL2 VDET1 VOUT =0.4V VOUT=0.4V Ta=+25°C 0.8xVDD 1.5 5 1.8 2.5 10 2.0 VDET2 Ta=-20 to +70°C 1.72 Input voltage 1 Input voltage 2 Output current 1 Output current 2 Power voltage detection voltage 1 Power voltage detection voltage 2 µA SCL,SDA µA SCL,SDA µA INT1,INT2 SDA 0.5 µA INT1,INT2 SDA V SDA,SCL 0.2xVDD V SDA,SCL mA INT1,INT2 mA SDA 2.2 V 0.5 0.5 0.5 2.3 V Table 9 DC characteristics (5V) (Ta=25°C, VDD=3V, DS-VT-200 (crystal oscillator, CL=6pF, 32,768Hz) manufactured by Seiko Instruments Inc.) Item Symbol Condition Min. Typ. Max. Range of operating voltage Current consumption 1 VDD Ta=-20 to +70°C 1.7 3.0 5.5 Unit Applicable pin V IDD1 1.6 3.0 µA Current consumption 2 IDD2 26 40 µA Input leak current 1 Input leak current 2 Output leak current1 IIZH IIZL IOZH During no communications During communications (SCL=100 kHz) VIN= VDD VIN= VSS VOUT =VDD -0.5 -0.5 -0.5 Output leak current2 IOZL VOUT =VSS -0.5 VIH VIL IOL1 IOL2 VDET1 VOUT =0.4V VOUT =0.4V Ta=+25°C 0.8xVDD 2.0 6 1.8 3.5 12 2.0 VDET2 Ta=-20 to +70°C 1.72 Input voltage 1 Input voltage 2 Output current 1 Output current 2 Power voltage detection voltage 1 Power voltage detection voltage 2 24 Seiko Instruments Inc. µA SCL,SDA µA SCL,SDA µA INT1,INT2 SDA 0.5 µA INT1,INT2 SDA V SDA,SCL 0.2xVDD V SDA,SCL mA INT1,INT2 mA SDA 2.2 V 0.5 0.5 0.5 2.3 V REAL-TIME CLOCK S-3530A n AC Electrical Characteristics VDD Table 10 Measurement conditions Input pulse voltage Input pulse rising/falling time Output judgment voltage Output load 0.1×VDD to 0.9×VDD 20ns R=1.0k SDA 0.5×VDD C=100pF Note: Both IC and load powers are the same VDD. 100pF+pull-up resistance 1.0kΩ Figure 22 Output load circuit Table 11 AC properties Symbol Item SCL clock frequency SCL clock “L” time SCL clock “H” time SDA output delay time Start condition setup time Start condition holding time Data input setup time Data input holding time Stop condition setup time SCL, SDA rising time SCL, SDA falling time Bus release time Noise suppression time f SCL tLOW tHIGH tPD tSU.STA tHD.STA tSU.DAT tHD.DAT tSU.STO tR tF tBUF tI tHIGH tLOW VDD=1.7V to Min. Typ. 0 4.7 4.0 4.7 4.0 250 150 4.7 4.7 5.5V Max. 100 3.5 1.0 0.3 100 Unit kHz µs µs µs µs µs ns ns µs µs µs µs ns tR tF SCL tHD.DAT tSU.STA tHD.STA tSU.DAT tSU.STO SDA IN tPD tDH tBUF SDA OUT Figure 23 Bus timing Seiko Instruments Inc. 25 REAL-TIME CLOCK S-3530A n Sample of Characteristics (Reference values) (1) Standby current versus Cg (2) Standby current versus VDD Ta=25°C 2 Ta=25°C 3 2.5 VDD=5V 1.5 2 IDD1 [µA] IDD1 [µA] 1 1.5 VDD=3V 1 0.5 0.5 0 0 0 5 10 15 0 Cg [pf] 1 2 3 4 5 6 VDD [V] (3) Operating current consumption versus Input clock Ta=25°C 30 (4) Standby current versus temperature 2 VDD=5V 1.5 VDD=5V 20 IDD2 [µA] IDD1 [µA] VDD=3V 1 10 0.5 0 VDD=3V 0 0 25 50 75 100 125 -40 0 SCL frequency 80 Ta [°C] (5) Oscillating frequency versus Cg (6) Oscillating frequency versus VDD Ta=25°C 80 40 Ta=25°C 4 VDD=5V 60 2 ∆f/f [ppm] ∆f/f 40 [ppm] 0 20 -2 0 VDD=3V -4 -20 0 5 10 0 15 4 VDD [V] Cg [pf] 26 2 Seiko Instruments Inc. 6 REAL-TIME CLOCK S-3530A (7) Oscillating frequency versus temperature (8) Oscillation start time versus Cg Ta=25°C,VDD=3V 20 Ta=25°C 800 VDD=5V 600 ∆f/f [ppm] -40 TSTA [mS] -80 400 -120 200 -160 0 -50 0 50 100 VDD=3V 0 5 (9) Output current 1 (VOUT versus IOL1) (10) Output current 2 (VOUT versus I OL2) INT1 and INT2 pin, Ta=25°C SDA pin, Ta=25°C 50 VDD=5V VDD=5V 40 10 I OL2 [mA] I OL1 [mA] 30 VDD=3V 20 VDD=3V 5 15 Cg [pf] Ta [°C] 15 10 10 0 0 0 1 2 3 4 5 VOUT [V] 0 1 2 3 4 5 VOUT [V] 2 2 Purchase of I C components of Seiko Instruments Inc. conveys a license under the Philips I C Patent Rights to use these components in an I2C system, provided that the system conforms to the 2 I C Standard Specification as defined by Philips. Please note that any product or system incorporating this IC may infringe upon the Philips I2C Bus Patent Rights depending upon its configuration. 2 In the event that such product or system incorporating the I C Bus infringes upon the Philips Patent Rights, Seiko Instruments Inc. shall not bear any responsibility for any matters with regard to and arising from such patent infringement. Seiko Instruments Inc. 27 FS008-A 990531 8-pin SSOP Unit:mm Dimensions 3.1±0.3 8 5 1 4 0.22±0.1 0.65 Reel Specifications Taping Specifications 1 reel holds 2000 ICs. 2.0 0.05 1.55 0.05 13.5 0.5 4.0 0.1 0.3 0.05 1.55 0.05 1.4 0.1 (4.0) R135 6.9 0.1 Winding core • • • • • • The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.