19-4802; Rev 0; 10/00 ILABLE N KIT AVA EVALUATIO 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference Lower speed, pin-compatible versions of the MAX1449 are also available. Refer to the MAX1444 data sheet for a 40Msps version, the MAX1446 data sheet for a 60Msps version, and the MAX1448 data sheet for 80Msps. The MAX1449 has parallel, offset binary, CMOS-compatible, three-state outputs that can be operated from +1.7V to +3.6V to allow flexible interfacing. The device is available in a 5mm x 5mm 32-pin TQFP package and is specified over the extended industrial (-40°C to +85°C) temperature range. Features ♦ Single +3.3V Operation ♦ Excellent Dynamic Performance 58.5dB SNR at fIN = 20MHz 72dBc SFDR at fIN = 20MHz ♦ Low Power 62mA (Normal Operation) 5µA (Shutdown Mode) ♦ Fully Differential Analog Input ♦ Wide 2Vp-p Differential Input Voltage Range ♦ 400MHz -3dB Input Bandwidth ♦ On-Chip +2.048V Precision Bandgap Reference ♦ CMOS-Compatible Three-State Outputs ♦ 32-Pin TQFP Package ♦ Evaluation Kit Available Ordering Information PART MAX1449EHJ TEMP. RANGE -40°C to +85°C PIN-PACKAGE 32 TQFP Pin-Compatible, Lower Speed Selection Table ________________________Applications PART NUMBER SAMPLING SPEED MAX1444 40Msps MAX1446 60Msps MAX1448 80Msps Ultrasound Imaging Functional Diagram CCD Imaging Baseband and IF Digitization CLK VDD MAX1449 Digital Set-Top Boxes GND CONTROL Video Digitizing Applications IN+ T/H PIPELINE ADC IN- PD REF D E C 10 OUTPUT DRIVERS D9–D0 OVDD REF SYSTEM + BIAS OGND Pin Configuration appears at end of data sheet. REFOUT REFIN REFP COM REFN OE ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX1449 General Description The MAX1449 +3.3V, 10-bit analog-to-digital converter (ADC) features a fully differential input, a pipelined 10stage ADC architecture with wideband track-and-hold (T/H), and digital error correction incorporating a fully differential signal path. The ADC is optimized for lowpower, high-dynamic performance in imaging and digital communications applications. The converter operates from a single +2.7V to +3.6V supply, consuming only 186mW while delivering a 58.5dB (typ) signalto-noise ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a -3dB 400MHz bandwidth and may be operated with single-ended inputs. In addition to low operating power, the MAX1449 features a 5µA power-down mode for idle periods. An internal +2.048V precision bandgap reference is used to set the ADC’s full-scale range. A flexible reference structure allow’s the user to supply a buffered, direct, or externally derived reference for applications requiring increased accuracy or a different input voltage range. MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V IN+, IN- to GND........................................................-0.3V to VDD REFIN, REFOUT, REFP, REFN, and COM to GND..........................-0.3V to (VDD + 0.3V) OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V) D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 32-Pin TQFP (derate 11.1mW/°C above +70°C)...........889mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +3.3V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.75 ±2.4 LSB DC ACCURACY Resolution 10 Integral Nonlinearity INL fIN = 7.5MHz Differential Nonlinearity DNL fIN = 7.5MHz, no missing codes guaranteed Bits ±0.5 ±1.0 LSB Offset Error < ±1 ±1.7 % FS Gain Error 0 ±2 % FS ANALOG INPUT Input Differential Range Common-Mode Voltage Range VDIFF Differential or single-ended inputs VCOM Input Resistance RIN Input Capacitance CIN Switched capacitor load ±1.0 V VDD/2 ± 0.5 V 20 kΩ 5 pF 5.5 Cycles CONVERSION RATE Maximum Clock Frequency fCLK 105 Data Latency MHz DYNAMIC CHARACTERISTICS (fCLK = 105.26MHz, 4096-point FFT) Signal-To-Noise Ratio (Note 1) SNR fIN = 7.5MHz 56.3 58.5 fIN = 20MHz 55.8 58.5 fIN = 50MHz Signal-To-Noise And Distortion (Up to 5th Harmonic) (Note 1) SINAD fIN = 7.5MHz 55.3 fIN = 20MHz 55.1 fIN = 50MHz Spurious-Free Dynamic Range (Note 1) SFDR 2 58.2 58.1 dB 57.6 fIN = 7.5MHz 61 72 fIN = 20MHz, TA = +25°C 63 72 fIN = 50MHz dB 58 70 _______________________________________________________________________________________ dBc 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference (VDD = +3.3V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS fIN = 7.5MHz -72 HD3 fIN = 20MHz -72 fIN = 50MHz -70 Intermodulation Distortion (First 5 Odd-Order IMDs) (Note 2) IMD f1 = 38MHz at -6.5dB FS f2 = 42MHz at -6.5dB FS -76 dBc Third-Order Intermodulation Distortion (Note 2) IM3 f1 = 38MHz at -6.5dB FS f2 = 42MHz at -6.5dB FS -76 dBc fIN = 7.5MHz, TA = +25°C -70 -61.5 -61.5 Third-Harmonic Distortion (Note 1) Total Harmonic Distortion (First 5 Harmonics) (Note 1) THD Small-Signal Bandwidth Full-Power Bandwidth FPBW dBc fIN = 20MHz, TA = +25°C -70 fIN = 50MHz -70 dBc Input at -20dB FS, differential inputs 500 MHz Input at -0.5dB FS, differential inputs 400 MHz Aperture Delay tAD 1 ns Aperture Jitter tAJ 2 psRMS 2 ns Overdrive Recovery Time For 1.5 x full-scale input ±1 % ±0.25 degree 0.2 LSBRMS REFOUT 2.048 ±1% V TCREF 60 ppm/°C 1.25 mV/mA Differential Gain Differential Phase Output Noise IN+ = IN- = COM INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation EXTERNAL REFERENCE Positive Reference REFP VREFIN = +2.048V 2.162 V Negative Reference REFN VREFIN = +2.048V 1.138 V Differential Reference Voltage ∆VREF VREFP -VREFN, VREFIN = +2.048V REFIN Resistance RREFIN 0.98 1.024 1.07 >50 V MΩ DIGITAL INPUTS (CLK, PD, OE) Input High Threshold Input Low Threshold CLK 0.8 x VDD PD, OE 0.8 x VDD VIH V CLK 0.2 x VDD PD, OE 0.2 x VDD VIL V _______________________________________________________________________________________ 3 MAX1449 ELECTRICAL CHARACTERISTICS (continued) MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, OVDD = +2.0V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = +2.048V, REFOUT connected to REFIN through a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 105MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Hysteresis Input Leakage SYMBOL CONDITIONS VIH = VDD = OVDD ±5 VIL = 0 ±5 Output Voltage High VOH ISOURCE = 200µA Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT OE = OVDD Output Supply Current CIN 5 TIMING CHARACTERISTICS CLK Rise-to-Output Data Valid µA pF 0.2 OVDD - 0.2 V V ±10 5 µA pF VDD 2.7 3.3 3.6 OVDD 1.7 3.3 3.6 V Operating, fIN = 20MHz at -0.5dB FS 58 74 mA Shutdown, clock idle, PD = OE = OVDD 4 15 µA Operating, CL = 15pF , fIN = 20MHz at -0.5dB FS 10 IVDD IOVDD Shutdown, clock idle, PD = OE = OVDD Power Supply Rejection UNITS V IIL ISINK = 200µA Analog Supply Current MAX IIH VOL Output Supply Voltage TYP 0.1 Input Capacitance DIGITAL OUTPUTS (D9–D0) Output Voltage Low POWER REQUIREMENTS Analog Supply Voltage MIN VHYST PSRR tDO 1 V mA 10 µA Offset ±0.1 mV/V Gain ±0.1 %/V Figure 6 (Note 3) 5 8 ns OE Fall-to-Output Enable tENABLE Figure 5 10 ns OE Rise-to-Output Disable tDISABLE Figure 5 15 ns CLK Pulse Width High tCH Figure 6, clock period 9.52ns 4.76 ±0.47 ns CLK Pulse Width Low tCL Figure 6, clock period 9.52ns 4.76 ±0.47 ns 1.5 µs Wake-Up Time tWAKE (Note 4) Note 1: SNR, SINAD, THD, SFDR and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale input voltage range. Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is 6dB better if referenced to the two-tone envelope. Note 3: Digital outputs settle to VIH,VIL. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. 4 _______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference 2ND HARMONIC 3RD HARMONIC -60 2ND HARMONIC -50 3RD HARMONIC -60 MAX1449 toc03 SNR = 57.9dB SINAD = 56.7dB THD = -71.3dBc SFDR = 71.1dBc -20 -30 2ND HARMONIC -40 -50 3RD HARMONIC -60 -70 -70 -70 -80 -80 -80 -90 -90 -90 -100 -100 -100 ANALOG INPUT FREQUENCY (MHz) 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz) FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) FFT PLOT (fIN = 19.99MHz, 8192-POINT FFT, SINGLE-ENDED INPUT) TWO-TONE INTERMODULATION (8192-POINT IMD, DIFFERENTIAL INPUT) 40 50 60 0 SNR = 57.7dB SINAD = 57.5dB THD = -71.8dBc SFDR = 74.4dBc -10 -20 2ND HARMONIC -50 -60 3RD HARMONIC 10 20 30 40 50 SNR = 57.7dB SINAD = 57.2dB THD = -67dBc SFDR = 67.7dBc -20 -30 2ND HARMONIC -40 -50 0 60 0 -10 AMPLITUDE (dB) -30 -40 0 0 3RD HARMONIC -60 -20 -50 -70 -80 -80 -90 -90 -90 -100 -100 -100 30 40 50 60 0 SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY DIFFERENTIAL 74 3RD ORDER IMD 0 60 60 DIFFERENTIAL 58 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz) 60 TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY MAX1449 toc07 80 10 20 30 40 50 ANALOG INPUT FREQUENCY (MHz) -50 MAX1449 toc08 20 2ND ORDER IMD -60 -70 ANALOG INPUT FREQUENCY (MHz) f1 -40 -80 10 f2 -30 -70 0 f1 = 38MHz AT -6.5dB FS f2 = 42MHz AT -6.5dB FS -10 60 MAX1449 toc09 30 AMPLITUDE (dB) 20 MAX1449 toc05 10 MAX1449 toc06 ANALOG INPUT FREQUENCY (MHz) 0 AMPLITUDE (dB) -30 -40 0 -10 AMPLITUDE (dB) AMPLITUDE (dB) -40 -50 -20 MAX1449 toc04 AMPLITUDE (dB) -30 SNR = 58.5dB SINAD = 58.4dB THD = -73.7dBc SFDR = 75.9dBc -10 MAX1449 toc02 SNR = 58.6dB SINAD = 58.4dB THD = -72.7dBc SFDR = 73.6dBc -20 0 MAX1449 toc01 0 -10 UNDERSAMPLING FFT PLOT (fIN = 50.12MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) FFT PLOT (fIN = 19.99MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) FFT PLOT (fIN = 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT) -56 SINGLE-ENDED 56 62 54 56 52 50 THD (dBc) 68 SNR (dB) SFDR (dBc) SINGLE-ENDED 10 ANALOG INPUT FREQUENCY (MHz) 100 -68 DIFFERENTIAL -74 -80 50 1 SINGLE-ENDED -62 1 10 ANALOG INPUT FREQUENCY (MHz) 100 1 10 100 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 5 MAX1449 Typical Operating Characteristics (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) SINGLE-ENDED 54 0 -2 2 0 -2 -4 -4 -6 -6 52 -8 -8 50 1 10 1 100 ANALOG INPUT FREQUENCY (MHz) SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 19MHz) 100 1 1000 1000 SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 19MHz) TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 19MHz) 60 -50 -55 -60 65 55 THD (dBc) SNR (dB) 50 60 -65 -70 45 55 50 -75 40 -12 -9 -6 -3 -80 -12 0 -9 -6 -3 0 INPUT POWER (dB FS) INPUT POWER (dB FS) SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 19MHz) SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE 50 45 40 80 76 -9 -6 INPUT POWER (dB FS) -3 0 0 fIN = 26.1696MHz 66 62 72 58 68 54 50 64 -12 -3 SIGNAL-TO-NOISE vs. TEMPERATURE SNR (dB) 55 -6 70 MAX1449 toc17 fIN = 26.1696MHz SFDR (dBc) 60 -9 INPUT POWER (dB FS) 84 MAX1449 toc16 65 -12 MAX1449 toc18 SFDR (dBc) 100 ANALOG INPUT FREQUENCY (MHz) 70 6 10 ANALOG INPUT FREQUENCY (MHz) MAX1449 toc14 75 10 65 MAX1449 toc13 80 MAX1449 toc12 MAX1449 toc11 2 VIN = 100mVp-p 4 MAX1449 toc15 56 6 AMPLITUDE (dB) DIFFERENTIAL 4 AMPLITUDE (dB) SINAD (dB) 6 MAX1449 toc10 60 58 SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED SIGNAL-T0-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY SINAD (dB) MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE fIN = 26.1696MHz -64 0.5 MAX1449 toc20 70 MAX1449 toc19 -60 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (BEST STRAIGHT LINE) fIN = 26.1696MHz 66 MAX1449 toc21 TOTAL HARMONIC DISTORTION vs. TEMPERATURE 0.4 0.3 -72 INL (LSB) SINAD (dB) THD (dBc) 0.2 -68 62 0.1 0 58 -0.1 -0.2 54 -76 -0.3 50 -15 10 35 60 -0.4 -40 85 -15 0 -0.1 -0.2 200 400 600 800 1000 0.06 0.04 10 35 60 ANALOG SUPPLY CURRENT vs. TEMPERATURE 85 1 0 -40 -15 10 35 60 85 DIGITAL SUPPLY CURRENT vs. TEMPERATURE 15 MAX1449 toc26 MAX1449 toc25 2 TEMPERATURE (°C) 70 65 12 57 55 55 50 53 45 51 IOVDD (mA) 60 IVDD (mA) IVDD (mA) -15 ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE 59 1200 -2 -40 TEMPERATURE (°C) 61 1000 -1 DIGITAL OUTPUT CODE 63 800 3 0 1200 600 4 0.02 0 400 OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE, VREFIN = +2.048V -0.3 -0.4 200 GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE, VREFIN = +2.048V OFFSET ERROR (LSB) DNL (LSB) 0.2 0.1 0 DIGITAL OUTPUT CODE 0.08 GAIN ERROR (LSB) 0.3 85 MAX1449 toc23 0.4 60 0.10 MAX1449 toc22 0.5 35 TEMPERATURE (°C) TEMPERATURE (°C) DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 10 MAX1449 toc24 -40 MAX1449 toc27 -80 2.85 3.00 3.15 VDD (V) 3.30 3.45 3.60 6 3 40 2.70 9 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX1449 Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +3.3V, OVDD = +2.0V, internal reference, differential input at -0.5dB FS, fCLK = 106.2345MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) DIGITAL SUPPLY CURRENT vs. TEMPERATURE ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGE 9 IOVDD (µA) IVDD (µA) 8 2.60 2.40 6 2.00 -15 10 35 60 85 0 2.70 2.85 3.00 TEMPERATURE (°C) 3.15 3.30 3.45 2.0 2.3 2.6 VDD (V) INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE SFDR MAX1449 toc32 fIN = 50.123MHz 75 2.100 MAX1449 toc31 80 3.0 OVDD (V) SFDR, SNR, THD, SINAD vs. CLOCK FREQUENCY 2.075 70 VREF (V) SFDR, SNR, THD, SINAD (dB) 3.60 THD 65 2.050 SNR 60 2.025 SINAD 55 50 2.000 100 104 108 112 116 120 2.70 2.85 3.00 CLOCK FREQUENCY (MHz) 3.15 3.30 3.45 3.60 VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE OUTPUT NOISE HISTOGRAM (DC INPUT) 70,000 MAX1449 toc33 2.10 2.08 MAX1449 toc34 -40 6 3 2.20 4 12 MAX1449 toc30 2.80 10 DIGITAL POWER-DOWN CURRENT vs. DIGITAL SUPPLY VOLTAGE MAX1449 toc29 3.00 MAX1449 toc28 12 IOVDD (mA) 64676 60,000 50,000 2.06 COUNTS VREF (V) MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference 2.04 40,000 30,000 20,000 2.02 10,000 0 2.00 -40 -15 10 35 TEMPERATURE (°C) 8 60 85 0 607 N-2 N-1 N 252 0 N+1 N+2 DIGITAL OUTPUT CODE _______________________________________________________________________________________ 3.3 3.6 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference PIN NAME 1 REFN FUNCTION Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 2 COM Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor. 3, 9, 10 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 4, 5, 8, 11, 14, 30 GND Analog Ground 6 IN+ Positive Analog Input. For single-ended operation connect signal source to IN+. 7 IN- Negative Analog Input. For single-ended operation connect IN- to COM. 12 CLK 13 PD Power Down Input. High: Power-down mode Low: Normal operation 15 OE Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled 16–20 D9–D5 Three-State Digital Outputs D9–D5. D9 is the MSB. 21 OVDD Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. Conversion Clock Input 22 T.P. 23 OGND Output Driver Ground Test Point. Do not connect. 24–28 D4–D0 Three-State Digital Outputs D4–D0. D0 is the LSB. 29 REFOUT 31 REFIN Reference Input. VREFIN = 2 ✕ (VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. 32 REFP Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF capacitor. Internal Reference Voltage Output. May be connected to REFIN through a resistor or a resistordivider. _______________________________________________________________________________________ 9 MAX1449 Pin Description MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference Detailed Description The MAX1449 uses a 10-stage, fully differential, pipelined architecture (Figure 1), that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage every half-clock cycle. Counting the delay through the output latch, the clock-cycle latency is 5.5. A 1.5-bit (2-comparator) flash ADC converts the held input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result back into an analog voltage, which is then subtracted from the original held input signal. The resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage where the process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1bit resolution. Digital error-correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Input Track-and-Hold (T/H) Circuit Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuit in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a and S5b are closed. The fully differential circuit samples the input signal onto the two capacitors C2a and C2b through switches S4a and S4b. Switches S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a and S4b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltage is held on capacitors C2a and C2b. The amplifier is used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. This value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The wide input bandwidth T/H amplifier allows the MAX1449 to track and sample/hold analog inputs of high frequencies beyond Nyquist. The analog inputs IN+ and IN- can be driven either differentially or single-ended. It is recommended to match the impedance of IN+ and IN- and set the common-mode voltage to mid-supply (VDD/2) for optimum performance. Analog Input and Reference Configuration The full-scale range of the MAX1449 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The ADC’s full-scale range is user-adjustable through the REFIN pin, which provides a high input impedance for this purpose. REFOUT, REFP, COM (VDD/2), and REFN are internally buffered low-impedance outputs. INTERNAL BIAS COM S5a S2a C1a MDAC VIN Σ T/H x2 S3a VOUT S4a IN+ FLASH ADC OUT DAC C2a S4c S1 1.5 BITS OUT INS4b C2b C1b VIN STAGE 1 STAGE 2 S3b STAGE 10 S2b INTERNAL BIAS DIGITAL CORRECTION LOGIC 10 D9–D0 VIN = INPUT VOLTAGE BETWEEN IN+ AND IN- (DIFFERENTIAL OR SINGLE-ENDED) Figure 1. Pipelined Architecture—Stage Blocks 10 TRACK HOLD TRACK CLK INTERNAL HOLD NON-OVERLAPPING CLOCK SIGNALS Figure 2. Internal T/H Circuit ______________________________________________________________________________________ S5b COM 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference In internal reference mode, the internal reference output REFOUT can be tied to the REFIN pin through a resistor (e.g., 10kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability purposes it is recommended to bypass REFIN with a >10nF capacitor to GND. In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a stable and accurate voltage at REFIN. In this mode, REFOUT may be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, REFIN is connected to GND thereby deactivating the on-chip buffers of REFP, COM, and REFN. With their buffers shut down, these pins become high impedance and can be driven by external reference sources. Clock Input (CLK) The MAX1449’s CLK input accepts CMOS-compatible clock signals. Since the inter-stage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the falling edge of the clock signal, mandating this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the ADC as follows: SNR = 20 × log (0.5 × π × fIN × tAJ) where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be consid- ered as an analog input and routed away from any analog input or other digital signal lines. The MAX1449 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics. (See Figures 3 (3a, 3b) and 4 (4a, 4b) for the relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), or signal-to-noise plus distortion (SINAD) versus duty cycle.) Output Enable (OE), Power Down (PD), and Output Data (D0–D9) All data outputs, D0 (LSB) through D9 (MSB), are TTL/CMOS logic-compatible. There is a 5.5 clock-cycle latency between any particular sample and its valid output data. The output coding is straight offset binary (Table 1). With OE and PD high, the digital outputs enter a high-impedance state. If OE is held low with PD high, the outputs are latched at the last value prior to the power down. The capacitive load on the digital outputs D0 through D9 should be kept as low as possible (<15pF), to avoid large digital currents that could feed back into the analog portion of the MAX1449, thereby degrading its dynamic performance. The use of buffers on the digital outputs of the ADC can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1449, small series resistors (e.g., 100Ω) may be added to the digital output paths, close to the ADC. Figure 5 displays the timing relationship between output enable and data output valid as well as power-down/wake-up and data output valid. System Timing Requirements Figure 6 depicts the relationship between the clock input, analog input, and data output. The MAX1449 samples at the falling edge of the input clock. Output Table 1. MAX1449 Output Code for Differential Inputs DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY VREF × 511/512 VREF × 510/512 VREF × 1/512 0 - VREF × 1/512 - VREF × 511/512 - VREF × 512/512 +Full Scale -1LSB +Full Scale -2LSB +1LSB Bipolar Zero -1LSB Negative Full Scale + 1LSB Negative Full Scale 11 1111 1111 11 1111 1110 10 0000 0001 10 0000 0000 01 1111 1111 00 0000 0001 00 0000 0000 *VREF = VREFP = VREFN ______________________________________________________________________________________ 11 MAX1449 The MAX1449 provides three modes of reference operation: • Internal reference mode • Buffered external reference mode • Unbuffered external reference mode MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference 90 -50 fIN = 25.123MHz AT -0.5dB FS fIN = 25.123MHz AT -0.5dB FS -55 82 THD (dBc) SFDR (dBc) -60 74 66 -65 -70 -75 58 -80 -85 50 35 42 49 56 63 35 70 42 Figure 3a. Spurious Free Dynamic Range vs. Clock Duty Cycle (Differential Input) 62 49 56 63 70 CLOCK DUTY CYCLE (%) CLOCK DUTY CYCLE (%) Figure 4a. Total Harmonic Distortion vs. Clock Duty Cycle (Differential Input) 64 fIN = 25.123MHz AT -0.5dB FS 61 fIN = 25.123MHz AT -0.5dB FS 62 60 59 SINAD (dB) SNR (dB) 60 58 57 58 56 56 54 55 52 54 35 42 49 56 63 70 CLOCK DUTY CYCLE (%) 35 42 49 56 63 70 CLOCK DUTY CYCLE (%) Figure 3b. Signal-to-Noise Ratio vs. Clock Duty Cycle (Differential Input) Figure 4b. Signal-to-Noise Plus Distortion vs. Clock Duty Cycle (Differential Input) data is valid on the rising edge of the input clock. The output data has an internal latency of 5.5 clock cycles. Figure 6 also determines the relationship between the input clock parameters and the valid output data. age follower and inverter. A low-pass filter, to suppress some of the wideband noise associated with high-speed op amps, follows the op amps. The user may select the RISO and CIN values to optimize the filter performance, to suit a particular application. For the application in Figure 7, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small bypassing capacitor. Applications Information Figure 7 depicts a typical application circuit containing a single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting purposes. The input is buffered and then split to a volt- 12 ______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference Single-Ended AC-Coupled Input Signal Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high bandwidth, low-noise, and low-distortion to maintain the integrity of the input signal. Grounding, Bypassing and Board Layout The MAX1449 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multi-layer boards with separated ground and power planes produce the highest level of signal integrity. Consider In general, the MAX1449 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (IN+, IN-) are balanced, and each of the inputs only requires half the signal swing compared to single-ended mode. OE tDISABLE tENABLE OUTPUT DATA D9–D0 HIGH-Z HIGH-Z VALID DATA Figure 5. Output Enable Timing 5.5 CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT CLOCK INPUT tD0 DATA OUTPUT tCH N-6 N-5 N-4 tCL N-3 N-2 N-1 N N+1 Figure 6. System and Output Timing Diagram ______________________________________________________________________________________ 13 MAX1449 Using Transformer Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1449 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the overall distortion. MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference +5V 0.1µF LOWPASS FILTER IN+ MAX4108 RISO 50Ω 0.1µF 300Ω CIN 22pF 0.1µF -5V MAX1449 600Ω 300Ω 600Ω COM 0.1µF +5V +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF IN- MAX4108 RISO 50Ω 300Ω -5V CIN 22pF 0.1µF 300Ω 300Ω 600Ω Figure 7. Typical Application Circuit Using the Internal Reference the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC's package. The two ground planes should be joined at a single point, such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital 14 signal traces away from sensitive analog traces. Keep all signal lines short and free of 90° turns. Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1449 are measured using the best straight-line fit method. ______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference IN+ 22pF Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N Bits): SNR(MAX) = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. MAX1449 0.1µF VIN 1 N.C. 2 3 T1 6 5 COM 2.2µF 4 0.1µF MINICIRCUITS TT1–6 25Ω IN22pF Figure 8. Using a Transformer for AC Coupling Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is computed from: Dynamic Parameter Definitions Aperture Jitter Figure 10 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. ENOB = (SINAD − 1.76) 6.02 REFP 1k VIN 0.1µF RISO IN+ MAX4108 100Ω CIN 1k MAX1449 COM REFN 0.1µF RISO 100Ω RISO = 50Ω CIN = 22pF INCIN Figure 9. Single-Ended AC-Coupled Input ______________________________________________________________________________________ 15 MAX1449 Aperture Delay Aperture delay (tAD) is the time defined between the falling-edge of the sampling clock and the instant when an actual sample is taken (Figure 10). 25Ω MAX1449 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. CLK ANALOG INPUT Intermodulation Distortion (IMD) The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale. tAD tAJ SAMPLED DATA (T/H) T/H TRACK HOLD TRACK Figure 10. T/H Aperture Timing Chip Information TRANSISTOR COUNT: 5684 PROCESS: CMOS Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: REFP REFIN GND REFOUT D0 D1 D2 D3 32 31 30 29 28 27 26 25 REFN 1 24 D4 COM 2 23 OGND VDD 3 22 T.P. GND 4 21 OVDD MAX1449 GND 5 IN+ 6 19 D6 IN- 7 18 D7 GND 8 17 D8 9 10 11 12 13 14 15 16 GND CLK PD GND OE D9 20 D5 VDD where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. TOP VIEW VDD (V22 + V32 + V42 + V52 ) THD = 20 × log V1 Pin Configuration TQFP 16 ______________________________________________________________________________________ 10-Bit, 105Msps, Single +3.3V, Low-Power ADC with Internal Reference 32L,TQFP.EPS ______________________________________________________________________________________ 17 MAX1449 Package Information 10-Bit, 80Msps, Single +3.3V, Low-Power ADC with Internal Reference MAX1449 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.