19-2524; Rev 0; 7/02 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs For lower speed, pin-compatible, 8-bit versions of the MAX1190, refer to the MAX1195–MAX1198 data sheets. Applications Baseband I/Q Sampling Multichannel IF Sampling Ultrasound and Medical Imaging Battery-Powered Instrumentation ♦ User-Selectable Output Format—Two’s Complement or Offset Binary ♦ Pin-Compatible, Lower-Speed, 10-Bit and 8-Bit Versions Available Ordering Information PART MAX1190ECM TEMP RANGE PIN-PACKAGE -40°C to +85°C 48 TQFP-EP* *EP = Exposed paddle. Functional Diagram appears at end of data sheet. Pin Configuration 37 38 39 40 41 42 43 44 45 46 REFN REFP REFIN REFOUT D9A D8A D7A D6A D5A D4A D3A D2A Pin-compatible lower speed versions of the MAX1190 are also available. Refer to the MAX1180–MAX1184 data sheets for 105Msps/80Msps/65Msps/40Msps. In addition to these speed grades, this family includes two multiplexed output versions (MAX1185/MAX1186 for 20Msps/40Msps), for which digital data is presented time-interleaved and on a single, parallel 10-bit output port. ♦ 400MHz -3dB Input Bandwidth ♦ On-Chip 2.048V Precision Bandgap Reference 47 The MAX1190 features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two’s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of 1.7V to 3.6V for flexible interfacing with various logic families. The MAX1190 is available in a 7mm ✕ 7mm, 48-pin TQFP-EP package, and is specified for the extended industrial (-40°C to +85°C) temperature range. ♦ 0.08dB Gain and 0.8° Phase Matching ♦ Wide ±1VP-P Differential Analog Input Voltage Range 48 An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. Features ♦ Single 3.3V Operation ♦ Excellent Dynamic Performance 57dB SINAD at fIN = 60MHz 64dBc SFDR at fIN = 60MHz ♦ -71dBc Interchannel Crosstalk at fIN = 60MHz ♦ Low Power 492mW (Normal Operation) 10mW (Sleep Mode) 3.3µW (Shutdown Mode) COM 1 36 D1A VDD GND 2 35 3 34 INA+ INAVDD GND INBINB+ GND VDD CLK 4 33 5 32 D0A OGND OVDD OVDD OGND D0B D1B D2B D3B 31 6 MAX1190 7 30 8 29 9 28 10 27 11 26 12 25 D4B D5B VSAT Terminals 24 23 22 21 20 19 18 17 16 15 14 GND VDD VDD GND T/B SLEEP PD OE D9B D8B D7B D6B Set-Top Boxes 13 WLAN, WWAN, WLL, MMDS Modems TQFP-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1190 General Description The MAX1190 is a 3.3V, dual 10-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The MAX1190 is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single 2.8V to 3.6V supply, consuming only 492mW while delivering a typical signal-to-noise and distortion (SINAD) of 57dB at an input frequency of 60MHz and a sampling rate of 120Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters can also be operated with single-ended inputs. In addition to low operating power, the MAX1190 features a 3mA sleep mode, as well as a 1µA power-down mode to conserve power during idle periods. MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs ABSOLUTE MAXIMUM RATINGS VDD, OVDD to GND ...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND ...............................-0.3V to VDD REFIN, REFOUT, REFP, REFN, COM, CLK to GND............................................-0.3V to (VDD + 0.3V) OE, PD, SLEEP, T/B, D9A–D0A, D9B–D0B to OGND ...........-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3.3V; OVDD = 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10kΩ resistor; VREFIN = 2.048V; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 120MHz; TA = TMIN to TMAX, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution 10 Bits ±0.75 ±3 LSB ±0.4 +1.5 LSB Offset Error <±1 ±1.8 %FS Gain Error 0 ±2 %FS Integral Nonlinearity Differential Nonlinearity INL fIN = 7.47MHz DNL fIN = 7.47MHz, no missing codes guaranteed -1 ANALOG INPUT Differential Input Voltage Range Common-Mode Input Voltage Range VDIFF Differential or single-ended inputs VCM Input Resistance RIN Input Capacitance CIN Switched capacitor load ±1.0 V VDD / 2 ± 0.5 V 20 kΩ 5 pF 5 Clock Cycles CONVERSION RATE Maximum Clock Frequency fCLK 120 Data Latency MHz DYNAMIC CHARACTERISTICS (fCLK = 120MHz, 4096-point FFT) Signal-to-Noise Ratio Signal-to-Noise and Distortion 2 SNR SINAD fINA or B = 20.01MHz at -0.5dB FS, TA = +25°C 55 58.5 fINA or B = 30.09MHz at -0.5dB FS 58.2 fINA or B = 59.74MHz at -0.5dB FS 58 fINA or B = 20.01MHz at -0.5dB FS, TA = +25°C 54.5 dB 57.5 fINA or B = 30.09MHz at -0.5dB FS 57 fINA or B = 59.74MHz at -0.5dB FS 57 _______________________________________________________________________________________ dB Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = 3.3V; OVDD = 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10kΩ resistor; VREFIN = 2.048V; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 120MHz; TA = TMIN to TMAX, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Spurious-Free Dynamic Range Third-Harmonic Distortion SYMBOL SFDR HD3 Intermodulation Distortion (First Five Odd-Order IMDs) IMD Third-Order Intermodulation Distortion IM3 Total Harmonic Distortion (First Four Harmonics) THD Small-Signal Bandwidth Full-Power Bandwidth FPBW CONDITIONS fINA or B = 20.01MHz at -0.5dB FS, TA = +25°C MIN TYP 58 67 fINA or B = 30.09MHz at -0.5dB FS 67 fINA or B = 59.74MHz at -0.5dB FS 64 fINA or B = 20.01MHz at -0.5dB FS, TA = +25°C -67 fINA or B = 30.09MHz at -0.5dB FS -67 fINA or B = 59.74MHz at -0.5dB FS fIN1(A or B) = 43.393MHz at -6.5dB FS, fIN2(A or B) = 48.9017MHz at -6.5dB FS (Note 1) fIN1(A or B) = 43.393MHz at -6.5dB FS, fIN2(A or B) = 48.9017MHz at -6.5dB FS (Note 1) -64 MAX dBc dBc -73 dBc -83 fINA or B = 20.01MHz at -0.5dB FS, TA = +25°C -65 fINA or B = 30.09MHz at -0.5dB FS -65 UNITS dBc -58 dBc fINA or B = 59.74MHz at -0.5dB FS -63 Input at -20dB FS, differential inputs 500 MHz Input at -0.5dB FS, differential inputs 400 MHz Aperture Delay tAD 1 ns Aperture Jitter tAJ 2 psRMS 2 ns 2.048 ±3% V 1.25 mV/mA 60 ppm/°C For 1.5 × full-scale input Overdrive Recovery Time INTERNAL REFERENCE Reference Output Voltage VREFOUT Load Regulation Reference Temperature Coefficient TCREF BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V) Positive Reference Output Voltage VREFP (Note 2) 2.162 V Negative Reference Output Voltage VREFN (Note 2) 1.138 V Common-Mode Level VCOM (Note 2) 1.651 V Differential Reference Output Voltage Range ∆VREF ∆VREF = VREFP - VREFN REFIN Resistance RREFIN 0.95 1.024 >50 1.09 V MΩ _______________________________________________________________________________________ 3 MAX1190 ELECTRICAL CHARACTERISTICS (continued) MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V; OVDD = 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10kΩ resistor; VREFIN = 2.048V; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 120MHz; TA = TMIN to TMAX, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER Maximum REFP, COM Source Current Maximum REFP, COM Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL CONDITIONS MIN TYP MAX UNITS ISOURCE 5 mA ISINK -250 µA ISOURCE 250 µA ISINK -5 mA UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM) REFP, REFN Input Resistance RREFP, RREFN Measured between REFP and COM, and REFN and COM Differential Reference Input Voltage Range ∆VREF ∆VREF = VREFP - VREFN 3.4 kΩ 1.024 ± 10% V COM Input Voltage Range VCOM VDD / 2 ± 10% V REFP Input Voltage VREFP VCOM + ∆VREF / 2 V REFN Input Voltage VREFN VCOM - ∆VREF / 2 V DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) Input High Threshold Input Low Threshold Input Hysteresis Input Leakage CLK 0.8 × VDD PD, OE, SLEEP, T/B 0.8 × OVDD VIH V CLK 0.2 × VDD PD, OE, SLEEP, T/B 0.2 × OVDD VIL VHYST IIH IIL 0.1 V VIH = VDD (CLK) ±5 VIH = OVDD (PD, OE, SLEEP, T/B) ±5 ISINK = -200µA Output Voltage High VOH ISOURCE = 200µA Three-State Leakage Current ILEAK OE = OVDD Three-State Output Capacitance COUT OE = OVDD µA ±5 VIL = 0 Input Capacitance CIN DIGITAL OUTPUTS (D9A–D0A, D9B–D0B) Output Voltage Low VOL V 5 pF 0.2 OVDD 0.2 V V ±10 5 µA pF POWER REQUIREMENTS Analog Supply Voltage Range VDD 2.8 3.3 3.6 V Output Supply Voltage Range OVDD 1.7 2.5 3.6 V 4 _______________________________________________________________________________________ Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs (VDD = 3.3V; OVDD = 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10kΩ resistor; VREFIN = 2.048V; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 120MHz; TA = TMIN to TMAX, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization; typical values are at TA = +25°C.) PARAMETER SYMBOL Analog Supply Current Output Supply Current Analog Power Dissipation Power-Supply Rejection Ratio TIMING CHARACTERISTICS CLK Rise to Output Data Valid Time OE Fall to Output Enable Time OE Rise to Output Disable Time IVDD IOVDD PDISS PSRR tDO Operating, fINA and B = 20.01MHz at -0.5dB FS Sleep mode tCH CLK Pulse Width Low tCL tWAKE MIN TYP MAX 149 185 1 Operating, fINA and B = 20.01MHz at -0.5dB FS; see Typical Operating Characteristics section, Digital Supply Current vs. Analog Input Frequency 16 Sleep mode 100 Shutdown, clock idle, PD = OE = OVDD Operating, fINA and B = 20.01MHz at -0.5dB FS Sleep mode UNITS mA 3 Shutdown, clock idle, PD = OE = OVDD 15 µA mA 2 10 492 611 10 µA mW mW Shutdown, clock idle, PD = OE = OVDD 3.3 Offset, VDD ±5% ±3.4 mV/V Gain, VDD ±5% ±0.81 %/V CL = 20pF (Note 3) tENABLE tDISABLE CLK Pulse Width High Wake-Up Time CONDITIONS Clock period: 8.34ns; see Typical Operating Characteristics section, AC Performance vs. Clock Duty Cycle Clock period: 8.34ns; see Typical Operating Characteristics section, AC Performance vs. Clock Duty Cycle Wake up from sleep mode (Note 4) Wake up from shutdown mode (Note 4) 4.8 50 7.4 µW ns 4.7 1.2 ns ns 4.17 ns 4.17 ns 0.65 µs 1.2 CHANNEL-TO-CHANNEL MATCHING Crosstalk fINA or B = 20.01MHz at -0.5dB FS -71 Gain Matching fINA or B = 20.01MHz at -0.5dB FS (Note 5) 0.08 Phase Matching fINA or B = 20.01MHz at -0.5dB FS (Note 6) 0.8 dBc ±0.2 dB Degrees Intermodulation distortion is the total power of the intermodulation products relative to the total input power. REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor. Digital outputs settle to VIH, VIL. Parameter guaranteed by design. With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the fundamental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test. Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test. Note 1: Note 2: Note 3: Note 4: Note 5: _______________________________________________________________________________________ 5 MAX1190 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 3.3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dB FS, fCLK = 120MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) -75 -100 12 24 36 48 60 -125 12 0 24 36 48 60 0 12 24 36 48 60 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) -75 -50 fINA -75 -100 -100 12 24 36 48 MAX1190 toc03b fINB -75 -125 0 60 -50 -100 -125 -125 CHB fINA = 49.0189MHz fINB = 59.7427MHz fCLK = 120.0128MHz AINA/AINB = -0.52dB FS -25 AMPLITUDE (dB) fINB -50 CHA fINA = 59.7427MHz fINB = 49.0189MHz fCLK = 120.0128MHz AINA/AINB = -0.52dB FS -25 0 MAX1190 toc03a 0 MAX1190 toc02b CHB fINA = 23.9967MHz fINB = 31.0873MHz fCLK = 120.0128MHz AINA/AINB = -0.52dB FS AMPLITUDE (dB) 12 24 36 48 60 0 12 24 36 48 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TWO-TONE IMD PLOT (8192-POINT RECORD, DIFFERENTIAL INPUT) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY fIN1 -75 54 -100 52 -125 CHA 56 12 24 36 48 ANALOG INPUT FREQUENCY (MHz) 60 CHB 58 56 CHA 54 52 50 0 60 60 MAX1190 toc06 58 SNR (dB) fIN2 -50 CHB SINAD (dB) fIN1 = 43.3933MHz fIN2 = 48.9017MHz fCLK = 120.0128MHz AIN = -6.5dB FS -25 60 MAX1190 toc04 0 MAX1190 toc05 AMPLITUDE (dB) -75 ANALOG INPUT FREQUENCY (MHz) 0 0 fINA -50 -100 -125 0 6 -75 CHA fINA = 31.0873MHz fINB = 23.9967MHz fCLK = 120.0128MHz AINA/AINB = -0.52dB FS -25 -100 -125 -25 fINB -50 0 AMPLITUDE (dB) fINA -50 -25 AMPLITUDE (dB) AMPLITUDE (dB) -25 fINA = 12.9799MHz fINB = 20.0119MHz fCLK = 120.0128MHz AINA/AINB = -0.52dB FS CHB FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1190 toc01b fINA = 20.0119MHz fINB = 12.9799MHz fCLK = 120.0128MHz AINA/AINB = -0.52dB FS CHA 0 MAX1190 toc01a 0 FFT PLOT CHB (8192-POINT RECORD, DIFFERENTIAL INPUT) MAX1190 toc02a FFT PLOT CHA (8192-POINT RECORD, DIFFERENTIAL INPUT) AMPLITUDE (dB) MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs 50 0 20 40 60 80 100 ANALOG INPUT FREQUENCY (MHz) 120 0 20 40 60 80 100 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 120 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY -56 CHA -64 64 CHA 56 CHB -72 48 -80 40 20 40 60 80 100 80 THD 60 SNR 40 SINAD 20 fINA/B = 20.02536MHz 0 20 0 120 SFDR 40 60 80 100 120 40 44 48 52 56 60 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) CLOCK DUTY CYCLE (%) FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY SIGNAL-TO-NOISE RATIO vs. INPUT POWER (fIN = 20.02536MHz) 2 60 4 MAX1190 toc12 6 MAX1190 toc10 5 MAX1190 toc11 0 100 MAX1190 toc09 MAX1190 toc08 CHB 72 SFDR (dBc) -48 THD (dBc) 80 MAX1190 toc07 -40 SNR/SINAD, THD/SFDR vs. CLOCK DUTY CYCLE SNR/SINAD, THD/SFDR (dB, dBc) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY 56 -4 SNR (dB) -1 GAIN (dB) GAIN (dB) 2 0 -2 52 48 -4 -7 44 -6 -10 1 10 1000 100 40 10 1 100 -20 1000 -16 -12 -8 -4 0 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) INPUT POWER (dB FS) SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (fIN = 20.02536MHz) TOTAL HARMONIC DISTORTION vs. INPUT POWER (fIN = 20.02536MHz) SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (fIN = 20.02536MHz) THD (dBc) 52 48 44 -62 -68 -16 -12 -8 INPUT POWER (dB FS) -4 0 68 62 50 -80 -20 74 56 -74 40 MAX1190 toc15 -56 SFDR (dBc) 56 80 MAX1190 toc14 -50 MAX1190 toc13 60 SINAD (dB) VIN = 100mVP-P -8 -20 -16 -12 -8 INPUT POWER (dB FS) -4 0 -20 -16 -12 -8 -4 0 INPUT POWER (dB FS) _______________________________________________________________________________________ 7 MAX1190 Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dB FS, fCLK = 120MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3.3V, OVDD = 2.5V, VREFIN = 2.048V, differential input at -0.5dB FS, fCLK = 120MHz, CL ≈ 10pF, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE MAX1190 toc18 0.5 MAX1190 toc17 0.3 MAX1190 toc16 0.6 GAIN ERROR (%FS) 0.3 0.2 INL (LSB) DNL (LSB) 0.1 -0.2 -0.1 CHB 0.1 -0.1 CHA -0.6 -0.3 341 0 682 1023 -0.3 0 341 1023 682 10 35 TEMPERATURE (°C) OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE ANALOG SUPPLY CURRENT vs. TEMPERATURE DIGITAL SUPPLY CURRENT vs. ANALOG INPUT FREQUENCY 170 25 -0.2 CHA -1.2 20 IOVDD (mA) IVDD (mA) 160 150 10 35 10 130 5 85 60 0 -40 -15 TEMPERATURE (°C) 10 35 85 60 0 TEMPERATURE (°C) 2.035 MAX1190 toc23 2.034 12 18 24 30 36 42 48 54 60 INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAx1190 toc22 2.038 6 ANALOG INPUT FREQUENCY (MHz) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 2.030 VREFOUT (V) 2.030 VREFOUT (V) 15 140 120 -15 2.026 2.022 2.018 2.025 2.020 2.014 2.010 2.015 -40 -15 10 35 TEMPERATURE (°C) 60 85 MAX1190 toc21 30 MAX1190 toc20 180 MAX1190 toc19 CHB -0.7 8 60 DIGITAL OUTPUT CODE 0.3 -40 -15 -40 DIGITAL OUTPUT CODE 0.8 OFFSET ERROR (%FS) MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs 85 2.70 2.85 3.00 3.15 3.30 3.45 VDD (V) _______________________________________________________________________________________ 3.60 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs PIN NAME FUNCTION 1 COM Common-Mode Voltage I/O. Bypass to GND with a ≥0.1µF capacitor. 2, 6, 11, 14, 15 VDD Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel with 0.1µF. 3, 7, 10, 13, 16 GND Analog Ground 4 INA+ Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+. 5 INA- Channel A Negative Analog Input. For single-ended operation, connect INA- to COM. 8 INB- Channel B Negative Analog Input. For single-ended operation, connect INB- to COM. 9 INB+ Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+. 12 CLK Converter Clock Input 17 T/B T/B selects the ADC Digital Output Format: High: Two’s complement Low: Straight offset binary 18 SLEEP 19 PD High-Active Power-Down Input: High: Power-down mode Low: Normal operation 20 OE Low-Active Output Enable Input: High: Digital outputs disabled Low: Digital outputs enabled 21 D9B Three-State Digital Output, Bit 9 (MSB), Channel B 22 D8B Three-State Digital Output, Bit 8, Channel B 23 D7B Three-State Digital Output, Bit 7, Channel B 24 D6B Three-State Digital Output, Bit 6, Channel B 25 D5B Three-State Digital Output, Bit 5, Channel B 26 D4B Three-State Digital Output, Bit 4, Channel B 27 D3B Three-State Digital Output, Bit 3, Channel B 28 D2B Three-State Digital Output, Bit 2, Channel B 29 D1B Three-State Digital Output, Bit 1, Channel B Three-State Digital Output, Bit 0, Channel B Sleep-Mode Input: High: Disables both quantizers, but leaves the reference bias circuit active Low: Normal operation 30 D0B 31, 34 OGND Output Driver Ground 32, 33 OVDD Output Driver Supply Voltage. Bypass to OGND with a capacitor combination of 2.2µF in parallel with 0.1µF. 35 D0A Three-State Digital Output, Bit 0, Channel A 36 D1A Three-State Digital Output, Bit 1, Channel A 37 D2A Three-State Digital Output, Bit 2, Channel A 38 D3A Three-State Digital Output, Bit 3, Channel A 39 D4A Three-State Digital Output, Bit 4, Channel A _______________________________________________________________________________________ 9 MAX1190 Pin Description Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1190 Pin Description (continued) PIN NAME 40 D5A Three-State Digital Output, Bit 5, Channel A FUNCTION 41 D6A Three-State Digital Output, Bit 6, Channel A 42 D7A Three-State Digital Output, Bit 7, Channel A 43 D8A Three-State Digital Output, Bit 8, Channel A 44 D9A Three-State Digital Output, Bit 9 (MSB), Channel A 45 REFOUT 46 REFIN Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. 47 REFP Positive Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. 48 REFN Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass to GND with a >0.1µF capacitor. Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider. Detailed Description The MAX1190 uses a nine-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by 2, and the residues are passed along to the next pipeline stages, where the process is repeated until the signals have been processed by all nine stages. Input Track-and-Hold Circuits Figure 2 displays a simplified functional diagram of the input T/H circuits in both track and hold mode. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. 2-BIT FLASH ADC STAGE 1 STAGE 2 STAGE 8 2-BIT FLASH ADC STAGE 9 STAGE 1 DIGITAL ALIGNMENT LOGIC T/H VINA 10 D9A–D0A STAGE 2 STAGE 8 DIGITAL ALIGNMENT LOGIC T/H VINB 10 D9B–D0B VINA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED) VINB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED) Figure 1. Pipelined Architecture—Stage Blocks 10 ______________________________________________________________________________________ STAGE 9 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1190 INTERNAL BIAS COM S5a S2a C1a S3a S4a INA+ OUT C2a S4c S1 OUT INAS4b C2b C1b S3b S5b S2b COM INTERNAL BIAS HOLD INTERNAL BIAS TRACK COM CLK HOLD TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a INB+ OUT C2a S4c S1 OUT INBS4b MAX1190 C2b C1b S3b S2b INTERNAL BIAS S5b COM Figure 2. MAX1190 T/H Amplifiers These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1190 to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+, INA- and INB-) can be driven either differentially or single ended. Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance. ______________________________________________________________________________________ 11 MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs Analog Inputs and Reference Configurations these nodes become high-impedance inputs and can be driven through separate, external reference sources. The full-scale range of the MAX1190 is determined by the internally generated voltage difference between REFP (VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The fullscale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section. The MAX1190 provides three modes of reference operation: • Internal reference mode The MAX1190’s CLK input accepts a CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: Clock Input (CLK) • Buffered external reference mode • Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 10kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REFIN with a >10nF capacitor to GND. In internal reference mode, REFOUT, COM, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode, COM, REFP, and REFN are outputs. REFOUT can be left open or connected to REFIN through a >10kΩ resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP, COM, and REFN. With their buffers shut down, 1 SNR = 20 × log 2 × π × f IN × t AJ where fIN represents the analog input frequency and tAJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. The MAX1190 clock input operates with a voltage threshold set to VDD/2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low periods as stated in the Electrical Characteristics. 5-CLOCK-CYCLE LATENCY N N+1 N+2 N+3 N+4 N+5 N+6 ANALOG INPUT tAD CLOCK INPUT tCH tDO tCL DATA OUTPUT D9A–D0A N-6 N-5 N-4 N-3 N-2 N-1 N N+1 DATA OUTPUT D9B–D0B N-6 N-5 N-4 N-3 N-2 N-1 N N+1 Figure 3. System Timing Diagram 12 ______________________________________________________________________________________ Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs Digital Output Data (D0A/B–D9A/B), Output Data Format Selection (T/B), Output Enable (OE) All digital outputs, D0A–D9A (channel A) and D0B–D9B (channel B), are TTL/CMOS-logic compatible. There is a five-clock-cycle latency between any particular sample and its corresponding output data. The output coding can be chosen to be either straight offset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding. The capacitive load on digital outputs D0A–D9A and D0B–D9B should be kept as low as possible (<15pF) to avoid large digital currents that could feed back into the analog portion of the MAX1190, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1190, small series resistors (e.g., 100Ω) can be added to the digital output paths, close to the MAX1190. Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wakeup and data output valid. MAX1190 System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1190 samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 3 also determines the relationship between the input clock parameters and the valid output data on channels A and B. OE tENABLE OUTPUT D9A–D0A HIGH-Z OUTPUT D9B–D0B HIGH-Z tDISABLE VALID DATA VALID DATA HIGH-Z HIGH-Z Figure 4. Output Timing Diagram (both ADCs are disabled), and current consumption is reduced to 3mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state. Applications Information Figure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a VDD/2 output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed operational amplifiers. The user can select the RISO and CIN values to optimize the filter performance to suit a particular application. For the application in Figure 5, a RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF CIN capacitor acts as a small filter capacitor. Power-Down (PD) and Sleep (SLEEP) Modes The MAX1190 offers two power-save modes—sleep mode and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active Table 1. MAX1190 Output Codes For Differential Inputs DIFFERENTIAL INPUT VOLTAGE* DIFFERENTIAL INPUT STRAIGHT OFFSET BINARY T/B = 0 TWO’S COMPLEMENT T/B = 1 VREF × 512/512 +FULL SCALE - 1LSB 11 1111 1111 01 1111 1111 VREF × 1/512 +1LSB 10 0000 0001 00 0000 0001 0 Bipolar Zero 10 0000 0000 00 0000 0000 -VREF × 1/512 -1LSB 01 1111 1111 11 1111 1111 -VREF × 511/512 -FULL SCALE + 1LSB 00 0000 0001 10 0000 0001 -VREF × 512/512 -FULL SCALE 00 0000 0000 10 0000 0000 *VREF = VREFP - VREFN ______________________________________________________________________________________ 13 MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs +5V 0.1µF LOWPASS FILTER INA- MAX4108 300Ω RIS0 50Ω 0.1µF CIN 22pF 0.1µF -5V 600Ω 600Ω 300Ω +5V COM 0.1µF +5V 0.1µF 600Ω INPUT 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INA+ MAX4108 RIS0 50Ω 300Ω CIN 22pF 0.1µF -5V 300Ω 300Ω +5V 600Ω MAX1190 0.1µF LOWPASS FILTER INB- MAX4108 300Ω RIS0 50Ω 0.1µF 0.1µF -5V +5V CIN 22pF 600Ω 600Ω 300Ω 0.1µF +5V 0.1µF INPUT 600Ω 0.1µF LOWPASS FILTER MAX4108 300Ω -5V 0.1µF INB+ MAX4108 RIS0 50Ω 300Ω -5V CIN 22pF 0.1µF 300Ω 300Ω 600Ω Figure 5. Typical Application for Single-Ended to Differential Conversion 14 ______________________________________________________________________________________ Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1190 25Ω INA+ 22pF 0.1µF 1 VIN N.C. T1 6 5 2 3 4 COM 2.2µF 0.1µF MINICIRCUITS TT1–6-KK81 25Ω INA22pF MAX1190 25Ω INB+ 22pF 0.1µF 1 VIN N.C. T1 6 2 5 3 4 2.2µF 0.1µF MINICIRCUITS TT1-6-KK81 25Ω INB22pF Figure 6. Transformer-Coupled Input Drive Using Transformer Coupling Single-Ended AC-Coupled Input Signal An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the MAX1190 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD/2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX4108 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. In general, the MAX1190 provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. Buffered External Reference Drives Multiple ADCs Multiple-converter systems based on the MAX1190 are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source. A precision bandgap reference like the MAX6062 generates an external DC level of 2.048V (Figure 8), and exhibits a noise voltage density of 150nV/√Hz. Its output passes through a 1-pole lowpass filter (with 10Hz cutoff frequency) to the MAX4250, which buffers the reference before its output is applied to a second 10Hz lowpass filter. The MAX4250 provides a low offset voltage (for ______________________________________________________________________________________ 15 MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs REFP VIN 0.1µF 1kΩ RISO 50Ω INA+ MAX4108 100Ω CIN 22pF 1kΩ COM REFN 0.1µF RISO 50Ω INA- 100Ω CIN 22pF REFP VIN 0.1µF MAX1190 1kΩ RISO 50Ω INB+ MAX4108 100Ω CIN 22pF 1kΩ REFN 0.1µF RISO 50Ω INB- 100Ω CIN 22pF Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive high-gain accuracy) and a low noise level. The passive 10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision-ADC operation. Unbuffered External Reference Drives Multiple ADCs Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider, the MAX6066 generates a DC level of 2.500V. The buffered outputs of this divider are set to 2.0V, 1.5V, and 1.0V, with an accuracy that depends on the tolerance of the divider resistors (Figure 9). 16 Those three voltages are buffered by the MAX4252, which provides low noise and low DC offset. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nV/√Hz. The 2.0V and 1.0V reference voltages set the differential full-scale range of the associated ADCs at 2VP-P. The 2.0V and 1.0V buffers drive the ADCs’ internal ladder resistances between them. Note that the common power supply for all active components removes any concern regarding powersupply sequencing when powering up or down. With the outputs of the MAX4252 matching better than 0.1%, the buffers and subsequent lowpass filters can be replicated to support as many as 32 ADCs. For applications that require more than 32 matched ADCs, a voltage reference and divider string common to all converters is highly recommended. ______________________________________________________________________________________ Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs MAX1190 3.3V 3.3V 0.1µF 2.048V 0.1µF N.C. 31 1 32 0.1µF MAX6062 2 16.2kΩ 3 1 2 162Ω 4 10Hz LOWPASS FILTER 1 5 MAX4250 1µF 3 29 REFOUT REFIN REFP REFN COM N=1 MAX1190 100µF 2 0.1µF 0.1µF 0.1µF 10Hz LOWPASS FILTER NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs. 0.1µF N.C. 29 31 32 0.1µF 1 2 2.2µF 10V REFOUT REFIN REFP N = 1000 REFN MAX1190 COM 0.1µF 0.1µF 0.1µF Figure 8. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference Typical QAM Demodulation Application A frequently used modulation technique in digital communications applications is quadrature amplitude modulation (QAM). Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90° phase shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 10 displays the demodulation process performed in the analog domain, using the dualmatched 3.3V, 10-bit ADC MAX1190 and the MAX2451 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the MAX1190, the mixed-down signal components can be filtered by matched analog filters, such as Nyquist or pulse-shaping filters, which remove unwanted images from the mixing process, thereby enhancing the overall SNR performance and minimizing intersymbol interference. Grounding, Bypassing, and Board Layout The MAX1190 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass VDD, REFP, REFN, and COM with two parallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OVDD) to OGND. Multilayer boards with separated ground and power planes produce the ______________________________________________________________________________________ 17 MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs 3.3V 0.1µF N.C. 29 31 1 2.0V 2 MAX6066 3 4 REFP 1 REFN 2.0V AT 8mA 1/4 MAX4252 1 47Ω 2 2 3 10µF 6V 1.47kΩ 11 21.5kΩ 1.5V REFIN 32 3.3V 21.5kΩ REFOUT N=1 MAX1190 COM 330µF 6V 0.1µF 0.1µF 0.1µF 3.3V 5 4 1.5V AT 0mA 1/4 MAX4252 7 47Ω 6 1µF 10µF 6V 1.47kΩ 11 21.5kΩ 3.3V 1.0V 0.1µF 21.5kΩ 0.1µF 2.2µF 10V 3.3V 10 4 1.0V AT -8mA 1/4 MAX4252 8 MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP. 330µF 6V 47Ω 9 11 21.5kΩ 10µF 6V 1.47kΩ 330µF 6V 29 N.C. 31 32 1 2 REFOUT REFIN REFP N = 32 REFN MAX1190 COM 0.1µF 0.1µF 0.1µF NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs. Figure 9. External Unbuffered Reference Drive with MAX4252 and MAX6066 MAX2451 INA+ INA0° 90° MAX1190 INB+ INB- DOWNCONVERTER ÷8 Figure 10. Typical QAM Application Using the MAX1190 18 ______________________________________________________________________________________ DSP POSTPROCESSING Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1190 are measured using the best-straight-line fit method. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Dynamic Parameter Definitions Aperture Jitter Figure 11 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 11). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNRdB[max] = 6.02dB ✕ N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: CLK SINAD − 1.76 ENOB = 6.02 ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) T/H TRACK HOLD TRACK Figure 11. T/H Aperture Timing ______________________________________________________________________________________ 19 MAX1190 highest level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC’s package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90° turns. MAX1190 Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs Total Harmonic Distortion (THD) Intermodulation Distortion (IMD) THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels are at -6.5dB full scale and their envelope is at -0.5dB full scale. V2 2 + V3 2 + V4 2 + V5 2 THD = 20 × log V1 Chip Information where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. TRANSISTOR COUNT: 10,811 PROCESS: CMOS Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Functional Diagram VDD OGND OVDD GND INA+ 10 ADC T/H DEC OUTPUT DRIVERS 10 D9A–D0A INA- CONTROL CLK OE INB+ 10 T/H ADC DEC OUTPUT DRIVERS 10 D9B–D0B INB- REFERENCE MAX1190 REFOUT REFN COM REFP 20 REFIN ______________________________________________________________________________________ T/B PD SLEEP Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs 48L,TQFP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1190 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)