ONSEMI NB3N3001DTG

NB3N3001
3.3 V 106.25 MHz/ 212.5 MHz
PureEdge Clock Generator with
LVPECL Differential Output
Description
The NB3N3001 is a low−jitter, dual−rate PLL−synthesized clock
generator. It accepts a standard 26.5625 MHz fundamental mode AT cut
parallel resonant crystal as the reference source for its integrated crystal
oscillator and low noise phase−locked loop (PLL) and produces user
selectable clock frequencies of either 106.25 MHz or 212.5 MHz.
In addition, the PLL circuitry will generate a 50% duty cycle
square−wave through a pair of differential LVPECL clock outputs.
Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to
10 MHz.
The LVPECL output drivers can be disabled to high impedance with
the OE pin set LOW. The NB3N3001 operates from a single +3.3 V
supply, and is available in both plastic package and die form. The
operating temperature range is from −40°C to +85°C.
The NB3N3001 device provides the optimum combination of low
cost, flexibility, and high performance which makes it ideal for
Fibre−Channel applications.
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MARKING
DIAGRAM
301
YWW
AG
TSSOP−8
DT SUFFIX
CASE 948S
A
Y
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Features
•
•
•
•
•
•
•
•
•
•
•
•
PureEdge Clock Family Provides Accuracy and Precision
Selectable Output Frequency of 106.25 MHz or 212.5 MHz
Crystal Oscillator Interface Designed for a 26.5625 MHz Crystal
Fully Integrated Phase−Lock−Loop with Internal Loop Filter
Differential 3.3 V LVPECL Outputs
Exceeds Bellcore and ITU Jitter Generation Specification
RMS Phase Jitter @ 106.25 MHz, using a 26.5625 MHz Crystal
(637 kHz − 10 MHz): 0.3 ps (Typical)
RMS Phase Noise at 106.25 MHz
Phase Noise:
Offset Noise Power
100 Hz −108 dBc/Hz
1 kHz −122 dBc/Hz
10 kHz −135 dBc/Hz
100 kHz −135 dBc/Hz
Operating Range: VCC = 3.135 V to 3.465 V
−40°C to +85°C Ambient Operating Temperature
Small Footprint 8−pin TSSOP Package
This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
FSEL
XIN
Crystal
Oscillator
26.5625 MHz
Q
Phase
Detector
Charge
Pump
VCO
850 MHz
XOUT
N =B8
orB4
LVPECL
Output
212.5 MHz
or
Q 106.25 MHz
M = B32
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 1
1
Publication Order Number:
NB3N3001/D
NB3N3001
VCCA
1
8
VCC
Table 1. Output Frequency Select
VEE
2
7
Q
6
Q
NB3N3001
XOUT
XIN
3
4
5
FSEL
Output Frequency (MHz)
0
106.25
1
212.5
NOTE: Input crystal = 26.5625 MHz
FSEL
Figure 2. Pinout (Top View)
Table 2. PIN DESCRIPTION
Pin
Symbol
Type
Description
1
VCCA
Power
Positive analog power supply pin. Connected to VCC with filter components (See Figure 8).
2
VEE
Power
Negative supply pin.
3
XOUT
Input
Crystal input (OUT).
4
XIN
Input
Crystal input (IN).
5
FSEL
6
Q
Output
Inverted differential output. Typically terminated with 50 to VCC−2.0 V.
7
Q
Output
Noninverted differential output. Typically terminated with 50 to VCC−2.0 V.
8
VCC
Power
Positive digital core power supply pin. Connected to 3.3 V.
LVTTL/LVCMOS
Input
Frequency select pin. Defaults LOW when left open. Internal pull down resistor to VEE.
Table 3. ATTRIBUTES
Characteristic
Value
ESD Protection
Moisture Sensitivity (Note 1)
Human Body Model
Machine Model
> 6 kV
> 200 V
Pb−Free Pkg, TSSOP−8
Level 3
Flammability Rating Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
4150
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
VCC
Supply Voltage
VI
Inputs
IO
Output Current
JA
Thermal Resistance (Junction−to−Ambient)
TSTG
Storage Temperature
Value
Unit
4.6
V
−0.5 to VCC + 0.5
V
Continuous
Surge
50
100
mA
0 Lfpm
500 Lfpm
142
103
°C/W
−65 to 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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NB3N3001
Table 5. POWER SUPPLY DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C)
Symbol
Min
Typ
Max
Unit
VCC
Core Supply Voltage
Parameter
Conditions
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
ICCA
Analog Supply Current
19
23
mA
IEE
Power Supply Current
27
31
mA
Included in IEE
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 6. LVPECL DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOH
Output High Voltage (Note 2)
VCC − 1.4
VCC − 0.9
V
VOL
Output Low Voltage (Note 2)
VCC − 2.0
VCC − 1.7
V
VSWING
Peak−to−Peak Output Voltage Swing
1.0
V
0.6
0.75
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Outputs terminated with 50 to VCC − 2.0 V. See Figures 4 and 12.
Table 7. LVTTL/LVCMOS DC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C)
Symbol
Parameter
Conditions
Min
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
FSEL
VCC = VIN = 3.465 V
IIL
Input Low Current
FSEL
VCC = 3.465 V, VIN = 0 V
−5.0
Conditions
Min
Typ
2.0
−0.3
Max
Unit
VCC + 0.3
V
0.8
V
150
A
A
Table 8. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
RPD
Input Pull Down Resistor
Typ
Max
Unit
4
pF
100
k
Table 9. CRYSTAL CHARACTERISTICS (Fundamental Mode 18 pF Parallel Resonant Crystal)
Parameter
Conditions
Frequency
Min
Typ
Max
26.5625
Unit
MHz
Equivalent Series Resistance (ESR)
50
Shunt Capacitance
7.0
pF
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NB3N3001
Table 10. AC CHARACTERISTICS, (VCC = 3.3 V ±5%, TA = −40°C to 85°C (Note 4))
Symbol
Parameter
Conditions
fOUT
Output Frequency
24 MHz − 30 MHz Crystal
(Typ. 25 MHz − 26.5625 MHz)
tjit(∅)
RMS Phase Jitter (Random)
(Note 3)
Min
Typ
Max
Unit
106.25/
212.5
MHz
106.25 MHz; Integration Range:
637 kHz −10 MHz
0.3
ps
212.5 MHz; Integration Range:
637 kHz −10 MHz
0.3
tR/tF
Output Rise/Fall Time
20% to 80% (See Figure 7)
275
600
ps
odc
Output Duty Cycle
(See Figure 6)
48
52
%
NOISE POWER (dBc)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Please refer to the Phase Noise Plot.
4. Output terminated with 50 to VCC− 2.0 V. See Figures 4 and 12.
OFFSET FREQUENCY (Hz)
Figure 3. Typical Phase Noise at 106.25 MHz
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NB3N3001
PARAMETER MEASUREMENT INFORMATION
2V
Z = 50 Q
VCC
Noise Power
Phase Noise Plot
SCOPE
50 LVPECL
Z = 50 Phase Noise Mask
Q
VEE
50 Offset Frequency
f1
−1.3 V " 0.165 V
f2
RMS + ǸArea Under the Masked Phase Noise Plot
Figure 4. Output Load AC Test Circuit
(Split Power Supply)
Figure 5. RMS Phase Jitter
Q
80%
Q
80%
VSWING
Clock
Outputs
Q
Pulse Width
20%
20%
Q
tPERIOD
odc +
tR
tPW
tF
tPERIOD
Figure 6. Output Duty Cycle/Pulse Width/Period
Figure 7. Output Rise/Fall Time
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NB3N3001
APPLICATION INFORMATION
Power Supply Filtering
Figure 9 illustrates a parallel resonant crystal with its
associated load capacitors. The capacitor values shown were
determined using a 26.5625 MHz, 18 pF parallel resonant
crystal and were chosen to minimize the ppm error.
Capacitor values can be adjusted slightly for different board
layouts to optimize accuracy.
The NB3N3001 is a mixed analog/digital product, and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NB3N3001 also
generates sub−nanosecond output edge rates, and therefore,
a good power supply bypassing scheme is a must.
The NB3N3001 provides separate power supplies for the
digital circuitry (VCC) and the internal PLL (VCCA). The
simplest form of noise isolation is a power supply filter on
the VCCA pin.
Figure 8 illustrates a typical power supply filter scheme.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
The purpose of this design technique is to try and isolate
the high switching noise of the digital outputs from the
relatively sensitive internal analog phase−locked loop. The
power supply filter and bypass schemes discussed in this
section should be adequate to eliminate power supply
noise−related problems in most designs.
3.3 V
VCC
0.01 F
10 VCCA
0.01 F
10 F
Figure 8. Power Supply Filtering
XOUT
C1
33 pF
X1
Crystal Oscillator Input Interface
18 pF Parallel Crystal
The NB3N3001 features an integrated crystal oscillator to
minimize system implementation costs. The oscillator
circuit is a parallel resonant circuit and thus, for optimum
performance, a parallel resonant crystal should be used.
As the oscillator is somewhat sensitive to loading on its
inputs, the user is advised to mount the crystal as close to the
NB3N3001 as possible to avoid any board level parasitics.
Surface mount crystals are recommended, but not required.
XIN
C2
27 pF
Figure 9. Crystal Input Interface
APPLICATION SCHEMATIC
Figure 10 shows a schematic example of the NB3N3001.
An example of LVPECL termination is shown in this
schematic. Additional LVPECL termination approaches are
shown in the AND8020 Application Note. In this example,
an 18 pF parallel resonant 26.5625MHz crystal is used for
generating 106.25 MHz output frequency. The C1 = 27 pF
and C2 = 33 pF are recommended for frequency accuracy.
For different board layout, the C1 and C2 values may be
slightly adjusted for optimizing frequency accuracy.
VCC
VCC
VCCA
R2
10
C2
33 pF
C3
10 F
18 pF
VCC
0.01 F
X1
C1
27 pF
R3
ZO = 50 133
U1
C4
1
VCCA
2 V
EE
3 X
OUT
4
XIN
8
VCC
7
Q
Q 6
FSEL 5
Q
+
Q
ZO = 50 C5
0.1 VCC = 3.3 V
Figure 10. Typical Application Schematic
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R5
133
−
R4
82.5
R6
82.5
NB3N3001
PC Board Layout Example
Table 11. Footprint Table
Figure 11 shows a representative board layout for the
NB3N3001. There exists many different potential board
layouts and the one pictured is but one. The crystal X1
footprint shown in this example allows installation of either
surface mount HC49S or through−hole HC49 package. The
footprints of other components in this example are listed in
Table 11. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located
as close as possible to the power pins. The layout assumes
that the board has clean analog power ground plane. The
important aspect of the layout in Figure 11 is the low
impedance connections between VCC and GND for the
bypass capacitors. Combining good quality general purpose
chip capacitors with good PCB layout techniques will
produce effective capacitor resonances at frequencies
adequate to supply the instantaneous switching current for
the NB3N3001 outputs. It is imperative that low inductance
chip capacitors are used. It is equally important that the
board layout not introduce any of the inductance saved by
using the leadless capacitors. Thin interconnect traces
between the capacitor and the power plane should be
avoided and multiple large vias should be used to tie the
capacitors to the buried power planes. Fat interconnect and
large vias will help to minimize layout induced inductance
and thus maximize the series resonant point of the bypass
capacitors.
The voltage amplitude across the crystal is relatively
small. It is imperative that no actively switching signals
cross under the crystal as crosstalk energy coupled to these
lines could significantly impact the jitter of the device.
Q
Reference
Size
C1, C2
0402
C3
0805
C4, C5
0603
R2
0603
C2
C1
Figure 11. PC Board Layout
Zo = 50 D
Receiver
Device
Driver
Device
Q
Zo = 50 D
50 50 VTT
VTT = VCC − 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
NB3N3001DTG
TSSOP8 4.4 mm
(Pb−Free)
100 Units / Rail
NB3N3001DTR2G
TSSOP8 4.4 mm
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB3N3001
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE B
8x
0.20 (0.008) T U
K REF
0.10 (0.004)
S
2X
L/2
8
B
−U−
1
S
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
J J1
4
PIN 1
IDENT
S
T U
5
L
0.20 (0.008) T U
M
K1
K
A
−V−
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
DETAIL E
G
PLANE
P
0.25 (0.010)
N
M
N
P1
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
P
P1
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
−−−
1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
−−−
2.20
−−−
3.20
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
−−− 0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
−−− 0.087
−−− 0.126
F
DETAIL E
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NB3N3001/D