NB3N2304NZ D

NB3N2304NZ
3.3V 1:4 Clock Fanout
Buffer
Description
The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer,
designed for high speed clock distribution such as in PCI−X
applications. The NB3N2304NZ guarantees low output−to−output
skew. Optimal design, layout and processing minimizes skew within a
device and from device−to−device.
The Output Enable (OE) pin forces the outputs LOW when LOW.
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MARKING
DIAGRAM*
40N
YWW
AG
Features
Input/Output Clock Frequency up to 140 MHz
Low Skew Outputs (100 ps)
Output Enable
Operating Range: VDD = 3.0 V to 3.6 V
Ideal for PCI−X and networking clocks
Packaged in 8−pin TSSOP, 4.4 mm x 3 mm
Industrial Temperature Range
These are Pb−Free Devices*
TSSOP−8
DT SUFFIX
CASE 948S
6O M
•
•
•
•
•
•
•
•
1
DFN8
MN SUFFIX
CASE 506AA
A
Y
WW
M
G
1
4
= Assembly Location
= Year
= Work Week
= Date Code
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 6
1
Publication Order Number:
NB3N2304NZ/D
NB3N2304NZ
Logic
Control
OE
IN
1
8
Q4
OE
2
7
Q3
Q1
3
6
VDD
GND
4
5
Q2
Q1
Q2
IN
Q3
Q4
Figure 3. NB3N2304NZ Package Pinout (Top View)
Figure 2. Block Diagram
Table 1. PIN DESCRIPTION
Pin #
Pin
Name
Type
1
IN
LVCMOS/LVTTL Input
Clock Input
2
OE
LVCMOS/LVTTL Input
Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs
are forced to logic LOW when OE is forced LOW.
3
Q1
LVCMOS/LVTTL Output
4
GND
Power
5
Q2
(LV)CMOS/(LV)TTL Input
6
VDD
Power
7
Q3
(LV)CMOS/(LV)TTL Output
Clock Output 3
8
Q4
(LV)CMOS/(LV)TTL Input
Clock Output 4
−
EP
Thermal Exposed Pad
Description
Clock Output 1
Negative Supply Voltage; Connect to Ground, 0 V
Clock Output 2
Positive Supply Voltage (3.0 V to 3.6 V)
(DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit.
Electrically connect to the most negative supply (GND) or leave unconnected, floating
open.
Table 2. OE, OUTPUT ENABLE FUNCTION TABLE
Inputs
Outputs
IN
OE
L
L
L
H
L
L
L
H
L
H
H
H
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2
NB3N2304NZ
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
> 2kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−8
DFN−8
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
UL 94 V−O @ 0.125 in
480 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
GND = 0 V
Rating
Unit
VDD + 0.5V
V
VDD
Positive Power Supply
VI
Input Voltage
GND – 0.5 v
VI v VDD + 0.5
V
TA
Operating Temperature Range, Industrial
w −40 to v +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
0 lfpm
500 lfpm
143
103
129
84
°C/W
TSOL
Wave Solder
(Note 2)
265
°C
qJC
Thermal Resistance (Junction−to−Case)
35 to 40
°C/W
Pb−Free
(Note 2)
TSSOP−8
TSSOP−8
DFN−8
DFN−8
DFN8
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
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NB3N2304NZ
Table 5. DC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
Symbol
Characteristic
Min
Typ
Max
Unit
12
25
mA
IDD
Power Supply Current @ 66.66 MHz, Unloaded Outputs
VOH
Output HIGH Voltage
− IOH = −24 mA
−IOH = −12 mA
VOL
Output LOW Voltage
−IOL = 24 mA
−IOL = 12 mA
VIH
Input HIGH Voltage, IN and OE (Note 3)
VIL
Input LOW Voltage, IN and OE (Note 3)
0.8
V
IIH
Input HIGH Current, VIN = VDD
−50
50
mA
IIL
Input LOW Current, VIN = 0 V
−100
100
mA
CIN
Input Capacitance, IN, OE
7
pF
2.0
2.4
V
0.8
0.55
2.0
V
V
5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. IN input has a threshold voltage of VDD/2.
Table 6. AC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 4) (Figure 4)
Symbol
Characteristic
Min
fin
Input Clock Frequency
DC
tDCskew
Duty Cycle Skew = t2 ÷ t1 (Figure 4) Measured at 1.5 V
40
tr/tf
Output Rise and Fall Times; 0.8 V to 2.0 V
tpd
Propagation Delay, IN−to−Qn (Note 5)
tskew
Output−to−Output Skew; (Note 5)
tpu
Powerup Time for VDD to Reach Minimum Specified Voltage
CL = 25 pF
CL = 10 pF
2.5
0.05
Typ
Max
Unit
140
MHz
50
60
%
0.9
0.6
1.5
ns
3.5
5
ns
100
ps
50
ms
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. All outputs loaded equally with CL = 25 pF to GND. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should be connected between
VDD and GND.
5. Measured on rising edges at VDD B 2; all outputs with equal loading.
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NB3N2304NZ
t1
Duty Cycle Timing
t2
1.5 V
1.5 V
1.5 V
All Outputs Rise/Fall Time
2.0 V
0.8 V
OUTPUT
2.0 V
0.8 V
tr
tf
3.3 V
0V
Output−Output Skew
1.5 V
OUTPUT
1.5 V
OUTPUT
tSKEW
Input−Output Propagation Delay
VDD/2
INPUT
VDD/2
OUTPUT
tpd
Figure 4. Switching Waveforms
ORDERING INFORMATION
Device
Package
Shipping†
NB3N2304NZDTG
TSSOP−8
(Pb−Free)
100 Units / Rail
NB3N2304NZDTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
NB3N2304NZMNR4G*
DFN8
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Contact a sales representative.
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5
NB3N2304NZ
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE C
8x
0.20 (0.008) T U
K REF
0.10 (0.004)
S
2X
L/2
8
0.20 (0.008) T U
T U
B
−U−
1
V
4
K1
K
SECTION N−N
−W−
C
0.076 (0.003)
D
−T− SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
J J1
A
−V−
S
S
ÉÉÉÉ
ÇÇÇ
ÉÉÉÉ
ÇÇÇ
5
L
PIN 1
IDENT
M
DETAIL E
G
0.25 (0.010)
N
M
N
F
DETAIL E
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6
DIM
A
B
C
D
F
G
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
4.30
4.50
--1.10
0.05
0.15
0.50
0.70
0.65 BSC
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.114
0.122
0.169
0.177
--0.043
0.002
0.006
0.020
0.028
0.026 BSC
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
NB3N2304NZ
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
2X
0.10 C
2X
TOP VIEW
0.10 C
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.20
−−−
0.25
0.35
A
0.10 C
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
0.08 C
(A3)
SIDE VIEW
A1
SEATING
PLANE
C
D2
e
e/2
4
1
8X
L
E2
K
8
5
8X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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NB3N2304NZ/D