ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output Member of the Applications • Low voltage, high density systems with Intermediate Bus Architectures (IBA) • Point-of-load regulators for high performance DSP, FPGA, ASIC, and microprocessor applications • Industrial computing, servers, and storage • Broadband, networking, optical, and wireless communications systems • Active memory bus terminators Benefits • Integrates digital power conversion with intelligent power management • Eliminates the need for external power management components and communication bus • Completely programmable via pin strapping and external R and C • One part that covers all applications • Reduces board space, system cost and complexity, and time to market Family Features • RoHS lead free and lead-solder-exempt products are available • Wide input voltage range: 3V–14V • High continuous output current: 15A • Wide programmable output voltage range: 0.5V–5.5V • Active digital current share • Output voltage margining • Overcurrent and overtemperature protections • Overvoltage and undervoltage protections, and Power Good signal tracking the output voltage setpoint • Programmable power-up delay • Tracking during turn-on and turn-off with guaranteed slew rates • Sequenced and cascaded modes of operation • Single-wire line for frequency synchronization between multiple POLs • Programmable interleave • Programmable feedback loop compensation • Enable control with programmable polarity • Flexible fault management and propagation • Start-up into the load pre-biased up to 100% • Full rated current sink • Real time current and temperature measurements, monitoring, and reporting • Small footprint SMT package: 16x32mm • Low profile of 8mm • Compatible with conventional pick-and-place equipment • Wide operating temperature range • UL60950 recognized, CSA C22.2 No. 60950-00 certified, and TUV EN60950-1:2001 certified Description The ZY1015 is an intelligent, fully programmable step-down point-of-load DC-DC module integrating digital power conversion and intelligent power management. The ZY1015 completely eliminates the need for external components for sequencing, tracking, protection, monitoring, and reporting. Performance parameters of the ZY1015 are programmable by pin strapping and external resistor and capacitor and can be changed by a user at any time during product development and service without a need for a communication bus. REV. 1.2 MAR 14, 2007 www.power-one.com Page 1 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output Reference Documents No-BusTM POL Converters. Z-1000 Series Application Note Z-One® POL Converters. Eutectic Solder Process Application Note Z-One® POL Converters. Lead-Free Process Application Note 1. Ordering Information ZY 10 Product family: Z-One Module Series: No-Bus POL Converter 15 Output Current: 15A y RoHS compliance: No suffix - RoHS compliant 1 with Pb solder exemption G - RoHS compliant for all six substances – Dash zz 2 Packaging Option : T1 – 500pcs T&R T2 – 100pcs T&R T3 – 50pcs T&R Q1 – 1pc sample for evaluation only K1 – 1pc mounted on the evaluation 3 board ______________________________________ 1 The solder exemption refers to all the restricted materials except lead in solder. These materials are Cadmium (Cd), Hexavalent chromium (Cr6+), Mercury (Hg), Polybrominated biphenyls (PBB), Polybrominated diphenylethers (PBDE), and Lead (Pb) used anywhere except in solder. 2 Packaging option is used only for ordering and not included in the part number printed on the POL converter label. 3 The evaluation board is available in only one configuration: ZY1015-K1. Example: ZY1015G-T3: A 50-piece reel of RoHS compliant POL converters. Each POL converter is labeled ZY1015G. 2. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect longterm reliability, and cause permanent damage to the POL converter. 3. Parameter Conditions/Description Min Max Units Operating Temperature Controller Case Temperature -40 105 °C Input Voltage 250ms Transient 15 VDC Output Current (See Output Current Derating Curves) 15 ADC -15 Environmental and Mechanical Specifications Parameter Conditions/Description Min Nom Max Units Ambient Temperature Range -40 85 °C Storage Temperature (Ts) -55 125 °C 15 grams Weight MTBF Calculated Per Telcordia Technologies SR-332 Peak Reflow Temperature ZY1015 Peak Reflow Temperature ZY1015G Lead Plating ZY1015 and ZY1015G 1.5µm Ag over 1.5µm Ni Moisture Sensitivity Level JEDEC J-STD-020C 3 REV. 1.2 MAR 14, 2007 www.power-one.com 4.82 MHrs 245 220 °C 260 °C Page 2 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 4. Electrical Specifications Specifications apply at the input voltage from 3V to 14V, output load from 0 to 15A, ambient temperature from 40°C to 85°C, output capacitance consisting of 110µF ceramic and 220µF tantalum, and default performance parameters settings unless otherwise noted. 4.1 4.2 Input Specifications Parameter Conditions/Description Min Input voltage (VIN) At VIN<4.75V, VLDO pin needs to be connected to an external voltage source higher than 4.75V Nom 3 Input Current (at no load) VIN≥4.75V, VLDO pin connected to VIN 50 mADC Undervoltage Lockout (VLDO connected to VIN) Ramping Up Ramping Down 4.00 3.9 VDC VDC Undervoltage Lockout (VLDO connected to VAUX=5V) Ramping Up Ramping Down 2.8 2.7 VDC VDC External Low Voltage Supply Connect to VLDO pin when VIN<4.75V VLDO Input Current Current drawn from the external low voltage supply at VLDO=5V 4.75 Max Units 14 VDC 14 50 VDC mADC Output Specifications Parameter Conditions/Description Output Current (IOUT) Min Nom 1 Max Units 15 ADC 5.5 VDC VIN MIN to VIN MAX -15 0.5 Output Voltage Setpoint Accuracy3 Programmable2 with a resistor between TRIM and REF pins Default (no resistor) VIN=12V, IOUT=0.5*IOUT MAX, room temperature 0.5 ±1.5% or 20mV whichever is greater Line Regulation3 VIN MIN to VIN MAX ±0.2 %VOUT Output Voltage Range (VOUT) Load Regulation 3 VDC %VOUT 0 to IOUT MAX ±0.2 %VOUT Dynamic Regulation Peak Deviation Peak Deviation Settling Time Output Voltage Peak-to-Peak Ripple and Noise BW=20MHz Full Load Slew rate 1A/µs, 50-75% load step, VIN≥5V VIN=3.3V to 10% of peak deviation VIN=5.0V, VOUT≤2.5V VIN=5.0V, VOUT>2.5V VIN=12V, VOUT≤2.5V VIN=12V, VOUT>2.5V 80 100 30 15 25 25 30 mV mV µs mV mV mV mV Temperature Coefficient VIN=12V, IOUT=0.5*IOUT MAX 100 ppm/°C Switching Frequency 450 500 550 1 kHz At the negative output current (bus terminator mode) efficiency of the ZY1015 degrades resulting in increased internal power dissipation. Therefore maximum allowable negative current under specific conditions is 20% lower than the current determined from the derating curves shown in paragraph 5.5. 2 ZY1015 is a step-down converter, thus the output voltage is always lower than the input voltage as show in Figure 1. 3 Digital PWM has an inherent quantization uncertainty of ±6.25mV that is not included in the specified static regulation parameters. REV. 1.2 MAR 14, 2007 www.power-one.com Page 3 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output VOUT [V] 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Min Load 0.2A 0.5 3.0 2.0 3.15 4.0 5.5 6.25 6.0 VIN [V] 8.0 10.0 12.0 14.0 Figure 1. Output Voltage as a Function of Input Voltage and Output Current 4.3 Protection Specifications Parameter Conditions/Description Min Nom Max Units Output Overcurrent Protection Type Non-Latching, 130ms period Threshold 170 Threshold Accuracy %IOUT -25 25 %IOCP.SET Output Overvoltage Protection Type Latching Threshold Follows the output voltage setpoint Threshold Accuracy Measured at VO.SET=2.5V Delay From instant when threshold is exceeded until the turn-off command is generated 1 130 -2 %VO.SET 2 %VOVP.SET 6 µs Output Undervoltage Protection Type Threshold Non-Latching, 130ms period Follows the output voltage setpoint Threshold Accuracy Measured at VO.SET=2.5V Delay From instant when threshold is exceeded until the turn-off command is generated REV. 1.2 MAR 14, 2007 www.power-one.com 75 -2 %VO.SET 2 %VUVP.SET 6 µs Page 4 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output Overtemperature Protection Type Non-Latching, 130ms period Turn Off Threshold Temperature is increasing 120 °C Turn On Threshold Temperature is decreasing after module was shut down by OTP 110 °C Threshold Accuracy Delay -5 From instant when threshold is exceeded until the turn-off command is generated °C 5 6 µs Power Good Signal (PGOOD pin) VOUT is inside the PG window and stable VOUT is outside of the PG window or ramping up/down High Follows the output voltage setpoint 90 %VO.SET Upper Threshold Follows the output voltage setpoint 110 %VO.SET Delay From instant when threshold is exceeded until status of PG signal changes 6 µs Threshold Accuracy Measured at VO.SET=2.5V Logic Lower Threshold N/A Low -2 2 %VO.SET ___________________ 1 Minimum OVP threshold is 1.0V 4.4 Feature Specifications Parameter Conditions/Description Min Nom Max Units Current Share (CS pin) Type Maximum Number of Modules Connected in Parallel Maximum Number of Modules Connected in Parallel Active, Single Line IOUT MIN≥20%*IOUT NOM 10 IOUT MIN=0 4 Current Share Accuracy IOUT MIN≥20%*IOUT NOM Interleave (Phase Lag) Programmable via INTL0…INTL4 pins in 11.25° steps (IM pin is open) Default (IM pin is pulled low) ±20 %IOUT 348.75 degree Interleave (IM and INTL0…INTL4 pins) 0 0 degree Sequencing (DELAY pin) Power-Up Delay Programmable by capacitor connected to DELAY pin Default: CDELAY=0 210 ms 0 ms Tracking Rising Slew Rate Proportional to SYNC frequency 0.1 V/ms Falling Slew Rate Proportional to SYNC frequency -0.5 V/ms REV. 1.2 MAR 14, 2007 www.power-one.com Page 5 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output Enable (EN and ENP pins) ENP pin is pulled low EN Pin Polarity ENP pin is open Negative (enables the output when EN pin is pulled low) Positive (enables the output when EN pin is open or pulled high) EN High Threshold 2.3 VDC EN Low Threshold Open Circuit Voltage Turn-On Delay Turn-Off Delay 1.0 EN and ENP From EN pin changing state to VOUT starting to ramp up From EN pin changing state to VOUT reaching 0V VDC 3.3 VDC 0 ms 11 ms Feedback Loop Compensation (CCA0…CCA2 pins) CCA=7 (default) CCA=6 CCA=5 CCA=3 or CCA=4 CCA=2 CCA=1 CCA=0 Recommended VIN range Recommended COUT/ESR range, combination of ceramic+ tantalum Recommended VIN range Recommended COUT range, tantalum Recommended ESR range, tantalum Recommended VIN range Recommended COUT/ESR range, ceramic Recommended VIN range Recommended COUT/ESR range, combination of ceramic + tantalum Recommended VIN range Recommended COUT/ESR range, tantalum Recommended VIN range Recommended COUT/ESR range, ceramic Recommended VIN range Recommended COUT/ESR range, combination of ceramic+ tantalum 8 50/5 + 220/40 8 440 40 8 100/5 3 50/5 + 220/40 3 100/25 3 100/5 6 50/5 + 220/40 12 100/5 + 470/40 12 880 25 12 220/5 5 100/5 + 470/40 5 440/20 5 220/5 100/5 + 470/40 14 400/5 + 2000/20 14 10,000 10 14 400/5 5.5 200/5 + 880/40 5.5 1,000/10 5.5 400/5 11 200/5 + 880/40 VDC µF/mΩ µF/mΩ VDC µF mΩ VDC µF/mΩ VDC µF/mΩ µF/mΩ VDC µF/mΩ VDC µF/mΩ VDC µF/mΩ µF/mΩ +20 %IOUT Output Current Monitoring (CS pin) Output Current Monitoring Accuracy Conversion Ratio 20%*IOUT NOM < IOUT < IOUT NOM VIN=12V Duty Cycle of the negative pulse corresponding to 100% of nominal current -20 65 % Temperature Monitoring (TEMP pin) Temperature Monitoring Accuracy Junction temperature of POL controller Conversion Ratio Junction temperature from -40°C to 140°C Monitoring Voltage Range Corresponds to -40°C to 140°C junction temperature range Output Impedance TEMP pin -5 +5 10 0.2 °C mV/°C 2 6.4 VDC kΩ Remote Voltage Sense (-VS and +VS pins) Type Differential Voltage Drop Compensation Between +VS and VOUT 300 mV Voltage Drop Compensation Between -VS and PGND 100 mV REV. 1.2 MAR 14, 2007 www.power-one.com Page 6 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 4.5 Signal Specifications Parameter Conditions/Description Min Nom Max Units VDD Internal supply voltage 3.15 3.3 3.45 V 0.3 x VDD V VDD + 0.5 V 0.45 x VDD V SYNC Line ViL_s LOW level input voltage -0.5 ViH_s HIGH level input voltage Vhyst_s Hysteresis of input Schmitt trigger IoL_s LOW level sink current V(SYNC)=0.5V 14 60 mA Ipu_s Pull-up current source V(SYNC)=0V 300 1000 µA Tr_s Maximum allowed rise time 10/90%VDD 300 ns Cnode_s Added node capacitance 10 pF Freq_s Clock frequency of external SYNC line 0.75 x VDD 0.25 x VDD 5 475 525 Tsynq Sync pulse duration 22 28 T0 Data=0 pulse duration 72 78 kHz % of clock cycle % of clock cycle Inputs: INTL0…INTL4, CCA0…CCA2, EN, ENP, IM Iup_x Pull-up current source V(X)=0 25 110 µA ViL_x LOW level input voltage -0.5 0.3 x VDD V ViH_x HIGH level input voltage 0.7 x VDD VDD+0.5 V Vhyst_x Hysteresis of input Schmitt trigger 0.1 x VDD 0.3 x VDD V RdnL_x External pull down resistance pin forced low 10 kΩ Power Good and OK Inputs/Outputs Iup_PG Pull-up current source V(PG)=0 25 110 µA Iup_OK Pull-up current source V(OK)=0 175 725 µA ViL_x LOW level input voltage -0.5 0.3 x VDD V ViH_x HIGH level input voltage 0.7 x VDD VDD+0.5 V Vhyst_x Hysteresis of input Schmitt trigger 0.1 x VDD 0.3 x VDD V IoL_x LOW level sink current at 0.5V 4 20 mA 0.84 3.10 mA -0.5 0.3 x VDD V VDD+0.5 V 0.45 x VDD V 60 mA 100 ns Current Share/Sense Bus Iup_CS Pull-up current source at V(CS)=0V ViL_CS LOW level input voltage ViH_CS HIGH level input voltage Vhyst_CS Hysteresis of input Schmitt trigger IoL_CS LOW level sink current V(CS)=0.5V Tr_CS Maximum allowed rise time 10/90% VDD REV. 1.2 MAR 14, 2007 www.power-one.com 0.75 x VDD 0.25 x VDD 14 Page 7 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 5. Typical Performance Characteristics 5.1 Efficiency Curves 95 90 95 85 80 Efficiency, % Efficiency, % 90 85 75 70 65 80 60 55 75 Vout=0.5V Vout=1.2V 50 Vout=2.5V 0 1.5 3 Vout=0.5V Vout=1.2V Vout=3.3V Vout=5.0V 4.5 70 6 7.5 9 10.5 Vout=2.5V 12 13.5 15 5 5.5 Output Current, A 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 Output Current, A Figure 4. Efficiency vs. Load. Vin=12V Figure 2. Efficiency vs. Load. Vin=3.3V 95 100 90 Efficiency, % Efficiency, % 95 90 85 85 80 75 80 70 Vin=3.3V 75 70 Vout=0.5V Vout=1.2V Vout=2.5V Vout=3.3V Vin=5V Vin=12V 65 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Output Voltage, V 0 1.5 3 4.5 6 7.5 9 10.5 12 13.5 15 Output Current, A Figure 5. Efficiency vs. Output Voltage, Iout=15A Figure 3. Efficiency vs. Load. Vin=5V REV. 1.2 MAR 14, 2007 www.power-one.com Page 8 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 5.3 95 Turn-Off Characteristics 90 Efficiency, % 85 80 75 70 65 3 4 Vout=0.5V Vout=1.2V Vout=2.5V Vout=3.3V 5 6 7 8 Input Voltage, V 9 10 11 12 Figure 6. Efficiency vs. Input Voltage. Iout=15A 5.2 Figure 8. Tracking Turn-Off Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3 Turn-On Characteristics 5.4 Transient Response The pictures below show the deviation of the output voltage in response to the 50-75-50% step load at 1.0A/µs. In all tests the POL converters had 5x22µF ceramic capacitors and a 220µF tantalum capacitor connected across the output pins. The speed of the transient response was optimized by selecting appropriate CCA settings. Figure 7. Tracking Turn-On. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3 Figure 9. Vin=12V, Vout=1V. CCA=07 REV. 1.2 MAR 14, 2007 www.power-one.com Page 9 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output Figure 10. Vin=12V, Vout=2.5V. CCA=05 Figure 13. Vin=5V, Vout=2.5V. CCA=03 Figure 11. Vin=12V, Vout=5V, CCA=05 Figure 14. Vin=3.3V, Vout=1V. CCA=03 Figure 12. Vin=5V, Vout=1V. CCA=03 REV. 1.2 MAR 14, 2007 www.power-one.com Page 10 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 5.5 Thermal Derating Curves 15 14 Output Current, A 13 12 11 10 9 8 7 6 0LFM 100LFM 200LFM 400LFM 600LFM 5 45 55 65 Ambient Temperature, Degree C 75 85 Figure 15. Thermal Derating Curves. Vin=12V, Vout=5.0V 15 14 Output Current, A 13 12 11 10 9 8 7 6 0LFM 100LFM 200LFM 400LFM 600LFM 5 45 55 65 Ambient Temperature, Degree C 75 85 Figure 16. Thermal Derating Curves. Vin=14V, Vout=5.0V REV. 1.2 MAR 14, 2007 www.power-one.com Page 11 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 6. Typical Application Figure 17. Complete Schematic of Application with Three Independent Outputs. Intermediate Bus Voltage is from 8V to 14V. In this application four POL converters are configured to deliver three independent output voltages. POL1 and POL2 are connected in parallel for increased output current. Output voltages are programmed with the resistors connected between TRIM and VREF pins of individual converters. POL1 is configured as a master (IM and INTL0…INTL4 pins are grounded) and all other POL converters are synchronized to the switching frequency of POL1. Interleave is programmed with pins INTL0…INTL4 to ensure the lowest input and output noise. POL2 has 180° phase shift, POL 3 and POL4 have phase shifts of 270° and 90° respectively. All converters are controlled by the common ENABLE signal. Turn-on and turn-off processes of the system are illustrated by pictures in Figure 7 and Figure 8. REV. 1.2 MAR 14, 2007 www.power-one.com Page 12 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 7. Pin Assignments and Description Pin Name Pin No. Pin Type Buffer Type VLDO 1 P IM 2 I TEMP 3 A ENP 4 I DELAY 5 A CCA2 6 I PU CCA1 7 I PU CCA0 8 I PU VREF 9 A EN 10 I Pin Description Low Voltage Dropout PU Interleave Mode Temperature Measurement PU Enable Logic Selection Power-Up Delay Compensation Coefficient Address Bit 2 Compensation Coefficient Address Bit 1 Compensation Coefficient Address Bit 0 Voltage Reference PU Enable Notes Connect to an external voltage source higher than 4.75V, if VIN<4.75V. Connect to VIN, if VIN≥4.75V Tie to PGND for master or leave open to set interleave by INTL0…INTL4 pins Analog voltage proportional to junction temperature of the controller Tie to PGND for Negative logic or leave open for Positive logic Connect a capacitor between the pin and PGND to program the Power-Up delay. Leave open for zero delay Tie to PGND for 0 or leave open for 1 Tie to PGND for 0 or leave open for 1 Tie to PGND for 0 or leave open for 1 To program the output voltage, connect a resistor between VREF and TRIM Polarity is determined by ENP pin Connect to OK pin of other Z-1000 POLs. Leave open, if not used Connect to SYNC pin of other Z-POLs and/or to an external clock generator OK 11 I/O PU Fault Status SYNC 12 I/O PU Frequency Synchronization Line PGOOD 13 I/O PU Power Good TRIM 14 A CS 15 I/O PU Current Share/Sense INTL4 16 I PU Interleave Bit 4 Tie to PGND for 0 or leave open for 1 INTL3 17 I PU Interleave Bit 3 Tie to PGND for 0 or leave open for 1 INTL2 18 I PU Interleave Bit 2 Tie to PGND for 0 or leave open for 1 INTL1 19 I PU Interleave Bit 1 Tie to PGND for 0 or leave open for 1 INTL0 20 I PU Interleave Bit 0 Tie to PGND for 0 or leave open for 1 -VS 21 I PU Negative Voltage Sense Connect to the negative point close to the load +VS 22 I PU Positive Voltage Sense Connect to the positive point close to the load VOUT 23 P Output Voltage PGND 24 P Power Ground VIN 25 P Input Voltage Output Voltage Trim To program the output voltage, connect a resistor between VREF and TRIM Connect to CS pin of other Z-POLs connected in parallel Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up REV. 1.2 MAR 14, 2007 www.power-one.com Page 13 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 8. 8.1 fault occurs. Pulling low the OK input by an external circuitry turns off the POL converter. Pin and Feature Description VLDO, Low Voltage Dropout 8.10 SYNC, Frequency Synchronization Line The input of the internal linear regulator. VVLDO always needs to be greater than 4.75V for normal operation of the POL converter. 8.2 IM, Interleave Mode The input with the internal pull-up resistor. When the pin is left floating, the phase lag of the POL converter is set by INTL0…INTL4 pins. If the pin is pulled low, the phase lag is set to 0°. Pulling all INTL pins and the IM pin low configures a POL converter as a master. The master determines the clock on the SYNC line. 8.3 TEMP, Temperature Measurement The voltage output of the internal temperature sensor measuring junction temperature of the controller IC. Voltage range from 0 to 2V corresponds to the temperature range from -50°C to 150°C. 8.4 ENP, Enable Polarity The input with the internal pull-up resistor. When the ENP pin is pulled low, the control logic of the EN input is inverted. 8.5 DELAY, Power-Up Delay The bidirectional input/output with the internal pull-up resistor. If the POL converter is configured as a master, the SYNC line propagates clock to other POL converters. If the POL converter is configured as a slave, the internal clock recovery circuit synchronizes the POL converter to the clock of the SYNC line. 8.11 PG, Power Good The open drain input/output with the internal pull-up resistor. The pin is pulled low by the POL converter, if the output voltage is outside of the window defined by the Power Good High and Low thresholds. 8.12 TRIM, Output Voltage Trim The input of the TRIM comparator for the output voltage programming. The output voltage can be programmed by a single resistor connected between VREF and TRIM pins. Resistance of the trim resistor can be determined from the equation below: RTRIM = 20 × (5.5 − VOUT ) , kΩ VOUT The input of the POR circuit with the internal pull-up resistor. By connecting a capacitor between the pin and PGND the power-up delay can be programmed. where VOUT is the desired output voltage in Volts. 8.6 If the RTRIM is open or the TRIM pin is shorted to PGND, the VOUT=0.5V. CCA[0:2], Compensation Coefficient Address Inputs with internal pull-ups to select one of 7 sets of digital filter coefficients optimized for various application conditions. 8.7 VREF, Voltage Reference The output of the 2V internal voltage reference that is used to program the output voltage of the POL converter. 8.13 CS, Current Share/Sense Bus The open drain digital input/output with the internal pull-up resistor. The duty cycle of the digital signal is proportional to the output current of the POL converter. External capacitive loading of the pin shall be avoided. 8.14 INTL[0:4], Interleave Bits The input with the internal pull-up resistor. The POL converter is turned off, when the pin is pulled low (see ENP to inverse logic of the Enable function). Inputs with internal pull-up resistors. The encoded address determines the phase lag of the POL converter when the IM pin is left floating. One digit of the address corresponds to the phase lag of 11.25°. 8.9 8.15 –VS and +VS 8.8 EN, Enable OK, Fault Status The open drain input/output with the internal pull-up resistor. The POL converter pulls its OK pin low, if a REV. 1.2 MAR 14, 2007 www.power-one.com The differential voltage input of the POL converter feedback loop. Page 14 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 9. 9.1 RDOWN while the “Margining Up” switch is normally open disconnecting the resistor RUP. Application Information Output Voltage Margining Margining can be implemented either by changing the trim voltage as described in the previous paragraph or by changing the resistance between the REF and TRIM pins. Margining Down Switch (normally closed) Margining Up Switch (normally open) POL REF An alternative configuration of the margining circuit is shown in Figure 19. In the configuration both switches are normally open that may be advantageous in some implementations. R DOWN R UP REF Margining Up Switch (normally open) R TRIM R UP TRIM R TRIM RDOWN TRIM Margining Down Switch (normally open) PGND In the schematic shown in Figure 18, the nominal output voltage is set with the trim resistor RTRIM calculated from the equation in the paragraph 8.12. Resistors RUP and RDOWN are added to margin the output voltage up and down respectively and determined from the equations below. 20 × RTRIM ⎛ 5 × RTRIM − ∆V % ⎞ = ×⎜ ⎟⎟ , kΩ 20 + RTRIM ⎜⎝ ∆V % ⎠ RUP and RDOWN for this configuration are determined from the following equations: RUP = ⎛ ∆V % ⎞ = (20 + RTRIM ) × ⎜ ⎟ , kΩ ⎝ 100 − ∆V % ⎠ where RTRIM is the value of the trim resistor in kΩ and ∆V% is the absolute value of desired margining expressed in percents of the nominal output voltage. During normal operation the resistors are removed from the circuit by the switches. The “Margining Down” switch is normally closed shorting the resistor REV. 1.2 MAR 14, 2007 www.power-one.com 20 × RTRIM ⎛ 5 × RTRIM − ∆V % ⎞ ×⎜ ⎟⎟ , kΩ 20 + RTRIM ⎜⎝ ∆V % ⎠ R DOWN = Caution: R DOWN PGND Figure 19. Alternative Margining Configuration Figure 18. Margining Configuration RUP POL 20 × RTRIM ⎛ 100 − ∆V % ⎞ ×⎜ ⎟ , kΩ 20 + RTRIM ⎝ ∆V % ⎠ Noise injected into the TRIM node may affect accuracy of the output voltage and stability of the POL converter. Always minimize the PCB trace length from the TRIM pin to external components to avoid noise pickup. Refer to No-BusTM POL Converters. Z-1000 Series Application Note on www.power-one.com for more application information on this and other product features. Page 15 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 10. Mechanical Drawings All Dimensions are in mm Tolerances: 0.5-10 ±0.1 10-100 ±0.2 Pin Coplanarity: 0.1 max 32 ±0.30 8 10 25 23 8 ±0.20 14 ±0.30 2.3 1.6 7.7 12.4 16 Pin 1 22 2.03 1.27 2.54 0.4 SMT PICKUP POINT 20.3 Figure 20. Mechanical Drawing REV. 1.2 MAR 14, 2007 www.power-one.com Page 16 of 17 ZY1015 15A No-Bus POL Data Sheet 3V to 14V Input • 0.5V to 5.5V Output 8.6 3.97 10 10 25 3.97 3 23 (x 3) 16.9 14.2 0.8 Pin 1 2.4 22 1.27 2.54 (x 22) Figure 21. Recommended Pad Sizes Figure 22. Recommended PCB Layout for Multilayer PCBs Notes: 1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not designed, intended for use in, or authorized for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems without the express written consent of the respective divisional president of Power-One, Inc. 2. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice. REV. 1.2 MAR 14, 2007 www.power-one.com Page 17 of 17