OKI MSM65512A

E2E1011-27-Y4
¡ Semiconductor
MSM65512A/65P512A
¡ Semiconductor
This
version: Jan. 1998
MSM65512A/65P512A
Previous version: Nov. 1996
High Performance 8-Bit Microcontroller
GENERAL DESCRIPTION
The MSM65512A is a high-performance 8-bit microcontroller that employs OKI original nX-8/
50 CPU core. With a minimum instruction execution time of 400 ns (10MHz clock), the
MSM65512A is capable of high-speed processing, and includes 8K bytes of program memory,
256 bytes of data memory, timers and serial ports. Also available are the MSM65P512A, which
replaces the MSM65512's built-in program memory with one-time PROM, and the MSM65X512A,
which uses external program memory.
FEATURES
• Operating range
Operating frequency
Operating voltage
Operating temperature
• Memory space
Internal program memory
Internal data memory
• Minimum instruction execution time
• Powerful instruction set
• Abundant addressing modes
• Multiplication/division operation functions
• I/O ports
Input-output port
• Timers
• Counters
• Capture input
• Compare output
• Serial ports
• External interrupts
• Interrupt sources
• Package
40-pin plastic DIP (DIP40-P-600-2.54)
: 0 to 10 MHz (VDD=4.5 to 5.5 V)
0 to 5 MHz (VDD=2.7 to 5.5 V)
: 2.7 to 5.5 V
: –40 to +85°C (Operation at +125°C is
assured by the other specification.)
: 64K bytes
: 8K bytes
: 256 bytes
: 400 ns @ 10 MHz
: 83 basic instructions
8/16-bit operation instructions
Bit manipulation instructions
Compound function instructions
: 8 ¥ 8 Æ 16
16/8 Æ 16 ... 8
: 4 ports ¥ 8 bits
: 8-bit auto-reload timer ¥ 2
16-bit auto-reload timer ¥ 1
Watchdog timer ¥ 1
: Time base counter ¥ 1
16-bit free-running counter ¥ 1
: 1 channel
: 2 channels
: Shift register ¥ 1
Serial port with baud rate generator
(UART/synchronous) ¥ 1
: 3
: 15
: (MSM65512A-¥¥¥RS,
MSM65P512A-¥¥¥RS)
44-pin plastic QFP (QFP44-P-910-0.80-2K)
: (MSM65512A-¥¥¥GS-2K,
MSM65P512A-xxxGS-2K)
44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27): (MSM65512A-¥¥¥JS,
MSM65P512A-¥¥¥JS)
¥¥¥ indicates the code number.
1/23
OSC
CONT.
AD0-7*
8
A8-15*
RD
WR*
ALE
EA
8
BUS
CONT.
IR
8
BR
RAM
(256 bytes)
GMAR
PC
ALU
T/C
AR
8
CPU CORE
INST.
DEC.
VDD
GND
EXT.MEM.
CONT.
8
PSW
SP
LMAR
TBC
WDT
16-bit TIMER
T2CK*
16-bit FRC
CAP¥1, CMP¥2
CAP*
CMP0*
CMP1*
SIO
8-bit TIMER¥3**
MUL/DIV
¡ Semiconductor
ROM
(8K bytes)
BLOCK DIAGRAM
OSC 0
OSC 1
RESET
HSTOP*
I/O PORT
8-bit SHIFT-REG.
P0 P1 P2 P3
2/23
* Secondary functions of ports.
** One timer is used for the SIO
baud rate generator
T1OUT*
T0CK*
GATE*
SFTO*
SFTI*
SFTCK*
INT0*
INT1*
INT2*
MSM65512A/65P512A
INTERRUPT CONT.
TXD*
RXD*
¡ Semiconductor
MSM65512A/65P512A
PIN CONFIGURATION (TOP VIEW)
P3.0/T2CK
1
40
VDD
P3.1/CAP
2
39
P0.0/AD0
P3.2/CMP0
3
38
P0.1/AD1
P3.3/CMP1
4
37
P0.2/AD2
P3.4/INT2
5
36
P0.3/AD3
P3.5/SFTO
6
35
P0.4/AD4
P3.6/SFTI
7
34
P0.5/AD5
P3.7/SFTCK
8
33
P0.6/AD6
RESET
9
32
P0.7/AD7
P2.0/RXD 10
P2.1/TXD 11
31
30
EA
ALE
P2.2/INT0 12
29
RD
P2.3/INT1/GATE 13
28
P1.7/A15
P2.4/T0CK
14
27
P1.6/A14
P2.5/HSTOP
15
26
P1.5/A13
P2.6/WR
16
25
P1.4/A12
P2.7/T1OUT
OSC1
17
18
24
23
P1.3/A11
P1.2/A10
OSC0
19
22
P1.1/A9
GND 20
21
P1.0/A8
40-Pin Plastic DIP
3/23
¡ Semiconductor
MSM65512A/65P512A
34 NC
35 P0.3/AD3
36 P0.2/AD2
37 P0.1/AD1
39 VDD
40 P3.0/T2CK
41 P3.1/CAP
42 P3.2/CMP0
43 P3.3/CMP1
44 P3.4/INT2
38 P0.0/AD0
PIN CONFIGURATION (TOP VIEW) (Continued)
NC
1
33 P0.4/AD4
P3.5/SFTO
2
32 P0.5/AD5
P3.6/SFTI
3
31 P0.6/AD6
P3.7/SFTCK
4
30 P0.7/AD7
RESET
5
29 EA
P2.0/RXD
6
28 ALE
P2.1/TXD
7
27 RD
P2.2/INT0
8
26 P1.7/A15
P2.3/INT1/GATE
9
25 P1.6/A14
P2.4/T0CK 10
24 P1.5/A13
23 NC
P1.4/A12 22
P1.3/A11 21
P1.1/A9 19
P1.2/A10 20
*VDD 17
P1.0/A8 18
GND 16
OSC0 15
OSC1 14
P2.7/T1OUT 13
P2.6/WR 12
P2.5/HSTOP 11
* No-connection pin for MSM65P512A
NC: No-connection pin
44-Pin Plastic QFP
4/23
¡ Semiconductor
MSM65512A/65P512A
29 P1.5/A13
30 P1.6/A14
27 P1.4/A12
26 P1.3/A11
25 P1.2/A10
24 P1.1/A9
23 P1.0/A8
22 GND
21 OSC0
20 OSC1
19 P2.7/T1OUT
NC 17
P2.5/HSTOP 16
18 P2.6/WR
P2.4/T0CK 15
33 ALE
34 EA
35 P0.7/AD7
36 P0.6/AD6
37 P0.5/AD5
31 P1.7/A15
28 NC
P2.3/INT1/GATE 14
NC 6
P2.2/INT0 13
P3.4/INT2 5
P2.1/TXD 12
P3.3/CMP1 4
P2.0/RXD 11
P3.1/CAP 2
P3.2/CMP0 3
RESET 10
VDD 44
P3.0/T2CK 1
P3.7/SFTCK 9
P0.0/AD0 43
38 P0.4/AD4
,
39 NC
P0.1/AD1 42
P3.6/SFTI 8
P0.2/AD2 41
P3.5/SFTO 7
P0.3/AD3 40
32 RD
PIN CONFIGURATION (TOP VIEW) (Continued)
NC: No-connection pin
44-Pin Plastic QFJ (PLCC)
5/23
¡ Semiconductor
MSM65512A/65P512A
PIN DESCRIPTIONS
Basic Functions
Function
Symbol
Power
Supply
VDD
—
+5V power supply
GND
—
0V digital ground
OSC0
I
Crystal oscillation input/external clock input
OSC1
O
Crystal oscillation output
RESET
I
System reset input (program starts from address 0040H);
internal pull-up resistor
EA
I
Program memory select input pin.
"L" level input for external program memory; "H" level input
for internal program memory.
RD
O
Read strobe signal during external memory access
ALE
O
Address latch signal during external memory access
PORT 0
I/O
8-bit Input-output port
During external memory access, becomes address/data bus for address
output, instruction fetch or data read/write along with ALE,
RD and WR pins
PORT 1
I/O
8-bit Input/output port
Address bus during external memory access
PORT 2
PORT 3
I/O
8-bit Input/output port ¥ 2. Secondary functions shown in following table are
added for ports 2 and 3.
Oscillation
Type
Control
Description
Port
6/23
¡ Semiconductor
MSM65512A/65P512A
Secondary Functions
Symbol
Type
Description
RXD
I/O
P2.0 secondary functions
UART: Input pin for serial port receive data.
Synchronous: Input/output pin for serial port transmit/receive data.
TXD
O
P2.1 secondary functions
UART: Output pin for serial port transmit data.
Synchronous: Output pin for serial port synchronizing clock.
INT0
I
P2.2 secondary function
External interrupt 0 input pin.
INT1/GATE
I
P2.3 secondary functions
External interrupt 1 input pin. Also used as input pin for gate signal
for timer 0 count enable/disable.
T0CK
I
P2.4 secondary function
Timer 0 external clock input pin.
HSTOP
I
P2.5 secondary function
Hard stop mode input pin; stops system clock oscillation with "L" level input.
WR
O
P2.6 secondary function
Write strobe signal output pin during external data memory access.
T1OUT
O
P2.7 secondary function
Output pin for signal obtained by dividing timer overflow by 2.
T2CK
I
P3.0 secondary function
Timer 2 external clock input pin.
CAP
I
P3.1 secondary function
Capture trigger input pin.
CMP0
O
P3.2 secondary function
Compare output channel 0 output pin.
CMP1
O
P3.3 secondary function
Compare output channel 1 output pin.
INT2
I
P3.4 secondary function
External interrupt 2 input pin
SFTO
O
P3.5 secondary function
Shift register data output pin.
SFTI
I
P3.6 secondary function
Shift register data input pin.
SFTCK
I/O
P3.7 secondary function
Shift register synchronizing clock input/output pin.
7/23
¡ Semiconductor
MSM65512A/65P512A
Port Circuit Configuration
Type
Port
Data Bus
PORT0
P0D
1
Electrical Characteristics
(VDD=5V)
Circuit Configuration
P0.0/AD0P0.7/AD7
P0
DIR
"H" Output Voltage:
• VOH=3.75V
• IOH=–400mA
"L" Output Voltage:
• VOL=0.4V
• IOL=3.2mA
External Memory Control
Data Bus
PORT1
P1D
2
P1.0/A8P1.7/A15
"H" Input Voltage:
• VIH=2.4V
"L" Input Voltage:
• VIL=0.8V
"H" Input Voltage:
• VIH=2.4V
"L" Input Voltage:
• VIL=0.8V
"H" Output Voltage:
• VOH=3.75V
• IOH=–200mA
P1
DIR
"L" Output Voltage:
• VOL=0.4V
• IOL=1.6mA
External Memory Control
"H" Input Voltage:
• VIH=2.4V
"L" Input Voltage:
• VIL=0.8V
Data Bus
3
P2.0/RXD,
P2.1/TXD,
P2.6/WR,
P2.7/T1OUT,
P3.2/CMP0,
P3.3/CMP1,
P3.5/SFT0,
P3.7/SFTCK
Px
MOD
Secondary
Output
Function
PORTx
PxD
Px
DIR
Secondary
Input
Function
(x=2 to 5)
P2.6/WR
"H" Output Voltage:
• VOH=3.75V
• IOH=–400mA
"L" Output Voltage:
• VOL=0.4V
• IOL=3.2mA
Excluding P2.6/WR
"H" Output Voltage:
• VOH=3.75V
• IOH=–200mA
"L" Output Voltage:
• VOL=0.4V
• IOL=1.6mA
8/23
¡ Semiconductor
MSM65512A/65P512A
Port Circuit Configuration (Continued)
Type
4
Port
P2.2/INT0,
P2.3/INT1/GATE,
P2.4/T0CK,
P2.5/HSTOP,
P3.0/T2CK,
P3.1/CAP,
P3.4/INT2,
P3.6/SFTI
Electrical Characteristics
(VDD=5V)
Circuit Configuration
Data Bus
PORTx
PxD
Px
DIR
Secondary
Input Function
(x=2 to 5)
"H" Input Voltage:
• VIH=2.4V
"L" Input Voltage:
• VIL=0.8V
"H" Output Voltage:
• VOH=3.75V
• IOH=–200mA
"L" Output Voltage:
• VOL=0.4V
• IOL=1.6mA
9/23
¡ Semiconductor
MSM65512A/65P512A
MEMORY MAPS
General Memory Space
0FFFFH
External Memory
Local Memory Space
17FH
Page 1
Data Memory
2000H
100H
Program Memory
100H
SFR
Internal Memory
80H
Vector Call Table Area
Data Memory
40H
30H
20H
10H
0
Page 0
Local Register Set 3
Local Register Set 2
Local Register Set 1
Local Register Set 0
80H
Program Memory
40H
20H Interrupt Vector Table Area
0 Vector Call Table Area
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Symbol
Rating
VDD
Input Voltage
VI
Output Voltage
VO
Power Dissipation
PD
Storage Temperature
Condition
TSTG
Unit
–0.3 to 7.0
Ta=25°C
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
Ta=25°C per package
400
Ta=25°C per output
50
—
–55 to +150
°C
Unit
mW
RECOMMENDED OPERATING CONDITIONS
Symbol
Condition
Range
VDD
Refer to Figure 1.
2.7 to 5.5
Memory Hold Voltage
VDDMH
fOSC=0 Hz
2.0 to 5.5
Oscillation Operating
Frequency *1
fOSC
Refer to Figure 1.
1 to 10
MHz
External Clock Operating
Frequency
fEXTCLK
Refer to Figure 1.
0 to 10
MHz
Operating Temperature
Top
—
–40 to +85
°C
Parameter
Supply Voltage
V
*1 This is due to the standard of a crystal oscillator or ceramic resonator.
10/23
¡ Semiconductor
MSM65512A/65P512A
Ta=–40 to +85°C
fOSC, fEXTCLK (MHz)
10
8
6
5
4
2
1
* Oscillates at 1MHz or more.
2
3
2.7
4
5
5.5
6
VDD (V)
Figure 1. Operating Frequency vs. Power Supply Voltage
11/23
¡ Semiconductor
MSM65512A/65P512A
ELECTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD=4.5 to 5.5V)
(GND=0V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
"H" Input Voltage 1 *1
VIH1
"H" Input Voltage 2 *2
VIH2
—
2.4
—
VDD+0.3
—
0.7VDD
—
VDD+0.3
"L" Input Voltage
VIL
—
–0.3
—
0.8
"H" Output Voltage 1 *3
VOH1
IOH=–200mA
0.75VDD
—
—
"H" Output Voltage 2
*4
VOH2
IOH=–400mA
0.75VDD
—
—
"L" Output Voltage 1
*3
VOL1
IOL=1.6mA
—
—
0.4
"L" Output Voltage 2
*4
Unit
V
VOL2
IOL=3.2mA
—
—
0.4
Input Leakage Current 1
*5
ILI1
VI=VDD/0V
—
—
±1
Input Leakage Current 2
*6
ILI2
VI=VDD/0V
—
—
±10
IIL
VI=0V
–40
–200
–400
CI
f=1MHz, Ta=25°C
—
5
—
pF
IDDS
5V, Stop mode *8
—
—
50
mA
IDDS
10MHz, 5V, no load *9
—
20
40
mA
"L" Input Current
*7
Input Capacitance
Current Consumption
mA
Excluding OSC0 and RESET
OSC0 and RESET
Excluding P0, ALE, RD, P2.6/WR
P0, ALE, RD, P2.6/WR
EA
Excluding RESET, EA
RESET
The ports configured as inputs should be coupled to VDD or 0V. Other ports should not be
loaded.
*9 Refer to Figure 2.
*1
*2
*3
*4
*5
*6
*7
*8
12/23
¡ Semiconductor
MSM65512A/65P512A
DC Characteristics 2 (2.7£ VDD<4.5V)
(GND=0V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
"H" Input Voltage 1 *1
VIH1
—
0.5VDD+0.2
—
VDD+0.3
"H" Input Voltage 2 *2
VIH2
—
0.6VDD+0.4
—
VDD+0.3
"L" Input Voltage
VIL
—
–0.3
—
0.15VDD+0.1
"H" Output Voltage 1 *3
VOH1
IOH=–10mA
0.75VDD
—
—
"H" Output Voltage 2
*4
VOH2
IOH=–20mA
0.75VDD
—
—
"L" Output Voltage 1
*3
VOL1
IOL=10mA
—
—
0.1
"L" Output Voltage 2
*4
Unit
V
VOL2
IOL=20mA
—
—
0.1
Input Leakage Current 1
*5
ILI1
VI=VDD/0V
—
—
±1
Input Leakage Current 2
*6
ILI2
VI=VDD/0V
—
—
±10
IIL
VDD=2.7 to 3.3V, VI=0V
–40
–120
–240
CI
f=1MHz, Ta=25°C
—
5
—
pF
IDDS
3V, Stop mode *8
—
—
25
mA
IDD
5MHz, 3V, no load *9
—
6
15
mA
"L" Input Current
*7
Input Capacitance
Current Consumption
mA
Excluding OSC0 and RESET
OSC0 and RESET
Excluding P0, ALE, RD, P2.6/WR
P0, ALE, RD, P2.6/WR
EA
Excluding RESET, EA
RESET
The ports configured as inputs should be coupled to VDD or 0V. Other ports should not be
loaded.
*9 Refer to Figure 2.
*1
*2
*3
*4
*5
*6
*7
*8
13/23
¡ Semiconductor
MSM65512A/65P512A
10MHz
50
Max.
IDD (mA)
40
30
Typ.
20
10
2
3
4
5
VDD (V)
6
6MHz
50
IDD (mA)
40
Max.
30
20
Typ.
10
2
3
4
5
VDD (V)
6
2MHz
50
IDD (mA)
40
30
20
Max.
10
Typ.
2
3
4
5
VDD (V)
6
Ta=–40 to +85°C, no load
Figure 2. Operating Current Consumption vs. Power Supply Voltage
14/23
¡ Semiconductor
MSM65512A/65P512A
AC Characteristics
• External memory control
(VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C)
Parameter
Clock Cycle
Symbol
Condition
tC
Max.
100
—
45
—
"L" Clock Pulse Width
tCLW
"H" Clock Pulse Width
tCHW
45
—
tC
200
—
90
—
Clock Cycle
VDD=4.5 to 5.5V
Min.
"L" Clock Pulse Width
tCLW
"H" Clock Pulse Width
tCHW
90
—
ALE Pulse Width
tAW
tC+tCHW–20
—
ALE Pulse Delay Time 1
tALD1
tCLW–20
—
ALE Pulse Delay Time 2
tALD2
tCLW–20
—
RD Pulse Width
tRW
tC+tCHW–40
—
RD Pulse Delay Time
tRD
tCLW–40
tCLW+20
WR Pulse Width
tWW
tC+tCHW–40
—
WR Pulse Delay Time
tWD
tCLW–20
tCLW+40
"L" Address Setup Time
tLAS
tC–40
—
"H" Address Setup Time
tHAS
tC–40
—
"L" Address Hold Time
tLAH
tCLW–20
—
Bus Float Time
tLAZ
—
20
"H" Address Hold Time
tHAHR
tC–20
—
"H" Address Hold Time
tHAHW
tC–20
—
Read Data Access Time
tRDAA
—
tC+tCLW–15
Read Data Access Time
tRDAR
—
tCHW+10
Read Data Hold Time
tRDH
0
—
Write Data Setup Time
tWDS
tC+tCLH–40
—
Write Data Hold Time
tWDH
tCLW–20
—
VDD=2.7 to 5.5V
CL=100pF
Unit
ns
15/23
¡ Semiconductor
MSM65512A/65P512A
tCHW
tC
OSC0
tCLW
tAW
ALE
tRD
tRW
tALD1
RD
tRDAR
tLAS
P0
tLAH
tRDH
tLAZ
INST or
DATA IN
ADDRESS L
tRDAA
tHAS
tHAHR
P1
ADDRESS H
tWD
tWW
tALD2
tWDS
tWDH
WR
P0
ADDRESS L
DATA OUT
tHAHW
P1
ADDRESS H
16/23
¡ Semiconductor
MSM65512A/65P512A
• CPU control
(VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C)
Parameter
RESET Pulse Width *1
RESET Pulse Width *2
Symbol
tRESW1
tRESW2
Condition
—
—
Min.
Max.
Unit
20
*3
—
ns
—
—
*1 Excluding power ON, stop mode and hard stop mode.
*2 During power ON, in stop mode and hard stop mode.
*3 Oscillation stabilization time depends on resonator.
RESET pulse width
tRESW1, 2
RESET
• Peripheral control 1
Symbol
OSC
Clock Cycle
tC
EXI
External Interrupt Pulse
Width
T0
T2
CAP
*
(VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C)
Parameter
Condition
Min.
Max.
VDD=4.5 to 5.5V
100
—
VDD=2.7 to 5.5V
tEXIW
200
4 tC
—
—
External Clock Pulse
Width
tT0CW
4 tC
—
GATE Pulse Width
tT0GW
1 tTOCLK *
—
External Clock Pulse
Width
tT2CW
4 tC
—
CAP Pulse Width
tCAPW
12 tC
—
—
Unit
ns
tT0CLK : Timer 0 count clock cycle selected by T0CON.
17/23
¡ Semiconductor
MSM65512A/65P512A
tC
OSC0
tCLW
1) EXI pulse width
tEXIW
INT0-2
2) T0
tT0CW
T0CK
tT0GW
GATE
3) T2
tT2CW
T2CK
4) CAP
tCAPW
CAP
18/23
¡ Semiconductor
MSM65512A/65P512A
• Peripheral control 2
(VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C)
Parameter
OSC
SFT
Symbol
Condition
Min.
Max.
VDD=4.5 to 5.5V
100
200
—
Clock Cycle
tC
SFTCK Cycle
tSFC
8 tC
—
SFTCK "L" Pulse Width
tSFCLW
4 tC–20
—
SFTCK "H" Pulse Width
tSFCHW
4 tC–20
—
SFTCK Setup Time
tSFOS
tSFCLW–100
—
SFTO Hold Time
tSFOH
tSFCHW–100
—
SFTI Setup Time
tSFIS
100
—
SFTI Hold Time
Synchronous Clock Cycle
Synchronous Clock "L"
Pulse Width
tSFIH
tSIC
100
8 tC
—
—
tSICLW
4 tC–20
—
tSICHW
4 tC–20
—
tSIOS
6 tC–100
—
tSIOH
2 tC–100
—
Input Data Setup Time
tSIIS
tC+tCLW+100
—
Input Data Hold Time
tSIIH
0
—
SIO
(Clock Synchronous Clock "H"
Syn- Pulse Width
chro- Output Data Setup Time
nous)
Output Data Hold Time
VDD=2.7 to 5.5V
CL=100pF
Unit
—
ns
19/23
¡ Semiconductor
MSM65512A/65P512A
1) SFT
tSFC
tSFCLW
tSFCHW
tSFOS
tSFOH
tSFIS
tSFIH
SFTCK
SFTO
SFTI
2) SIO
(Clock synchronous mode)
tSIC
tSICLW
tSICHW
tSIOS
tSIOH
tSIIS
tSIIH
TXD
RXD (transmission)
RXD (reception)
20/23
¡ Semiconductor
MSM65512A/65P512A
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
6.10 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
21/23
¡ Semiconductor
MSM65512A/65P512A
(Unit : mm)
QFP44-P-910-0.80-2K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
0.41 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
22/23
¡ Semiconductor
MSM65512A/65P512A
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
Cu alloy
Solder plating
5 mm or more
2.00 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
23/23