a Adjustable Output Ultralow IQ, 200 mA, SOT-23, anyCAP™ Low Dropout Regulator ADP3331 FEATURES High Accuracy Over Line and Load: ⴞ0.7% @ +25ⴗC, 1.4% Over Temperature Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA Can Be Used as a High Current (>1 A) LDO Controller Requires Only CO = 0.47 F for Stability anyCAP = Stable with Any Type of Capacitor (Including MLCC) Current and Thermal Limiting Low Noise Low Shutdown Current: <2 A 2.6 V to 12 V Supply Range 1.5 V to 10 V Output Range –40ⴗC to +85ⴗC Ambient Temperature Range Ultrasmall Thermally Enhanced Chip-on-Lead™ SOT-23-6 Lead Package APPLICATIONS Cellular Telephones Notebook, Palmtop Computers Battery Powered Systems PCMCIA Regulator Bar Code Scanners Camcorders, Cameras FUNCTIONAL BLOCK DIAGRAM Q1 IN OUT ADP3331 THERMAL PROTECTION CC ERR FB DRIVER Q2 gm SD BANDGAP REF GND ERR ADP3331 VIN OUT IN C1 0.47mF EOUT R3 330kV VOUT R1 + + SD FB GND C2 0.47mF R2 ON OFF Figure 1. Typical Application Circuit GENERAL DESCRIPTION The ADP3331 is a member of the ADP330x family of precision low dropout anyCAP voltage regulators. The ADP3331 operates with an input voltage range of 2.6 V to 12 V and delivers a load current up to 200 mA. The ADP3331 stands out from the conventional LDOs with a novel architecture and an enhanced process that enables it to offer performance advantages and higher output current than its competition. Its patented design requires only a 0.47 µF output capacitor for stability. This device is insensitive to capacitor Equivalent Series Resistance (ESR), and is stable with any good quality capacitor, including ceramic (MLCC) types for space restricted applications. The ADP3331 achieves exceptional accuracy of ± 0.7% at room temperature and ± 1.4% overall accuracy over temperature, line and load variations. The dropout voltage of the ADP3331 is only 140 mV (typical) at 200 mA. This device also includes a safety current limit, thermal overload protection and a shutdown feature. In shutdown mode, the ground current is reduced to less than 2 µA. The ADP3331 has ultralow quiescent current 34 µA (typical) in light load situations. The SOT-23-6 package has been thermally enhanced using Analog Device’s proprietary Chip-on-Lead feature to maximize power dissipation. anyCAP and Chip-on-Lead are trademarks of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (@TA = –40ⴗC to +85ⴗC, VIN = 7 V, CIN = 0.47 F, COUT = 0.47 F, unless otherwise ADP3331–SPECIFICATIONS noted) 1, 2 Parameter Symbol 3 OUTPUT VOLTAGE ACCURACY HIGH OUTPUT VOLTAGE RANGE Conditions VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM ≥ 2.35 V, IL = 0.1 mA to 200 mA, TA = +25°C VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM ≥ 2.35 V, IL = 0.1 mA to 150 mA, TA = –40°C to +85°C VIN = VOUTNOM + 0.25 V to 12 V, VOUTNOM ≥ 2.35 V, IL = 0.1 mA to 200 mA, TA = –20°C to +85°C OUTPUT VOLTAGE ACCURACY3 LOW OUTPUT VOLTAGE RANGE VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 200 mA, TA = +25°C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 150 mA, TA = –40°C to +85°C VIN = 2.6 V to 12 V, VOUTNOM = 1.5 V to 2.35 V, IL = 0.1 mA to 200 mA, TA = –20°C to +85°C Min Typ Max Units –0.7 +0.7 % –1.4 +1.4 % –1.4 +1.4 % –0.7 +0.7 % –1.4 +1.4 % –1.4 +1.4 % ∆VO ∆VIN VIN = VOUTNOM +0.25 V to 12 V TA = +25°C 0.06 mV/V ∆VO ∆IL IL= 0.1 mA to 200 mA TA = +25°C 0.04 mV/mA GROUND CURRENT IGND IL = 200 mA, TA = –20°C to +85°C IL = 150 mA IL = 50 mA IL = 0.1 mA 1.6 1.2 0.4 34 4.0 3.1 1.1 50 mA mA mA µA GROUND CURRENT IN DROPOUT IGND VIN = VOUTNOM – 100 mV IL = 0.1 mA 37 55 µA DROPOUT VOLTAGE VDROP VOUT = 98% of V OUTNOM IL = 200 mA, TA = –20°C to +85°C IL = 150 mA IL = 10 mA IL = 1 mA 0.14 0.11 0.042 0.025 0.23 0.17 0.06 0.052 V V V V LINE REGULATION LOAD REGULATION PEAK LOAD CURRENT ILDPK VIN = VOUTNOM + 1 V 300 mA OUTPUT NOISE VNOISE f = 10 Hz–100 kHz, CL = 10 µF IL = 200 mA, CNR = 10 nF, VOUT = 3 V f = 10 Hz–100 kHz, CL = 10 µF IL = 200 mA, CNR = 0 nF, VOUT = 3 V 47 µV rms 95 µV rms SHUTDOWN THRESHOLD VTHSD ON OFF 2.0 0.4 V V SHUTDOWN PIN INPUT CURRENT ISD 0 < SD ≤ 12 V 0 < SD ≤ 5 V 1.9 1.4 9 6 µA µA GROUND CURRENT IN SHUTDOWN MODE IGNDSD SD = 0 V, VIN = 12 V 0.01 2 µA –2– REV. 0 ADP3331 Parameter Symbol Conditions OUTPUT CURRENT IN SHUTDOWN MODE IOSD ERROR PIN OUTPUT LEAKAGE ERROR PIN OUTPUT “LOW” VOLTAGE Min Typ Max Units TA = +25°C @ VIN = 12 V TA = +85°C @ V IN = 12 V 1 2 µA µA IEL VEO = 5 V 1 µA VEOL ISINK = 400 µA 0.40 V 0.19 NOTES 1 Ambient temperature of +85°C corresponds to a junction temperature of +125°C under typical full load test conditions. 2 Application stable with no load. 3 Assumes the use of ideal resistors. Overall accuracy also depends on the tolerance of the external resistors used to set the output voltage. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . . . –0.3 to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Ambient Temperature Range . . . . –40°C to +85°C Operating Junction Temperature Range . . . –40°C to +125°C θJA␣ (4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . 165°C/W θJA␣ (2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . 190°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C Pin Name Function 1 OUT 2 3 IN ERR 4 5 GND FB 6 SD Output of the Regulator. Bypass to ground with a 0.47 µF or larger capacitor. Regulator Input. Open Collector Output that goes low to indicate that the output is about to go out of regulation. Ground. Feedback Input. Connect to an external resistor divider which sets the output voltage. Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. ORDERING GUIDE Model Output Voltage Package Option ADP3331ART ADJ RT-6 (SOT-23-6) Marking Code L9B PIN CONFIGURATION OUT 1 IN 2 ADP3331 6 SD 5 FB TOP VIEW ERR 3 (Not to Scale) 4 GND CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3331 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE ADP3331–Typical Performance Characteristics 3.010 IL = 10mA 3.002 3.000 IL = 50mA 2.998 IL = 100mA 2.996 2.994 IL = 200mA 2.992 2.990 3.25 4 5 IL = 150mA 6 7 8 9 10 INPUT VOLTAGE – Volts 3.003 VOUT = 3V 40 GROUND CURRENT – mA OUTPUT VOLTAGE – Volts IL = 0mA 3.004 45 VOUT = 3.0V VIN = 7V 3.004 3.006 3.002 3.001 3.000 2.999 2.998 2.997 2.996 11 12 Figure 2. Line Regulation Output Voltage vs. Supply Voltage Figure 3. Output Voltage vs. Load Current 0.4 IL = 50mA 0.2 IL = 150mA 0.1 IL = 200mA 0.0 0.2 0 50 100 150 OUTPUT LOAD – mA 200 Figure 5. Ground Current vs. Load Current –0.1 –45 –25 –5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE – 8C Figure 6. Output Voltage Variation % vs. Junction Temperature 2 4 6 8 10 INPUT VOLTAGE – Volts 12 Figure 7. Ground Current vs. Junction Temperature 3.5 200 150 100 50 0 25 50 75 100 125 150 175 200 OUTPUT LOAD – mA Figure 8. Dropout Voltage vs. Output Current VOUT = 3V SD = VIN RL = 15V 3.0 CL = 0.47mF VOUT – Volts INPUT/OUTPUT VOLTAGE – Volts 250 0 0 3.0 VIN = 7V 2.8 IL = 200mA 2.6 2.4 2.2 IL = 150mA 2.0 1.8 IL = 100mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 IL = 50mA 0.2 IL = 0mA 0 –45 –25 –5 15 35 55 75 95 115 135 JUNCTION TEMPERATURE – 8C 2.5 2.0 3 2 0 1.0 10 0.5 0 0 1.0 2.0 3.0 TIME – Sec 4.0 5.0 Figure 9. Power-Up/Power-Down –4– CL = 10mF 1 1.5 VIN – Volts 0 GROUND CURRENT – mA 0.3 OUTPUT VOLTAGE – % GROUND CURRENT – mA 1.4 0.6 10 Figure 4. Ground Current vs. Supply Voltage IL = 0mA 0.8 15 50 75 100 125 150 175 200 OUTPUT LOAD – mA 0.4 1.0 20 5 25 IL = 0mA 25 0 VIN = 7V 1.2 30 2.994 0 IL = 100mA 35 2.995 1.6 INPUT/OUTPUT VOLTAGE – mV OUTPUT VOLTAGE – Volts 3.005 VOUT = 3.0V 3.008 VIN = 7V VOUT = 3V SD = VIN RL = 15V 5 0 0 100 200 300 TIME – ms 400 500 Figure 10. Power-Up Response REV. 0 ADP3331 3.100 3.040 3.000 VOUT = 3V RL = 15V CL = 0.47mF 2.960 3.050 Volts VOUT – Volts VOUT – Volts 3.040 3.000 VOUT = 3V RL = 15V CL = 10mF 2.960 VIN = 7V VOUT = 3V CL = 0.47mF 2.950 2.920 2.920 3.000 2.900 7.5 7.0 0 100 200 300 TIME – ms 400 100 200 300 TIME – ms 400 3 0 0 500 2 VOUT mA 200 0 VERR 3 0 100 100 2 VIN = 7V 20mA VSD 0 0 0 200 400 600 800 0 0 1000 TIME – ms Figure 14. Load Transient Response CL = 0.47mF IL = 0.1mA 400 600 TIME – ms RMS NOISE – mV CL = 0.47mF IL = 200mA –50 –60 CL = 10mF IL = 200mA –70 100 1k 10k 100k FREQUENCY – Hz IL = 0mA IL = 200mA WITH NOISE REDUCTION 40 CL = 10mF IL = 0.1mA –80 100 60 20 1M 10M Figure 17. Power Supply Ripple Rejection 0 0 1000 Figure 16. Turn On–Turn Off Response CL = 0.47mF CNR = 0 IL = 200mA 80 800 1 120 –30 REV. 0 200 140 –20 –90 10 0 160 VOUT = 3.0V –10 –40 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TIME – Sec Figure 15. Short Circuit Current 0 1000 1 IOUT 300 200 800 VIN = 7V VOUT = 3V CL = 10mF RL = 15V 3 400 2.900 600 VOUT Volts 2.950 400 Figure 13. Load Transient Response 500 VIN = 7V VOUT = 3V CL = 10mF 200 TIME – ms Figure 12. Line Transient Response 3.000 RIPPLE REJECTION – dB 20mA 0 VOLTAGE NOISE SPECTRAL DENSITY – mV/ Hz Volts 3.050 100 7.0 0 Volts 3.100 mA 7.5 500 Figure 11. Line Transient Response mA VIN – Volts VIN – Volts 200 CL = 10mF CNR = 0 CL = 0.47mF CNR = 10nF 0.1 CL = 10mF CNR = 10nF VOUT = 3.0V IL = 200mA IL = 0mA WITH NOISE REDUCTION 10 20 30 CL – mF 40 Figure 18. RMS Noise vs. CL (10 Hz–100 kHz) –5– 50 0.01 10 100 1k 10k FREQUENCY – Hz 100k Figure 19. Output Noise Density 1M ADP3331 ESR. The innovative design allows the circuit to be stable with just a small 0.47 µF capacitor on the output. Additional advantages of the pole-splitting scheme include superior line noise rejection and very high regulator gain. The high gain leads to excellent regulation, and ± 1.4% accuracy is guaranteed over line, load and temperature. THEORY OF OPERATION The new ADP3331 anyCAP LDO uses a single control loop for both regulation and reference functions as shown in Figure 20. The output voltage is sensed by an external resistive voltage divider consisting of R1 and R2. Feedback is taken from this network by way of a series diode (D1) and a second resistor divider (R3 and R4) to the input of an amplifier. Additional features of the circuit include current limit, thermal shutdown and an error flag. Compared to standard solutions that give a warning after the output has lost regulation, the ADP3331 provides improved system performance by enabling the ERR pin to give a warning just before the device loses regulation. OUTPUT INPUT COMPENSATION CAPACITOR Q1 NONINVERTING WIDEBAND DRIVER gm ATTENUATION (VBANDGAP/VOUT) R3 PTAT VOS R1 D1 (a) R4 PTAT CURRENT CLOAD As the chip’s temperature rises above +165°C, the circuit activates a soft thermal shutdown to reduce the current to a safe level. The thermal shutdown condition is indicated by the ERR signal going low. RLOAD R2 ADP3331 APPLICATION INFORMATION Capacitor Selection GND Output Capacitor: The stability and transient response of the LDO is a function of the output capacitor. The ADP3331 is stable with a wide range of capacitor values, types and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is needed for stability; larger capacitors can be used if high current surges on the output are anticipated. The ADP3331 is stable with extremely low ESR capacitors (ESR ≈ 0), such as Multilayer Ceramic Capacitors (MLCC) or OSCON. Note that the effective capacitance of some capacitor types fall below the minimum over temperature or with DC voltage. Figure 20. Functional Block Diagram A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that at equilibrium it produces a large, temperature-proportional input “offset voltage” that is repeatable and very well controlled. The temperatureproportional offset voltage is combined with the complementary diode voltage to form a “virtual bandgap” voltage, implicit in the network, although it never appears explicitly in the circuit. Ultimately, this patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise design. Input Capacitor: An input bypass capacitor is not strictly required but it is recommended in any application involving long input wires or high source impedance. Connecting a 0.47 µF capacitor from the input to ground reduces the circuit’s sensitivity to PC board layout and input transients. If a larger output capacitor is necessary, a larger value input capacitor is also recommended. The R1, R2 divider is chosen in the same ratio as the bandgap voltage to output voltage. Although the R1, R2 resistor divider is loaded by the diode D1 and a second divider consisting of R3 and R4, the values are chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider so that the error resulting from the base current loading in conventional circuits is avoided. Noise Reduction Capacitor: A noise reduction capacitor can be used to reduce the output noise by 6 dB to 10 dB. This capacitor limits the noise gain when connected between the feedback pin (FB) and the output pin (OUT) as shown in Figure 21. Low leakage capacitors in the 10 pF to 500 pF range provide the best performance. Since FB is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible and long PC board traces are not recommended. When adding a noise reduction capacitor, use the following guidelines: The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. The use of this special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type and ESR of the load capacitor. Most LDOs place strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize due to the uncertainty of the load capacitance and resistance. Moreover, the ESR value required to keep conventional LDOs stable, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. • Maintain a minimum load current of 1 mA when not in shutdown • For CNR values greater than 500 pF, add a 100 kΩ series resistor (RNR). It is important to note that as CNR increases, the turn-on time will be delayed. With CNR values greater than 1 nF, this delay may be on the order of several milliseconds. This is no longer true with the ADP3331. It can be used with any good quality capacitor, with no constraint on the minimum –6– REV. 0 ADP3331 ERR ADP3331 R3 OUT VIN IN C1 + 0.47mF R1 SD FB GND divider network to achieve the best performance. Using standard values as shown in Table I will sacrifice some temperature stability. EOUT R NR C NR VOUT +C2 0.47mF Output Current Limit The ADP3331 is short circuit protected by limiting the pass transistor’s base drive current. The maximum output current is limited to about 300 mA. R2 ON Thermal Overload Protection OFF The ADP3331 is protected against damage due to excessive power dissipation by its thermal overload protection circuit. Thermal protection limits the die temperature to a maximum of +165°C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where the die temperature starts to rise above +165°C, the output current will be reduced until the die temperature has dropped to a safe level. Figure 21. Noise Reduction Circuit Output Voltage The ADP3331 has an adjustable output voltage that can be set by an external resistor divider. The output voltage will be divided by R1 and R2, and then fed back to the FB pin. Refer to Figure 21. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, the device’s power dissipation should be externally limited so that the junction temperature will not exceed 125°C. In order to have the lowest possible sensitivity of the output voltage to temperature variations, it is important that the parallel resistance of R1 and R2 is always 230 kΩ: R1 × R2 = 230 kΩ R1 + R2 Chip-on-Lead The ADP3331 uses a patented Chip-on-Lead package design to ensure the best thermal performance in an SOT-23 footprint. The standard SOT-23 depends on the majority of the heat to flow out of the ground pin. The Chip-on-Lead package uses an electrically isolated die attach, which allows all the pins to contribute to heat conduction. This technique reduces the thermal resistance to 190°C/W on a 2-layer board as compared to >230°C/W for a standard SOT-23 lead frame. Figure 22 shows the difference between the standard SOT-23 and the Chip-onLead lead frames. Also, for the best accuracy over temperature the feedback voltage should set for 1.204 V: R2 VOUT = VFB R1 + R2 where VOUT is the desired output voltage and VFB is the “virtual bandgap” voltage. Note that VFB does not actually appear at the FB pin due to loading by the internal PTAT current. Combining the above equations and solving for R1 and R2 gives the following formulas: V R1 = 230 OUT kΩ VFB R2 = SILICON DIE 230 kΩ VFB 1 − V OUT NORMAL SOT-23-6 PACKAGE THERMALLY ENHANCED CHIP-ON-LEAD PACKAGE Figure 22.␣ Chip-on-Lead Package Calculating Junction Temperature The output voltage can be adjusted to any voltage from 1.5 V to 10 V. For example, the Feedback Resistor Selection Table shows some representative feedback resistor values for output voltages in the specified range. Device power dissipation is calculated as follows: PD = (VIN – VOUT) ILOAD + (VIN ) IGND Where ILOAD and IGND are load current and ground current, VIN and VOUT are the input and output voltages respectively. Table I. Feedback Resistor Selection VOUT R1 (1% Resistor) R2 (1% Resistor) 1.5 V 1.8 V 2.2 V 2.7 V 3.3 V 5V 9V 243 kΩ 340 kΩ 422 kΩ 511 kΩ 634 kΩ 953 kΩ 1.00 MΩ 1.00 MΩ 698 kΩ 511 kΩ 412 kΩ 365 kΩ 301 kΩ 154 kΩ Assuming the worst case operating conditions are ILOAD = 200 mA, IGND = 4 mA, V IN = 4.2 V and VOUT = 3.0 V, the device power dissipation is: PD = (4.2 V – 3.0 V) 200 mA + (4.2 V) 4 mA = 257 mW The proprietary package used on the ADP3331 has a thermal resistance of 165°C/W when placed on a 4-layer board, and 190°C/W when placed on a 2-layer board. This allows the ambient temperature to be significantly higher for a given power dissipation than with a standard package. Assuming a 4-layer board, the junction temperature rise above ambient will be approximately equal to: Output voltages above 5 V and below 1.6 V will require nonstandard resistor values or adding an additional resistor to the REV. 0 SILICON DIE WITH ELECTRICALLY ISOLATED DIE ATTACH ∆TJA = 0.257 W × 165°C/W = 42.4°C –7– ADP3331 To limit the junction temperature to 125°C, the maximum allowable ambient temperature is: conjunction with the preload and noise reduction capacitor. Further increases in the output capacitance may be acceptable if the output already has a sizable load during start-up. TA(MAX) = +125°C – 42.4°C = +82.6°C The ADP3331 can source up to 200 mA without any heat sink or pass transistor. If higher current is needed, an appropriate pass transistor can be used, as in Figure 23, to increase the output current to 1 A. Applying a TTL level high signal to the shutdown (SD) pin, or tying it to the input pin, will turn the output ON. Pulling the SD to 0.4 V or below, or tying it to ground, will turn the output OFF. In shutdown mode, the quiescent current is reduced to less than 1 µA. VIN = 3.3V Error Flag Dropout Detector C1 47mF The ADP3331 will maintain its output voltage over a wide range of load, input voltage, and temperature conditions. If the output is about to lose regulation, due to the input voltage approaching the dropout level, the error flag will be activated. The ERR output is an open collector, which will be driven low. MJE253* VOUT = 1.8V @ 1A R1 50V IN OUT C2 10mF ADP3331 SD Once set, the ERR flag’s hysteresis will keep the output low until a small margin of operating range is restored either by raising the supply voltage or reducing the load. C3624–2.5–6/99 Higher Output Current Shutdown Mode 340kV FB GND ERR 698kV *REQUIRES HEAT SINK Low Voltage Applications In applications where the output voltage is 2.2 V or less, the ADP3331 may begin to exhibit some turn-on overshoot. The degree of overshoot is determined by several factors: the output voltage setting, the output load, the noise reduction capacitor, and the output capacitor. Printed Circuit Board Layout Considerations The output voltage setting is determined by the application and cannot be tailored for minimum overshoot. In general, for output voltages 2.2 V or less, the overshoot becomes larger as the output voltage decreases. 1. PC board traces with larger cross sectional areas will remove more heat from the ADP3331. For optimum heat transfer, specify thick copper and use wide traces. Figure 23. High Output Current Linear Regulator Use the following general guidelines when designing printed circuit boards: 2. The thermal resistance can be decreased by approximately 10% by adding a few square centimeters of copper area to the lands connected to the pins of the LDO. The output load is also determined by the system requirements. However, if the ADP3331 has no load on the output during start-up, a small amount of preload can be added to minimize overshoot. A preload of 2 µA to 20 µA is recommended. 3. The feedback pin is a high impedance input, and care should be taken when making a connection to this pin. The voltage setting resistors and noise reduction network must be located as close as possible. Long PC board traces are not recommended. Avoid routing traces near possible noise sources. A noise reduction capacitor, if not already being used, is suggested to reduce the overshoot. Values in the range of 10 pF to 100 pF works best along with the preload suggested previously. The output capacitor can be adjusted to minimize the overshoot. Values in the 0.47 µF to 1.0 µF range should be used in OUTLINE DIMENSIONS Dimensions shown in inches and (mm). PRINTED IN U.S.A. 6-Lead Surface Mount RT-6 (SOT-23-6) 0.122 (3.10) 0.106 (2.70) 0.071 (1.80) 0.059 (1.50) 6 5 4 1 2 3 0.118 (3.00) 0.098 (2.50) PIN 1 0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.059 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE –8– 10° 0.009 (0.23) 0° 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) REV. 0