W312-02 FTG for VIA™ K7 Series Chipset with Programmable Output Frequency Features • Single chip FTG solution for VIA™ K7 Series chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog timer for system recovery • Automatically switch to HW selected or SW programmed clock frequency when watchdog timer time-out • Capable of generate system RESET after a watchdog timer time-out occurs or a change in output frequency via SMBus interface • Support SMBus byte read/write and block read/ write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength for PCI output clocks • Programmable output skew between CPU, AGP and PCI • Maximized EMI suppression using Cypress’s Spread Spectrum technology • • • • • • • • Low jitter and tightly controlled clock skew Two pairs of differential CPU clocks Eleven copies of PCI clocks Three copies of 66-MHz outputs Two copies of 48-MHz outputs Three copies of 14.31818-MHz reference clocks One RESET output for system recovery Power management control support Key Specifications CPU Outputs Cycle-to-cycle Jitter: ............................. 250 ps 48-MHz, 3V66, PCI Outputs Cycle-to-cycle Jitter: ....................................................500 ps CPU, 3V66 Output Skew:............................................ 200 ps 48-MHz Output Skew: ................................................. 250 ps PCI Output Skew:........................................................ 500 ps [1] Block Diagram Pin Configuration VDD_REF X1 X2 XTAL OSC REF0/FS0* PLL REF FREQ SMBus Logic VDD_CPU Divider, Delay, and Phase Control Logic CPUT0,CPUC0 2 CPUT_CS,CPUC_CS VDD_AGP AGP0:2 3 (FS0:4) VDD_PCI PCI0/SEL24_48#* PLL 1 PCI1:8 5 PD# CPU_STOP# PCI_STOP# AGP_STOP# REF_STOP# PCI9_E RST# VDD_48MHz 48MHz/FS3* PLL2 24_48MHz/FS4* /2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W312-02 SDATA SCLK VDD_REF GND_REF X1 X2 VDD_48MHz *FS2/48MHz *FS3/24_48MHz GND_48MHz *FS4/PCI_F *SEL24_48#/PCI0 PCI1 GND_PCI PCI2 PCI3 VDD_PCI PCI4 PCI5 PCI6 GND_PCI PCI7 PCI8 PCI9_E VDD_PCI RST# REF2 REF1/FS1* 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/FS0* REF1/FS1* REF2 REF_STOP#* AGP_STOP#* GND_CPU CPUT0 CPUC0 VDD_CPU CPUT_CS CPUC_CS GND_CPU CPU_STOP#* PCI_STOP#* PD#* VDD_CORE GND_CORE SDATA SCLK GND_AGP AGP2 AGP1 AGP0 VDD_AGP Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. SEL24_48#* Cypress Semiconductor Corporation Document #: 38-07259 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 19, 2002 W312-02 I Pin Definitions Pin No. Pin Type REF0/FS0 48 I/O Reference Clock Output 0/Frequency Select 0: 3.3V 14.318-MHz clock output. REF0 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 4. REF1/FS1 47 I/O Reference Clock Output 0/Frequency Select 1: 3.3V 14.318-MHz clock output. REF1 will be disabled when REF_STOP# is active. This pin also serves as the select strap to determines device operating frequency as described in Table 4. REF2 46 I/O Reference Clock Output 2: 3.3V 14.318-MHz clock output. REF2 will be disabled when REF_STOP# is active. X1 3 I Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 4 I Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI_F/FS4 9 I Free-Running PCI Clock/Frequency Select 4: 3.3V 33-MHz free running PCI clock output. This pin also serves as the select strap to determines device operating frequency as described in Table 4. PCI_0/SEL24_48# 10 I/O PCI Clock 0/Select 24 or 48 MHz: 3.3V 33-MHz PCI clock outputs. This output will be disabled when PCI_STOP# is active. This pin also serves as the select strap to determine device operating frequency of 24_48MHz output. PCI1:8 11, 13, 14, 16, 17, 18, 20, 21 O PCI Clock 1 through 8: 3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled when PCI_STOP# is active. PCI9_E 22 O Early PCI Clock 9: 3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled when PCI_STOP# is active. AGP0:2 26, 27, 28 O AGP Clock 0 through 2: 3.3V 66-MHz clock outputs. The operating frequency is controlled by FS0:4 (see Table 4). AGP0:2 will be disabled when AGP_STOP# is active. 48MHz/FS2 6 I/O 48-MHz Output/Frequency Selection 3: 3.3V 48-MHz non-spread spectrum output. 48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 4. 24_48MHz/FS3 7 I/O 24 or 48-MHz Output/Select 24 or 48 MHz: 3.3V 24 or 48-MHz non-spread spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This pin also serves as the select strap to determine device operating frequency as described in Table 4. RST# 24 Pin Name Pin Description Reset#: Open-drain RESET# output. O (opendrain) CPUT0, CPUC0 42, 41 CPUT_CS, CPUC_CS 39, 38 O CPU Clock Output for Chipset: CPUT_CS and CPUC_CS are the differential CPU clock outputs for the chipset. They are push-pull outputs. These outputs will be disabled when CPU_STOP# is active. CPU_STOP# 36 I CPU STOP Input: This input will disable CPUT_CS and CPUC_CS when it is active. PCI_STOP# 35 I PCI STOP Input: This input will disable PCI0:8 and PCI9_E when it is active. AGP_STOP# 44 I AGP STOP Input: This input will disable AGP0:2 when it is active. REF_STOP# 45 I REF STOP Input: This input will disable REF0:2, 24_48MHz and 48 MHz outputs when it is active. Document #: 38-07259 Rev. *B O CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock out(open- puts for the K7 processor. They are open-drain outputs. drain) Page 2 of 21 W312-02 Pin Definitions (continued) Pin No. Pin Type PD# 34 I SDATA 31 I/O Data pin for SMBus circuitry. SCLK 30 I Clock pin for SMBus circuitry. VDD_CPU 40 P 2.5V Power Connection: Power supply for CPU output buffers. Connect to 2.5V. VDDQ_AGP 25 P 3.3V Power Connection: Power supply for AGP output buffers. Connect to 3.3V. VDDQ_PCI 15, 23 P 3.3V Power Connection: Power supply for PCI output buffers. Connect to 3.3V. VDDQ_48MHz 5 P 3.3V Power Connection: Power supply for 48 MHz output buffers. Connect to 3.3V. VDD_REF 1 P 3.3V Power Connection: Power supply for reference output buffers. Connect to 3.3V. VDD_Core 33 P 3.3V Power Connection: Power supply for PLL core. Connect to 3.3V. 2, 8, 29, 32, 37, 43 G Ground Connections: Connect all ground pins to the common system ground plane. Pin Name GND_REF, GND_48MHz, GND_PCI, GND_AGP, GND_Core, GND_CPU Document #: 38-07259 Rev. *B Pin Description Power-Down Input: This input will trigger the clock generator into Power Down mode when it is active. Page 3 of 21 W312-02 Serial Data Interface The W312-02 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol supports byte/word write, byte/word read, block write and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. For byte/word write and byte read operations, system controller can access individual indexed byte. The offset of the indexed byte is encoded in the command code. The definition for the command code is defined in Table 1. Bit Descriptions 7 0 = Block read or block write operation 1 = Byte/Word read or byte/word write operation 6:0 Byte offset for byte/word read or write operation. For block read or write operations, these bits need to be set at ‘0000000’. Table 1. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bits ‘00000000’ stands for block operation Block Read Protocol Bit 1 2:8 9 10 11:18 Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits ‘00000000’ stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave Data byte 0 – 8 bits Acknowledge from slave Data byte 1 – 8 bits 46 Acknowledge from slave ... Data Byte N/Slave Acknowledge... ... Data Byte N – 8 bits ... Acknowledge from slave ... Stop Document #: 38-07259 Rev. *B 21:27 28 29 30:37 38 39:46 47 48:55 Slave address – 7 bits Read Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits 56 Acknowledge ... Data bytes from slave/Acknowledge ... Data byte N from slave – 8 bits ... Not Acknowledge ... Stop Page 4 of 21 W312-02 Table 2. Word Read and Word Write Protocol Word Write Protocol Bit 1 2:8 Description Start Word Read Protocol Bit 1 Slave address – 7 bits 2:8 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 Command Code – 8 bits ‘1xxxxxxx’ stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte or word operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte low – 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 29:36 Data byte high –- 8 bits 28 Read 37 Acknowledge from slave 29 Acknowledge from slave 38 Stop 30:37 38 39:46 Slave address – 7 bits Data byte low from slave – 8 bits Acknowledge Data byte high from slave – 8 bits 47 NOT acknowledge 48 Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeat start 28 Acknowledge from slave 29 Stop 21:27 Read 29 Acknowledge from slave 30:37 Document #: 38-07259 Rev. *B Slave address – 7 bits 28 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Page 5 of 21 W312-02 W312-02 Serial Configuration Map 2. All unused register bits (reserved and N/A) should be written to a “0” level. 1. The serial bits will be read by the clock driver in the following order: 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register 0 Bit Pin# Bit 7 – Name Spread Enable Default 0 Description 0 = Disabled 1 = Enabled Bit 6 – Spread Select2 0 ‘000’ = ±0.25% ‘001’ = –0.5% Bit 5 – Spread Select1 0 Bit 4 – Spread Select0 0 ‘010’ = ±0.5% ‘011’ = ±0.38% ‘100’ = Reserved ‘101’ = Reserved ‘110’ = Reserved ‘111’ = Reserved Bit 3 – SEL3 0 Bit 2 – SEL2 0 Bit 1 – SEL1 0 Bit 0 – SEL0 0 SW Frequency selection bits. See Table 4. Byte 1: Control Register 1 Bit Pin# Name Default Description Bit 7 42, 41 CPUT0, CPUC0 1 (Active/Inactive) Bit 6 39, 38 CPUT_CS, CPUC_CS 1 (Active/Inactive) Bit 5 6 48MHz 1 (Active/Inactive) Bit 4 7 24_48MHz 1 (Active/Inactive) Bit 3 – Reserved 0 Reserved Bit 2 28 AGP2 1 (Active/Inactive) Bit 1 27 AGP1 1 (Active/Inactive) Bit 0 26 AGP0 1 (Active/Inactive) Document #: 38-07259 Rev. *B Page 6 of 21 W312-02 Byte 2: Control Register 2 Bit Pin# Name Default Description Bit 7 20 PCI7 1 (Active/Inactive) Bit 6 18 PCI6 1 (Active/Inactive) Bit 5 17 PCI5 1 (Active/Inactive) Bit 4 16 PCI4 1 (Active/Inactive) Bit 3 14 PCI3 1 (Active/Inactive) Bit 2 13 PCI2 1 (Active/Inactive) Bit 1 11 PCI1 1 (Active/Inactive) Bit 0 10 PCI0 1 (Active/Inactive) Byte 3: Control Register Bit Pin# Name Default Description Bit 7 9 PCI_F 1 (Active/Inactive) Bit 6 22 PCI9_E 1 (Active/Inactive) Bit 5 – Reserved 0 Reserved Bit 4 21 PCI8 1 (Active/Inactive) Bit 3 46 REF2 1 (Active/Inactive) Bit 2 – Reserved 0 Reserved Bit 1 47 REF1 1 (Active/Inactive) Bit 0 48 REF0 1 (Active/Inactive) Byte 4: Watchdog Timer Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – FS_Override 0 0 = Select operating frequency by FS[4:0] input pins 1 = Select operating frequency by SEL[4:0] settings Bit 5 – WD_TIMER4 1 Bit 4 – WD_TIMER3 1 Bit 3 – WD_TIMER2 1 Bit 2 – WD_TIMER1 1 Bit 1 – WD_TIMER0 1 These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the prescaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. Bit 0 – WD_PRE_SCAL ER 0 Document #: 38-07259 Rev. *B 0 = 150 ms 1 = 2.5 sec Page 7 of 21 W312-02 Byte 5: Control Register 5 Bit Pin# Name Default Description Bit 7 9 Latched FS4 input X Latched FS[4:0] inputs. These bits are read only. Bit 6 7 Latched FS3 input X Bit 5 6 Latched FS2 input X Bit 4 47 Latched FS1 input X Bit 3 48 Latched FS0 input X Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 0 Reserved Bit 0 – SEL4 0 SW Frequency selection bits. See Table 4. Byte 6: Reserved Register Bit Name Default Pin Description Bit 7 Reserved 1 Reserved Bit 6 Reserved 1 Reserved Bit 5 Reserved 1 Reserved Bit 4 Reserved 1 Reserved Bit 3 Reserved 1 Reserved Bit 2 Reserved 1 Reserved Bit 1 Reserved 1 Reserved Bit 0 Reserved 1 Reserved Byte 7: Reserved Register Bit Name Default Pin Description Bit 7 Reserved 1 Reserved Bit 6 Reserved 1 Reserved Bit 5 Reserved 1 Reserved Bit 4 Reserved 1 Reserved Bit 3 Reserved 1 Reserved Bit 2 Reserved 1 Reserved Bit 1 Reserved 1 Reserved Bit 0 Reserved 1 Reserved Document #: 38-07259 Rev. *B Page 8 of 21 W312-02 Byte 8: Vendor ID and Revision ID Register (Read Only) Bit Name Default Pin Description Bit 7 Revision_ID3 0 Revision ID bit[3] Bit 6 Revision_ID2 0 Revision ID bit[2] Bit 5 Revision_ID1 0 Revision ID bit[1] Bit 4 Revision_ID0 0 Revision ID bit[0] Bit 3 Vendor_ID3 1 Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 2 Vendor_ID2 0 Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 1 Vendor _ID1 0 Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only. Bit 0 Vendor _ID0 0 Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only. Byte 9: System Reset and Watchdog Timer Register Bit Name Default Pin Description Bit 7 Reserved 0 Reserved Bit 6 PCI_DRV 0 PCI clock output drive strength 0 = Normal 1 = High Drive Bit 5 Reserved 0 Reserved Bit 4 RST_EN_WD 0 This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs. 0 = Disabled 1 = Enabled Bit 3 RST_EN_FC 0 This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled Bit 2 WD_TO_STATU S 0 Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) Bit 1 WD_EN 0 0 = Stop and re-load Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. Bit 0 Reserved 0 Reserved Document #: 38-07259 Rev. *B Page 9 of 21 W312-02 Byte 10: Skew Control Register Bit Name Default Description Bit 7 CPU_Skew2 0 CPU skew control 000 = Normal 001 = –150 ps 010 = –300 ps 011 = –450 ps 100 = +150 ps 101 = +300 ps 110 = +450 ps 111 = +600 ps Bit 6 CPU_Skew1 0 Bit 5 CPU_Skew0 0 Bit 4 Reserved 0 Reserved Bit 3 PCI_Skew1 0 Bit 2 PCI_Skew0 0 PCI skew control 00 = Normal 01 = –500 ps 10 = Reserved 11 = +500 ps Bit 1 AGP_Skew1 0 Bit 0 AGP_Skew0 0 AGP skew control 00 = Normal 01 = –150 ps 10 = +150 ps 11 = +300 ps Byte 11: Recovery Frequency N - Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_N7 0 Bit 6 ROCV_FREQ_N6 0 Bit 5 ROCV_FREQ_N5 0 Bit 4 ROCV_FREQ_N4 0 Bit 3 ROCV_FREQ_N3 0 Bit 2 ROCV_FREQ_N2 0 Bit 1 ROCV_FREQ_N1 0 Bit 0 ROCV_FREQ_N0 0 If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W312-02 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W312-02 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. Document #: 38-07259 Rev. *B Page 10 of 21 W312-02 Byte 12: Recovery Frequency M- Value Register Bit Name Default Pin Description Bit 7 ROCV_FREQ_SEL 0 ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] Bit 6 ROCV_FREQ_M6 0 Bit 5 ROCV_FREQ_M5 0 Bit 4 ROCV_FREQ_M4 0 Bit 3 ROCV_FREQ_M3 0 Bit 2 ROCV_FREQ_M2 0 Bit 1 ROCV_FREQ_M1 0 Bit 0 ROCV_FREQ_M0 0 If ROCV_FREQ_SEL is set, W312-02 will use the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery CPU output frequency.when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W31202 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. W312-02 will change the output frequency whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. Byte 13: Programmable Frequency Select N-Value Register Bit Name Default Pin Description If Prog_Freq_EN is set, W300 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W31202 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 7 CPU_FSEL_N7 0 Bit 6 CPU_FSEL_N6 0 Bit 5 CPU_FSEL_N5 0 Bit 4 CPU_FSEL_N4 0 Bit 3 CPU_FSEL_N3 0 Bit 2 CPU_FSEL_N2 0 Bit 1 CPU_FSEL_N1 0 Bit 0 CPU_FSEL_N0 0 Byte 14: Programmable Frequency Select N-Value Register Bit Name Default Description Bit 7 Pro_Freq_EN 0 Programmable output frequencies enabled 0 = disabled 1 = enabled Bit 6 CPU_FSEL_M6 0 Bit 5 CPU_FSEL_M5 0 Bit 4 CPU_FSEL_M4 0 Bit 3 CPU_FSEL_M3 0 Bit 2 CPU_FSEL_M2 0 Bit 1 CPU_FSEL_M1 0 If Prog_Freq_EN is set, W300 will use the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is updated. The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM. When it is cleared, W312-02 will use the same frequency ratio stated in the Latched FS[4:0] register. When it is set, W31202 will use the frequency ratio stated in the SEL[4:0] register. W312-02 supports programmable CPU frequency ranging from 50 MHz to 248 MHz. Bit 0 CPU_FSEL_M0 0 Document #: 38-07259 Rev. *B Page 11 of 21 W312-02 Byte 15: Reserved Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – Reserved 0 Reserved Bit 5 – Reserved 0 Reserved Bit 4 – Reserved 0 Reserved Bit 3 – Reserved 0 Reserved Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 1 Reserved. Write with ‘1’ Bit 0 – Reserved 1 Reserved. Write with ‘1’ Byte 16: Reserved Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – Reserved 0 Reserved Bit 5 – Reserved 0 Reserved Bit 4 – Reserved 0 Reserved Bit 3 – Reserved 0 Reserved Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 0 Reserved Byte 17: Reserved Register Bit Pin# Name Default Description Bit 7 – Reserved 0 Reserved Bit 6 – Reserved 0 Reserved Bit 5 – Reserved 0 Reserved Bit 4 – Reserved 0 Reserved Bit 3 – Reserved 0 Reserved Bit 2 – Reserved 0 Reserved Bit 1 – Reserved 0 Reserved Document #: 38-07259 Rev. *B Page 12 of 21 W312-02 Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Output Frequency FS4 FS3 FS2 FS1 FS0 SEL4 SEL3 SEL2 SEL1 SEL0 CPU 3V66 PCI PLL Gear Constants (G) 0 0 0 0 0 156.0 78.0 39.0 48.00741 0 0 0 0 1 154.0 77.0 38.5 48.00741 0 0 0 1 0 152.0 76.0 38.0 48.00741 0 0 0 1 1 147.0 73.5 36.8 48.00741 0 0 1 0 0 144.0 72.0 36.0 48.00741 0 0 1 0 1 142.0 71.0 35.5 48.00741 0 0 1 1 0 138.0 69.0 34.5 48.00741 0 0 1 1 1 136.0 68.0 34.0 48.00741 0 1 0 0 0 124.0 62.0 31.0 48.00741 0 1 0 0 1 122.0 61.0 30.5 48.00741 0 1 0 1 0 117.0 78.0 39.0 48.00741 0 1 0 1 1 115.0 76.7 38.3 48.00741 0 1 1 0 0 113.0 75.3 37.7 48.00741 0 1 1 0 1 108.0 72.0 36.0 48.00741 0 1 1 1 0 105.0 70.0 35.0 48.00741 0 1 1 1 1 102.0 68.0 34.0 48.00741 1 0 0 0 0 Reserved Reserved Reserved Reserved 1 0 0 0 1 Reserved Reserved Reserved Reserved 1 0 0 1 0 Reserved Reserved Reserved Reserved 1 0 0 1 1 200.0 66.6 33.3 48.00741 1 0 1 0 0 190.0 76.0 38.0 48.00741 1 0 1 0 1 180.0 72.0 36.0 48.00741 1 0 1 1 0 170.0 68.0 34.0 48.00741 1 0 1 1 1 150.0 75.0 37.5 48.00741 1 1 0 0 0 140.0 70.0 35.0 48.00741 1 1 0 0 1 120.0 60.0 30.0 48.00741 1 1 0 1 0 110.0 73.3 33.3 48.00741 1 1 0 1 1 66.6 66.6 33.3 48.00741 1 1 1 0 0 200.0 66.6 33.3 48.00741 1 1 1 0 1 166.6 66.6 33.3 48.00741 1 1 1 1 0 100.0 66.6 33.3 48.00741 1 1 1 1 1 133.3 66.6 33.3 48.00741 Programmable Output Frequency, Watchdog Timer and Recovery Output Frequency Functional Description The Programmable Output Frequency feature allows users to generate any CPU output frequency from the range of 50 MHz to 248 MHz. Cypress offers the most dynamic and the simplest programming interface for system developers to utilize this feature in their platforms. The Watchdog Timer and Recovery Output Frequency features allow users to implement a recovery mechanism when the system hangs or getting unstable. System BIOS or other control software can enable the Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog timer time-out occurs, a system reset will be generated and a recovery frequency will be activated. All of the related registers are summarized inTable 6. Document #: 38-07259 Rev. *B Page 13 of 21 W312-02 Table 5. Register Summary Name Pro_Freq_EN Description Programmable output frequencies enabled 0 = Disabled (default) 1 = Enabled When it is disabled, the operating output frequency will be determined by either the latched value of FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used. When it is enabled, the CPU output frequency will be determined by the programmed value of CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0] or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between CPU and other frequency outputs FS_Override When Pro_Freq_EN is cleared or disabled, 0 = Select operating frequency by FS input pins (default) 1 = Select operating frequency by SEL bits in SMBus control bytes When Pro_Freq_EN is set or enabled, 0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the latched value of FS input pins (default) 1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are based on the programmed value of SEL bits in SMBus control bytes CPU_FSEL_N, CPU_FSEL_M When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL bits in SMBus control bytes. ROCV_FREQ_SEL ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL. 0 = From latched FS[4:0] 1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] ROCV_FREQ_N[7:0], ROCV_FREQ_M[6:0] When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog timer time-out occurs The setting of FS_Override bit determines the frequency ratio for CPU, AGP and PIC. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers within the same SMBus bus operation. WD_EN 0 = Stop and reload Watchdog timer 1 = Enable Watchdog timer. It will start counting down after a frequency change occurs. WD_TO_STATUS Watchdog Timer Time-out Status bit 0 = No time-out occurs (READ); Ignore (WRITE) 1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE) WD_TIMER[4:0] These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the prescaler. The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set to 150 ms. If the prescaler is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec. When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit. Document #: 38-07259 Rev. *B Page 14 of 21 W312-02 Table 5. Register Summary (continued) Name Description WD_PRE_SCALER 0 = 150 ms 1 = 2.5 sec RST_EN_WD This bit will enable the generation of a Reset pulse when a Watchdog timer time-out occurs. 0 = Disabled 1 = Enabled RST_EN_FC This bit will enable the generation of a Reset pulse after a frequency change occurs. 0 = Disabled 1 = Enabled How to Program CPU Output Frequency When the programmable output frequency feature is enabled (Pro_Freq_EN bit is set), the CPU output frequency is determined by the following equation: Fcpu = G * (N+3)/(M+3) “N” and “M” are the values programmed in Programmable Frequency Select N-Value Register and M-Value Register, respectively. “G” stands for the PLL Gear Constant, which is determined by the programmed value of FS[4:0] or SEL[4:0]. The value is listed in Table 4. The ratio of (N+3) and (M+3) need to be greater than “1” [(N+3)/(M+3) > 1]. Table 6 lists set of N and M values for different frequency output ranges.This example use a fixed value for the M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Table 6. Examples of N and M Value for Different CPU Frequency Range Frequency Ranges Gear Constants Fixed Value for M-Value Register Range of N-Value Register for Different CPU Frequency 50 MHz–129 MHz 48.00741 93 97–255 130 MHz–248 MHz 48.00741 48 127–245 Document #: 38-07259 Rev. *B Page 15 of 21 W312-02 Absolute Maximum Ratings[2] Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. . Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPU =100 MHz Outputs Loaded[3] 260 mA IDD 2.5V Supply Current CPUCS =100 MHz Outputs Loaded[3] 25 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 V VIH Input High Voltage 2.0 VDD + 0.3 V Input Low Current[4] –25 µA Input High Current[4] 10 µA 50 mV IIL IIH Clock Outputs VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA VOL Output Low Voltage CPUT_CS, CPUC_CS, CPUT0, CPUC0 Termination to V pull-up (external) 0 0.3 V VOH Output High Voltage CPUT_CS, CPUC_CS, CPUT0, CPUC0 Termination to V pull-up (external) 1.0 1.2 V IOL Output Low Current PCI, AGP VOL = 1.5V 70 110 135 mA REF VOL = 1.5V 50 70 100 mA 48 MHz VOL = 1.5V 50 70 100 mA IOH Output High Current 3.1 V 24_48 MHz VOL = 1.5V 50 70 100 mA PCI, AGP VOH = 1.5V 70 110 135 mA REF VOH = 1.5V 50 70 100 mA 48 MHz VOH = 1.5V 50 70 100 mA 24_48 MHz VOH = 1.5V 50 70 100 mA Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. All clock outputs loaded with 6" 60Ω transmission lines with 20-pF capacitors. 4. X1 input threshold voltage (typical) is VDD/2. Document #: 38-07259 Rev. *B Page 16 of 21 W312-02 DC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V±5% and 2.5V±5% (continued) Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input Threshold Voltage[4] CLOAD Load Capacitance, Imposed on External Crystal[5] CIN,X1 X1 Input Capacitance[6] VDD = 3.3V Pin X2 unconnected 1.65 V 18 pF TBD pF Pin Capacitance/Inductance CIN Input Pin Capacitance Except X1 and X2 5 pF COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[7] CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. CPU = 133 MHz Max. Unit tR Output Rise Edge Rate CPU_CS 1.0 4.0 Min. 1.0 Typ. 4.0 V/ns tF Output Fall Edge Rate CPU_CS 1.0 4.0 1.0 4.0 V/ns tD Duty Cycle Measured at 50% point 45 55 45 55 % tJC Jitter, Cycle to Cycle fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 3 ms Zo AC Output Impedance VO = VX 50 50 Ω 250 250 ps Notes: 5. The W312-02 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Refer to Figure 1 for K7 operation clock driver test circuit. Document #: 38-07259 Rev. *B Page 17 of 21 W312-02 PCI Clock Outputs (Lump Capacitance Test Load = 30 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 tF Output Fall Edge Rate Measured from 2.4V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle tSK 4 V/ns 1 4 V/ns 45 55 % Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1.5 Ω 30 REF Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description f Frequency, Actual Test Condition/Comments Min. Frequency generated by crystal oscillator Typ. Max. 14.318 Unit MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ω 40 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 48 MHz (48.008 – 48)/48 Min. Typ. Max. Unit 48.008 MHz +167 ppm m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Document #: 38-07259 Rev. *B 57/17 40 Ω Page 18 of 21 W312-02 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 24 MHz (24.004 – 24)/24 Typ. Max. Unit 24.004 MHz +167 ppm m/n PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 57/34 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 40 Ω VDD + V1 1.5V 3.3 Z0 = 52Ω Length = 5” T1 R1 68 Z0 = 52Ω Length = 3” T2 R8 CPUCLK_T 47 20p 1.5V Clock Chip CPUDriver R3 68 Z0 = 52Ω Length = 5” T4 CPUCLK_C Z0 = 52Ω Length = 3” T5 R9 47 20p Figure 1. K7 Open Drain Clock Driver Test Circuit Document #: 38-07259 Rev. *B Page 19 of 21 W312-02 Ordering Information Ordering Code Package Type Product Flow W312-02H 48-pin SSOP Commercial, 0°C to 70°C W312-02HT 48-pin SSOP - Tape and Reel Commercial, 0°C to 70°C Package Drawing and Dimension 48-Lead Shrunk Small Outline Package O48 51-85061-*C VIA is a trademark of VIA Technologies, Inc. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07259 Rev. *B Page 20 of 21 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W312-02 Document History Page Document Title: W312-02 FTG for VIA™ K7 Series Chipset with Programmable Output Frequency Document Number: 38-07259 REV. ECN NO. Issue Date Orig. of Change ** 110524 01/07/02 SZV Change from Spec number: 38-01087 to 38-07259 *A 118014 09/13/02 RGL Changed the KT266 word to K7 Series in the title and features in page 1. Filled up all the missing Byte # and Byte heading description on all the serial configuration tables on pages 6-12. Replaced the package drawing and dimension as per CY standard. Removed the word “PRELIMINARY” *B 122860 12/19/02 RBI Added power-up requirements to maximum ratings information. Document #: 38-07259 Rev. *B Description of Change Page 21 of 21